Patent application number | Description | Published |
20080320267 | Memory Element, Data Processing System, Method for Setting Operating Parameters of a Memory and Computer Program - A memory element includes a memory which is operable according to operating parameters from at least two sets of operating parameter values and an operating parameter control which is implemented to receive operating state information and to select a set of operating parameter values for the operation of the memory based on the operating state information. | 12-25-2008 |
20090002383 | MEMORY FOR PROVIDING A GRAPHIC CONTENT - A memory device comprises a memory array and a processing device. The memory array is configured to store a graphic data set. The processing device is configured to initiate outputting of data of the graphic data set from the memory array and to combine the outputted data in response to a read request for providing a graphic content. | 01-01-2009 |
20090024806 | STORAGE DEVICE, STORAGE CONTROLLER, SYSTEM, METHOD OF STORING DATA, METHOD OF READING DATA AND FILE SYSTEM - A storage device comprises a storage location, an interface coupled to the storage location, and a data conversion circuit coupled to the storage location and to the interface. The interface is configured for an exchange of data between the storage device and external circuitry coupled to the interface. The data conversion circuit is configured for converting data from a first data format to a second data format. The data conversion circuit is configured to convert at least one of data read from the storage location before they are transferred to the interface, and data received via the interface before they are written to the storage location. | 01-22-2009 |
20090129189 | METHOD AND APPARATUS FOR MONITORING A MEMORY DEVICE - A memory device comprising at least a plurality of memory cells and a memory control unit to read and write user data to said memory cells is provided. The memory device comprises further a monitoring unit for retrieving a plurality of data concerning the memory device and a comparing unit. The comparing unit receives an output signal of the monitoring unit and is configured to compare the plurality of retrieved data with a plurality of reference values. | 05-21-2009 |
20090150710 | Memory System With Extended Memory Density Capability - A system including a central processing unit, a first memory channel being configured to couple the central processing unit to a first semiconductor memory unit, wherein the first memory channel is configured to be clocked with a first clock frequency, and a second memory channel being configured to couple the central processing unit to a second semiconductor memory unit, wherein the second memory channel is configured or configurable to be clocked with a second clock frequency smaller than the first clock frequency. | 06-11-2009 |
20090175100 | METHOD AND APPARATUS FOR STORAGE DEVICE WITH A LOGIC UNIT AND METHOD FOR MANUFACTURING SAME - Method and apparatus that relate to a storage device comprising a plurality of memory cells, an interface device configured to connect the storage device to a host system and configured to transmit signals to read and write data from the host system to the memory cells via a first and second data path, and a logic unit. The logic unit is configured to read and write data from the plurality of memory cells via the second data path, and configured to perform logic operations on data stored in the plurality of memory cells. When performing read and write operations, the first data path excludes the logic unit, and the second data path includes the logic unit. Furthermore, the logic unit is communicatively coupled between the interface device and the plurality of memory cells. Additionally, a method for manufacturing the memory device is provided. | 07-09-2009 |
20090175115 | MEMORY DEVICE, METHOD FOR ACCESSING A MEMORY DEVICE AND METHOD FOR ITS MANUFACTURING - Embodiments relates to a memory device, comprising a plurality of memory cells, said memory cells being addressable by a plurality of addresses, an interface for reading and/or writing data from a host system to said memory device, said interface comprising at least an address bus and a clock signal line, said address bus being configured to transmit a first part of an address at the leading edge of said clock signal and a second part of an address at the trailing edge of said clock signal. | 07-09-2009 |
20090190432 | DRAM with Page Access - A DRAM chip with a data I/O-interface of an access width equal to a page size. | 07-30-2009 |
20090267084 | Integrated circuit with wireless connection - An integrated circuit includes a device stack including: a memory device with a first wireless coupling element, and a semiconductor device with a second wireless coupling element. The first and second wireless coupling elements are arranged face-to-face and are configured to provide a wireless connection between the memory device and the semiconductor device. | 10-29-2009 |
20090267678 | Integrated Circuit with Improved Data Rate - An integrated circuit includes: a terminal for outputting data, a driver for providing the data to the terminal, and a switch for selectively connecting/disconnecting the driver to the terminal. The disconnection of the driver reduces the capacitive load on the connection between the terminal and driver, thus reducing limitations on data rate from factors such as data reflections that reduce signal quality. Selective connection/disconnection allows the driver to be reconnected to the terminal only when needed. | 10-29-2009 |
20090271678 | INTERFACE VOLTAGE ADJUSTMENT BASED ON ERROR DETECTION - A method of adjusting an interface voltage includes transferring data between a memory device and a controller, and detecting whether an error occurred in the transfer of data. An interface voltage of at least one of the memory device and the controller is adjusted based on the detection. | 10-29-2009 |
20090287957 | METHOD FOR CONTROLLING A MEMORY MODULE AND MEMORY CONTROL UNIT - A memory control unit for controlling a memory module comprising a plurality of memory cells, said memory control unit comprising means for detecting failure of at least one memory cell, means for deactivating said at least one defective memory cell, means for assigning the address of said at least one defective memory cell to at least one replacement memory cell, first tracking means for tracking the remaining replacement memory cells and masking means to hide the address of a defective memory cell to prevent further usage of this address instead of assigning said address to a replacement memory cell. | 11-19-2009 |
20110034045 | Stacking Technique for Circuit Devices - Stackable circuit devices include mechanical and electrical connection elements that are optionally disengageable and disconnectable. The mechanical connection elements comprise pairs of complementary male and female plug-in engagement elements respectively arranged at opposite matching positions on top and bottom faces of each device package. The male and female plug-in engagement elements provide a mutual plug-in engagement. The electrical connection elements comprise a plurality of first and second complementary contact elements respectively arranged in opposite and matching positions on either the top or bottom face of each device package. When the circuit devices are stacked, the first contact elements are respectively configured to provide an electrical connection to a complementary matching second contact element of an adjacently plugged in circuit device. Some of the stackable circuit devices may accommodate an integrated memory die or chip and others of the stackable circuit devices may include line routing and distribution blocks. | 02-10-2011 |