Shirahige
Yasushi Shirahige, Tokyo JP
Patent application number | Description | Published |
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20140311557 | SEALING MATERIAL SHEET FOR SOLAR CELL MODULES - Provided is a sealing material sheet for solar cell modules, which is obtained by irradiating a polyethylene resin with ionizing radiation and has high transparency, heat resistance and adhesion at the same time. This sealing material sheet for solar cell modules contains a low density polyethylene having a density of 0.900 g/cm | 10-23-2014 |
20150083207 | SEALER SHEET FOR SOLAR-CELL MODULE - The present invention provides a crosslinked polyethylene sealing material sheet for a solar-cell module offering exceptional heat resistance, wherein the sealing material sheet is provided with high metal-adhesion performance. A sealing material sheet for a solar-cell module comprises a sealing material sheet composition for a solar-cell module containing a polyethylene resin in a concentration of 0.900 g/cm3 or less, glycidyl methacrylate (GMA), a radical polymerization initiator, and triallyl isocyanurate (TAIC), wherein the GMA content of the sealing material sheet is 0.15 to 3.0% by mass, the TAIC content of the sealing material sheet is 0.15 to 3.0% by mass, and the radical polymerization initiator content of the sealer is 0.01 to 2.5% by mass. | 03-26-2015 |
Yuji Shirahige, Kawasaki JP
Patent application number | Description | Published |
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20080320229 | PRE-FETCH CONTROL APPARATUS - A pre-fetch control apparatus is equipped with a next-line pre-fetch control apparatus | 12-25-2008 |
20100095071 | Cache control apparatus and cache control method - A cache control apparatus includes a plurality of processing units, each performing, in a mutually independent manner, corresponding processing that constitutes a pipeline process of outputting cache data with respect to requests belonging to threads, holding units, each being disposed corresponding to one of the processing units and each holding a thread-specific valid bit that corresponds to a request under processing in corresponding processing unit and that indicates whether a pipeline process for a thread to which the request under processing belongs is stalled, a storing unit that sequentially stores in a register a request that is under processing in a processing unit corresponding to a holding unit holding a valid bit that indicates pipeline process stalling, and a feeding unit that determines a priority for the request stored in the register by the storing unit and a request newly input from outside, and feeds either one of stored request and newly input request to the processing units. | 04-15-2010 |
20110119535 | PROCESSOR AND METHOD OF CONTROL OF PROCESSOR - A processor including: a first storage unit that stores data; an error detection unit that detects an occurrence of error in data read out from the first storage unit; a second storage unit that stores data read out from the first storage unit based on a load request; a rerun request generation unit that generates a rerun request of a load request to the first storage unit in the same cycle as the cycle in which error of data is detected when the error detection unit detects the occurrence of error in data read out from the first storage unit by the load request; and an instruction execution unit that retransmits the load request to the first storage unit when data in which error is detected and a rerun request are given. | 05-19-2011 |
Yuji Shirahige, Kawasaski JP
Patent application number | Description | Published |
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20130111183 | ADDRESS TRANSLATION APPARATUS, ADDRESS TRANSLATION METHOD, AND CALCULATION APPARATUS | 05-02-2013 |
20140115264 | MEMORY DEVICE, PROCESSOR, AND CACHE MEMORY CONTROL METHOD - A memory device includes a plurality of ways; a register configured to hold an access history of accessing the plurality of ways; and a way control unit configured to select one or more ways among the plurality of ways according to an access request and the access history, put the selected one or more ways in an operation state, and put one or more of the plurality of ways other than the selected one or more ways in a non-operation state. The way control unit dynamically changes a number of the one or more ways to be selected, according to the access request. | 04-24-2014 |
20150052306 | PROCESSOR AND CONTROL METHOD OF PROCESSOR - Lock information indicating that an address is locked and a lock address are held for each thread, and in a case where the execution of a CAS instruction is requested, a primary cache controller which receives a request from an instruction controlling unit which requests processing according to an instruction in each thread executes a plurality of pieces of processing included in the CAS instruction when an access target address of the CAS instruction is different from the lock address of a thread whose lock information is held, and prohibits the execution of store processing of a thread whose lock information is not held, to a cache memory when the lock information of any thread out of the plural threads is held. | 02-19-2015 |