Patent application number | Description | Published |
20140017283 | PORATED CARTILAGE PRODUCTS - This invention provides porated cartilage products, methods of producing porated cartilage products, and methods of treating subjects by administering cartilage products. Optionally, the cartilage products are sized, porated, and digested to provide a flexible cartilage product. Optionally, the cartilage products comprise viable chondrocytes, bioactive factors such as chondrogenic factors, and a collagen type II matrix. Optionally, the cartilage products are non-immunogenic. | 01-16-2014 |
20140017292 | METHODS OF MANUFACTURING CARTILAGE PRODUCTS - This invention provides porated cartilage products and methods of producing porated cartilage products. Optionally, the cartilage products are sized, porated, and digested to provide a flexible cartilage product. Optionally, the cartilage products comprise viable chondrocytes, bioactive factors such as chondrogenic factors, and a collagen type II matrix. Optionally, the cartilage products are non-immunogenic. | 01-16-2014 |
20140030309 | DISRUPTED CARTILAGE PRODUCTS - This invention provides disrupted cartilage products, methods of manufacturing disrupted cartilage products, and methods of treating a subject comprising administering a cartilage product. The cartilage products are manufactured by a method comprising disrupting a collagen matrix, e.g. to produce a flexible cartilage product. Optionally, the cartilage products comprise viable chondrocytes, bioactive factors such as chondrogenic factors, and a collagen type II matrix. Optionally, the cartilage products are non-immunogenic. | 01-30-2014 |
20150017222 | Disrupted Cartilage Products - This invention provides disrupted cartilage products, methods of manufacturing disrupted cartilage products, and methods of treating a subject comprising administering a cartilage product. The cartilage products are manufactured by a method comprising disrupting a collagen matrix, e.g. to produce a flexible cartilage product. Optionally, the cartilage products comprise viable chondrocytes, bioactive factors such as chondrogenic factors, and a collagen type II matrix. Optionally, the cartilage products are non-immunogenic. | 01-15-2015 |
20150140057 | PORATED CARTILAGE PRODUCTS - This invention provides porated cartilage products, methods of producing porated cartilage products, and methods of treating subjects by administering cartilage products. Optionally, the cartilage products are sized, porated, and digested to provide a flexible cartilage product. Optionally, the cartilage products comprise viable chondrocytes, bioactive factors such as chondrogenic factors, and a collagen type II matrix. Optionally, the cartilage products are non-immunogenic. | 05-21-2015 |
Patent application number | Description | Published |
20090130646 | BLOOD COLLECTION DEVICE, METHOD, AND SYSTEM FOR USING THE SAME - Disclosed is a fluid collection device wherein multiple, individual samples of fluid can be collected simultaneously. The device includes a chamber and an adapter which substantially and simultaneously distributes the blood to individual chambers with chamber specific additives. Also included is a system for using the blood collection device, preferably within a diagnostic testing laboratory. | 05-21-2009 |
20100279397 | BIOLOGICAL SPECIMEN COLLECTION AND STORAGE DEVICES - A biological sample containment system and method are provided that include a container for storing the biological sample and an indicator affixed to the container for displaying at least one measured characteristics of the container or sample, wherein measurement of the characteristic is commenced by activation of the indicator. In another embodiment of the invention, a biological sample containment system and method are provided that include a container for storing the biological sample and a colored scale affixed to the container, wherein the colored scale facilitates identification of at least one characteristic of the biological sample. In yet another embodiment of the invention, a biological sample containment system and method are provided that include a container for collecting a biological sample and a label affixed to the container, wherein information relating to the biological sample or container is situated on the label. | 11-04-2010 |
20140328734 | Biological Specimen Collection and Storage Devices - A biological sample containment system and method are provided that include a container for storing the biological sample and an indicator affixed to the container for displaying at least one measured characteristics of the container or sample, wherein measurement of the characteristic is commenced by activation of the indicator. In yet another embodiment of the invention, a biological sample containment system and method are provided that include a container for collecting a biological sample and a label affixed to the container, wherein information relating to the biological sample or container is situated on the label and at least a portion of said information is situated on a face of the label that is affixed to the container. | 11-06-2014 |
Patent application number | Description | Published |
20100176508 | SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF ASSEMBLY THEREOF - A semiconductor die package includes: an assembly including a semiconductor die, a clip structure attached to an upper surface of the semiconductor die, and a heat sink attached to an upper surface of the clip structure; and a molding material partially encapsulating the assembly, wherein an upper surface of the heat sink is exposed through the molding material. | 07-15-2010 |
20110095411 | Wirebond-less Semiconductor Package - A wirebond-less packaged semiconductor device includes a plurality of I/O contacts, at least one semiconductor die, the semiconductor die having a bottom major surface and a top major surface, the top major surface having at least two electrically isolated electrodes, and a conductive clip system disposed over the top major surface, the clip system comprising at least two electrically isolated sections coupling the electrodes to respective I/O contacts. | 04-28-2011 |
20110148376 | MOSFET WITH GATE PULL-DOWN - A MOSFET main switch transistor has a pull-down FET coupled between a drain thereof and the gate of the main switch transistor. A gate of the pull-down FET is coupled to the drain of the main switch transistor by a capacitor and is connected to a source thereof by a resistor. The pull-down FET is operated by capacitive coupling to the voltage drop across the main switch and can be used to hold the gate of the main switch transistor at or near its source potential to avoid or reduce unintentional turn-on of the main switch transistor by the Miller effect. | 06-23-2011 |
20120015483 | Semiconductor Device Package and Method of Assembly Thereof - A semiconductor die package includes: an assembly including a semiconductor die, a clip structure attached to an upper surface of the semiconductor die, and a heat sink attached to an upper surface of the clip structure; and a molding material partially encapsulating the assembly, wherein an upper surface of the heat sink is exposed through the molding material. | 01-19-2012 |
20120200281 | Three-Dimensional Power Supply Module Having Reduced Switch Node Ringing - A high frequency power supply module ( | 08-09-2012 |
20120248521 | Power Converter Having Integrated Capacitor - A power supply module ( | 10-04-2012 |
20120256239 | Ultra-Thin Power Transistor and Synchronous Buck Converter Having Customized Footprint - A packaged power transistor device ( | 10-11-2012 |
20130049077 | High Performance Power Transistor Having Ultra-Thin Package - A field-effect transistor package includes a leadframe with a first linear thickness ( | 02-28-2013 |
20130077250 | DC-DC Converter Vertically Integrated with Load Inductor Structured as Heat Sink - A power supply converter ( | 03-28-2013 |
20140245598 | FABRICATING A POWER SUPPLY CONVERTER WITH LOAD INDUCTOR STRUCTURED AS HEAT SINK - A method for fabricating a power supply converter comprises a load inductor wrapped by a metal sleeve structured to transform the inductor into a heat sink positioned to deposit layers of solder paste on a sleeve surface and on the inductor leads. A metal carrier having a portion of a first thickness and portions of a greater second thickness is placed on the solder layers of the inductor. The carrier portion of first thickness is aligned with the inductor sleeve. The carrier portions of second thickness are aligned with the inductor leads. A sync and a control FET are placed side-by-side on solder layers deposited on the carrier portion of first thickness opposite the inductor sleeve. Reflowing is preformed and the solder layers are solidified. The FETs, the carrier and the inductor become integrated and the un-soldered surfaces of the FETs and the carrier portions of second thickness become coplanar. | 09-04-2014 |
20140247562 | DC-DC CONVERTER VERTICALLY INTEGRATED WITH LOAD INDUCTOR STRUCTURED AS HEAT SINK - An apparatus includes a heat-generating component and a thermally inert component positioned in close proximity to the heat-generating component. A housing for the thermally inert component is in touch with the heat-generating component and is structured to transform the thermally inert component into a heat sink for the heat-generating component | 09-04-2014 |
20160005627 | ULTRA-THIN POWER TRANSISTOR AND SYNCHRONOUS BUCK CONVERTER HAVING CUSTOMIZED FOOTPRINT - A power field-effect transistor package is fabricated. A leadframe including a flat plate and a coplanar flat strip spaced from the plate is provided. The plate has a first thickness and the strip has a second thickness smaller than the first thickness. A field-effect power transistor chip having a third thickness is provided. A first and second contact pad on one chip side and a third contact pad on the opposite chip side are created. The first pad is attached to the plate and the second pad to the strip. Terminals are concurrently attached to the plate and the strip so that the terminals are coplanar with the third contact pad. The thickness difference between plate and strip and spaces between chip and terminals is filled with an encapsulation compound having a surface coplanar with the plate and the opposite surface coplanar with the third pad and terminals. The chip, leadframe and terminals are integrated into a package having a thickness equal to the sum of the first and third thicknesses. | 01-07-2016 |
Patent application number | Description | Published |
20110074007 | THERMALLY ENHANCED LOW PARASITIC POWER SEMICONDUCTOR PACKAGE - A method and structure for a dual heat dissipating semiconductor device. A method includes attaching a drain region on a first side of a die, such as a power metal oxide semiconductor field effect transistor (MOSFET) to a first leadframe subassembly. A source region and a gate region on a second side of the die are attached to a second leadframe subassembly. The first leadframe subassembly is attached to a third leadframe subassembly, then the device is encapsulated or otherwise packaged. An exposed portion of the first leadframe subassembly provides an external heat sink for the drain region, and the second leadframe subassembly provides external heat sinks for the source region and the gate region, as well as output leads for the gate region. The third leadframe subassembly provides output leads for the drain region. | 03-31-2011 |
20130087900 | Thermally Enhanced Low Parasitic Power Semiconductor Package - A semiconductor device includes a source region, a gate region and a drain region. A first leadframe subassembly is coupled to the drain region. on a second side of the die are attached to a second leadframe subassembly. A second leadframe subassembly has a first portion electrically coupled with the source region and a second portion electrically coupled with the gate region. The first leadframe subassembly is attached to a third leadframe subassembly. A die is interposed between the first leadframe subassembly and the second leadframe subassembly. The height of the third leadframe subassembly provides a standoff for a distance between the first leadframe subassembly and the second leadframe subassembly. | 04-11-2013 |
20130278328 | POWER TRANSISTOR PARTIAL CURRENT SENSING FOR HIGH PRECISION APPLICATIONS - A power transistor module including a power transistor with a first common power node, and a split control node. A first clip is connected to a portion of a second power node so that current through a first control segment of the control node is directed through a first transistor portion and through the first clip. A second clip is connected to another portion of the second power node so that current through a second control segment is directed through a second transistor portion and through the second clip. A ratio of an area of the first transistor portion to a combined area of the first and second portions is 5 percent to 75 percent. A shunt is coupled in series to the first clip. The shunt may be directly electrically connected to the first portion of the power transistor. | 10-24-2013 |
20140063744 | Vertically Stacked Power FETS and Synchronous Buck Converter Having Low On-Resistance - A power FET ( | 03-06-2014 |
20140210064 | WIRE BONDING METHOD AND STRUCTURE - An integrated circuit (“IC”) assembly includes an IC die with a metallization layer on a top surface thereof. A plurality of lead wires are bonded at first end portions thereof to the metallization layer. A conductive layer is attached to the metallization layer and covers the first ends of the lead wires. | 07-31-2014 |
20140306332 | Integrating Multi-Output Power Converters Having Vertically Stacked Semiconductor Chips - A packaged multi-output converter ( | 10-16-2014 |
20150221584 | Stacked Synchronous Buck Converter Having Chip Embedded in Outside Recess of Leadframe - A power supply system ( | 08-06-2015 |
20150221622 | DC-DC CONVERTER HAVING TERMINALS OF SEMICONDUCTOR CHIPS DIRECTLY ATTACHABLE TO CIRCUIT BOARD - A power supply system ( | 08-06-2015 |
20150262965 | WIRE BONDING METHOD AND STRUCTURE - An integrated circuit (“IC”) assembly includes an IC die with a metallization layer on a top surface thereof. A plurality of lead wires are bonded at first end portions thereof to the metallization layer. A conductive layer is attached to the metallization layer and covers the first ends of the lead wires. | 09-17-2015 |
20150318233 | DC-DC CONVERTER HAVING TERMINALS OF SEMICONDUCTOR CHIPS DIRECTLY ATTACHABLE TO CIRCUIT BOARD - A power supply system has a QFN leadframe with leads and a pad. The pad surface facing a circuit board has a portion recessed with a depth and an outline suitable for attaching side-by-side the sync and the control FET semiconductor chips. The input terminal of the control FET and the grounded output terminal of the sync FET are coplanar with the un-recessed portion of the pad (switch node terminal) so that all terminals can be directly attached to contacts of a circuit board. A driver-and-control chip is vertically stacked to the opposite pad surface and encapsulated in a packaging compound. | 11-05-2015 |
20160027722 | Stacked Synchronous Buck Converter Having Chip Embedded in Outside Recess of Leadframe - A system has a leadframe with leads and a pad. The pad surface having a portion recessed with a depth and an outline suitable for attaching a semiconductor chip. A first chip is vertically stacked to the opposite pad surface. A clip is vertically stacked on the first chip and tied to a lead. A second chip has a terminal attached to the recessed portion and terminals co-planar with the un-recessed portion. A second chip is attached to the clip. | 01-28-2016 |
20160064313 | Integrating Multi-Output Power Converters Having Vertically Stacked Semiconductor Chips - A electronic multi-output device having a substrate including a pad and pins. A composite first chip has a first and a second transistor integrated so that the first terminals of the transistors are merged into a common terminal on one chip surface. Patterned second and third terminals are on the opposite chip surface. The common first terminal is attached to the substrate pad. The second terminals are connected by discrete first and second metal clips to respective substrate pins. A composite second chip has a third and a fourth transistor integrated so that the second terminals of the transistors are merged into a common terminal on one chip surface. Patterned first and third terminals are on the opposite chip surface. The second chip is flipped to be vertically attached with its first terminals to the first and second clips, respectively. The third terminals are connected by discrete clips to respective substrate pins. The common second terminal is connected by a common clip to a substrate pin. | 03-03-2016 |
20160064352 | Integrating Multi-Output Power Converters Having Vertically Stacked Semiconductor Chips - A method for fabricating an electronic multi-output device. A substrate having a pad and pins is provided. A first chip is provided having a first and a second transistor integrated so that the first terminals of the transistors are merged into a common terminal on one chip surface and the patterned second and third terminals are on the opposite chip surface. The common first terminal is attached to the substrate pad. A driver and control chip is attached to the substrate pad adjacent to the first chip. The second terminals of the first and second transistors are connected by discrete first and second gang clips to respective substrate pins. A second chip is provided having a third and a fourth transistor integrated so that the second terminals of the transistors are merged into a common terminal on one chip surface. Patterned first and third terminals are on the opposite chip surface. The second chip is flipped to attach the first terminals vertically to the first and second gang clips. The third terminals are concurrently attached by discrete gang clips to respective pins. A common clip is attached to the common second terminal and connecting the common clip to a pin. | 03-03-2016 |
20160064361 | Integrating Multi-Output Power Converters Having Vertically Stacked Semiconductor Chips - An electronic multi-output device has a substrate including a first pad, a second pad and a plurality of pins. A first chip with a first transistor has a first terminal on one chip surface and a second and third terminals on the opposite chip surface. The first chip with its first terminal is tied to the first pad. A second chip with a second transistor has a first terminal on one chip surface and a second and third terminals on the opposite chip surface. The second chip with its first terminal is tied to the second pad. The second terminals are connected by a discrete first metal clip and a second metal clip to respective substrate pins. A composite third chip has a third and a fourth transistor integrated so that the first terminals of the transistors are on one chip surface. The second terminals are merged into a common terminal. The patterned third terminals are on the opposite chip surface. The first terminals are vertically attached to the first and second metal clips, respectively. The common terminal is connected by a common clip to a substrate pin. | 03-03-2016 |