Patent application number | Description | Published |
20080317140 | Method of Converting a User Bitstream Into Coded Bitstream, Method for Detecting a Synchronization Pattern in a Signal, a Record Carier, a Signal, a Recording Device and a Playback Device - This ID proposes synchronization patterns for RLL codes with a (repeated) minimum transition run (RMTR) constraint, where the synchronization pattern comprises a synchronization pattern-body that contains a characteristic bit-pattern that represents a violation of the RMTR constraint. Using a violation of the RMTR constraint allows for short synchronization patterns. | 12-25-2008 |
20090015446 | Coder and a Method of Coding For Codes With a Parity-Complementary Word Assignment Having a Constraint of D1=,R=2 - Presently known d=1 codes have long trains consisting of consecutive 2T runs and an overall high frequency of occurrence of the shortest 2T runs that reduce the performance of the bit detector By using a code with an MTR constraint of 2 an improvement in the bit detection is achieved. A code constructed in a systematic way that provides an MTR constraint of 2 is presented. A variation of such a code is disclosed where one sub-code is used, where coding states are divided into coding classes and where code words are divided into code word types. Then, for a given sub-code, an code word of type t can be concatenated with an code word of the next sub-code if said subsequent code word of said next sub-code belongs to one of coding states of the coding class with index T | 01-15-2009 |
20090019332 | SISO DECODER WITH SUB-BLOCK PROCESSING AND SUB-BLOCK BASED STOPPING CRITERION - The present invention relates to SISO decoder for iteratively decoding a block of received information symbols (r), in particular for use in a turbo decoder, said block being divided into a number of windows of information symbols. In order to achieve a significant reduction of power consumption a SISO decoder is proposed comprising:
| 01-15-2009 |
20090296556 | READING DEVICE FOR A RECORD CARRIER - The invention provides an efficient reading device in which, even if one radiation beam should fail, no information is lost and the information can still be read out without time-consuming recurring operations. The present invention solves this problem by providing a reading device (FIG. | 12-03-2009 |
20100188004 | DRIVING A LIGHT SOURCE - A method for driving a light source ( | 07-29-2010 |
20110122005 | METHOD TO LINEARIZE THE OUTPUT FROM AN ADC - A method is disclosed of compensating the output of an ADC for non-linearity in the response of the ADC. The method comprises converting an analog input signal to uncorrected digital ADC output samples, applying a vector of correction variables to each of a block of uncorrected ADC output samples to provide a block of corrected ADC samples, and iteratively minimizing a measure of the spectral flatness of the block of corrected ADC samples with response to the vector of correction variables. | 05-26-2011 |
20120008722 | SIGNAL PROCESSOR, RECEIVER AND SIGNAL PROCESSING METHOD - A processor ( | 01-12-2012 |
20120042228 | BITWISE RELIABILITY INDICATORS FROM SURVIVOR BITS IN VITERBI DECODERS - Various embodiments relate to the production of erasure flags to indicate errors resulting from decoding of convolutional codes. A Viterbi decoder may use a register exchange method to produce a plurality of survivor codes. At a defined index, a majority vote may take place comparing values of bits in each of the survivor codes. This majority vote may involve obtaining both the quantity of high-order bits and the quantity of low-order bits and obtaining the difference of the two quantities. The absolute value of the difference of high-order bits to low-order bits may be compared to a defined threshold. When the absolute value difference is below the defined quantity, an erasure flag may be produced and associated with the bits of the defined index, indicating that they are eligible for erasure. In some embodiments, a Reed-Solomon decoder may use the erasure flag to target specific survivor bits or survivor bytes for error-correction through erasure. | 02-16-2012 |
20120042229 | MULTI-STANDARD VITERBI PROCESSOR - Various embodiments relate to a multi-standard Viterbi decoder. Based on programmable values for constraint length, generator polynomials, and code rate, the multi-standard Viterbi decoder may adhere to a specific convolutional code standard. At a given time, the multi-standard Viterbi decoder may receive a variety of convolutional codes through a channel and may process them using various forms of the trace back method. Various embodiments include a branch metric unit and path metric unit that include a variety of sub-units that may or may not be active based on the value of the programmable value. Various embodiments also enable the multi-standard Viterbi decoder to handle different forms of convolutional codes, such as tail-biting codes. In some embodiments, the multi-standard Viterbi decoder may also process at least two convolutional codes concurrently. | 02-16-2012 |