Patent application number | Description | Published |
20080282100 | INTEGRATED CIRCUIT WITH POWER CONTROL AND POWER CONTROL METHOD THEREOF - Power management methods for integrated circuits are disclosed. A system core block is disposed in a chip and comprises a central processing unit. A power control block is disposed in the chip and comprises a power management mechanism coupled to a power supply to control the supply of power to the system core block. The power management mechanism outputs a power down signal and stops supply of power to the system core block according to a power saving mode setting signal from the central processor unit and starts the supply of power to the system core block according to a power saving mode release signal. | 11-13-2008 |
20090119526 | ELECTRONIC SYSTEM AND POWER CONTROL METHOD THEREOF - Electronic systems capable of entering a power saving mode even if a processing unit therein crashes are provided, in which a system core block comprises a processing unit. A power control block, operating in a different power domain than the system core block comprises a power control logic circuit, which sends an enabling signal to a power supply to power down the system core block according to a triggering signal. | 05-07-2009 |
20110069758 | VIDEO PROCESSING APPARATUS AND METHOD - A video processing apparatus includes a decoder, a controller and a display device. The decoder decodes a bitstream, wherein the bitstream includes a plurality of groups of pictures and each group of pictures includes a frame sequence. The controller is coupled to the decoder to determine whether a current frame of a current group of pictures to be displayed has macroblocks with forward reference to a previous frame of a previous group of pictures, wherein the current group of pictures is subsequent to the previous group of pictures. The display device is coupled to the controller to display the current frame of the current group of pictures when the current frame has no macroblock with forward reference to the previous frame of the previous group of pictures. | 03-24-2011 |
20150016466 | NETWORK DEVICE AND METHOD FOR OUTPUTTING DATA TO BUS WITH DATA BUS WIDTH AT EACH CYCLE BY GENERATING END OF PACKET AND START OF PACKET AT DIFFERENT CYCLES - A method used in a network device for outputting data to a bus with a data bus width at each cycle includes: using a packet generator for generating idle data after an end of packet for a packet at a cycle and generating a start of packet for a next packet at a different cycle; and using an inter-packet gap (IPG) generator for receiving data transmitted from the packet generator, dynamically writing the received data into the buffer, and inserting a gap of idle data between the end of packet and the start of packet according to the end of packet and the idle data generated by the packet generator. | 01-15-2015 |
Patent application number | Description | Published |
20080317121 | Rate control methods and devices - Rate control methods and devices for use in a video encoding device supporting at least one core are provided. First, a sequence of frames is received. A plurality of threads are created according to the number of the at least one core. The threads are employed to encode at least one frame of the received frames, simultaneously. The frames in the sequence are then encoded according to the encoding results corresponding to the at least one frame. | 12-25-2008 |
20130237219 | FREQUENCY ADJUSTMENT METHOD - A frequency adjustment method is provided for adjusting a frequency of a reference oscillating signal from an initial oscillation frequency to an adjusted oscillation frequency. The frequency adjustment method includes steps of: dividing a frequency scan section into M scan frequencies; down-converting a signal according to the M scan frequencies to obtain M down-converted signals; performing a correlation calculation operation on the M down-converted signals, respectively, to obtain M correlation results; grouping the M scan frequencies into N frequency groups each containing P selected frequencies, with the P selected frequencies corresponding to P consecutive scan frequencies; performing a group calculation on the N frequency groups, respectively, to obtain N group calculation results; and selecting a target frequency group from the N frequency groups according to the N group calculations results, and obtaining the adjusted oscillation frequency from the target frequency group. | 09-12-2013 |
20140092798 | METHODS PERFORMED BY MOBILE COMMUNICATION DEVICES - An embodiment of the invention provides a method performed by a mobile communication device in a discontinuous reception (DRX) mode. First, the device dumps contemporarily received data and performs multipath search while a beginning part of a relevant sub-frame in a control channel is being transmitted. Next, the device dumps contemporarily received data and decodes dumped data with an accelerated rake while a middle part of the relevant sub-frame is being transmitted. Then, the device decodes contemporarily received data with a normal rake while an ending part of the relevant sub-frame is being transmitted. | 04-03-2014 |
20150189613 | APPARATUSES AND METHODS FOR PHYSICAL BROADCAST CHANNEL (PBCH) ASSISTED SYNCHRONIZATION DURING A DISCONTINUOUS RECEPTION (DRX) OPERATION - A mobile communication device with a Radio Frequency (RF) unit and a processing unit is provided. The RF unit transmits and receives wireless signals to and from a service network. The processing unit configures the RF unit to communicate with the service network in a DRX operation, and uses a Physical Broadcast Channel (PBCH) for synchronizing with the service network during the DRX operation. | 07-02-2015 |
Patent application number | Description | Published |
20120235552 | LAMP - A lamp includes a housing, a heat sink, a cooling fan and a light-emitting module. The housing has an assembling opening and an electrical connection member on two ends thereof, wherein the housing further comprises an inner wall and a portion of the inner wall adjacent to the assembling opening is an air-guiding wall. The heat sink has a base plate disposed at the assembling opening of the housing, wherein the base plate has at least one partitioning board defining an air channel of the heat sink. A first air-guiding opening is formed between the air-guiding wall and the at least one partitioning board, and a second air-guiding opening is formed between the air channel and the air-guiding wall. The cooling fan is coupled with the heat sink and has an impeller. The light-emitting module is coupled with the base plate of the heat sink. | 09-20-2012 |
20120236576 | LAMP - A lamp includes a housing, a heat sink, a cooling fan and a light-emitting module. The housing has an assembling opening and an electrical connection member on two ends thereof, wherein the housing further comprises an inner wall and a portion of the inner wall adjacent to the assembling opening is an air-guiding wall. The heat sink has a base plate disposed at the assembling opening of the housing, wherein the base plate has at least one partitioning board defining an air channel of the heat sink. A first air-guiding opening is formed between the air-guiding wall and the at least one partitioning board, and a second air-guiding opening is formed between the air channel and the air-guiding wall. The cooling fan is coupled with the heat sink and has an impeller. The light-emitting module is coupled with the base plate of the heat sink. | 09-20-2012 |
20130044491 | Lamp with Wide-Angle Light Emission and Bulb Thereof - A lamp with wide-angle light emission including a housing, a light emitting module and a bulb is disclosed. The housing has a coupling portion and an electrical connector formed at two ends thereof. The light emitting module is arranged at the coupling portion of the housing. The bulb covers the light emitting module and comprises a center part and a border part, with the center part axially aligning with the light emitting module and the border part surrounding the center part. Furthermore, a diffusing reflector is arranged on the center part and the border part is formed by a light transmitting portion. | 02-21-2013 |
Patent application number | Description | Published |
20120299020 | LED PACKAGE MODULE FOR LIGHTING - An LED package module for lighting includes a plurality of LED chips spacedly arranged on a hard substrate and a plurality of dome-shaped encapsulants arranged on the hard substrate in such a way that the encapsulants enclose the LED chips respectively. By means of the dome-shaped encapsulants, the light extracting rate of the LED chips is enhanced. On the surface of the hard substrate, no dam structure is needed; therefore, the amount of the encapsulant material used in the LED package module can be effectively saved. | 11-29-2012 |
20150069435 | LED PACKAGE AND MANUFACTURING PROCESS OF SAME - A LED package is formed of a substrate, an LED chip, an insulated layer, and a fluorescent adhesive layer. The substrate includes a positive contact and a negative contact. The LED chip is fixed to the substrate and includes a positive terminal and a negative terminal, the former of which is electrically connected with the positive contact and latter is electrically connected with the negative contact. The insulated layer is mounted to the surface of the substrate and surrounds the LED chip. The fluorescent adhesive layer is mounted to a surface of the insulated layer and covers the LED chip. In this way, the LED package can reduce the production cost and the whole size. | 03-12-2015 |
20150069626 | CHIP PACKAGE, CHIP PACKAGE MODULE BASED ON THE CHIP PACKAGE, AND METHOD OF MANUFACTURING THE CHIP PACKAGE - A chip package is formed of a complex substrate and a chip. The complex substrate includes a core plate, a thermally-conductive insulated layer, and a through hole running through the core plate and the thermally-conductive insulated layer. The core plate is fixed to the core plate and buried into the thermally-conductive insulated layer. An upper electrode of the chip is connected with a first circuit layer. The first circuit layer is disposed on a top side of the thermally-conductive insulated layer, into the through hole, and on a lower surface of the core plate. A lower electrode of the chip is connected with a second circuit layer. The second circuit layer is disposed on the lower surface of the core plate. In light of the structure, the chip package has a simplified manufacturing process and reduces the production cost and the package size. | 03-12-2015 |
20150099315 | MECHANISMS FOR MONITORING IMPURITY IN HIGH-K DIELECTRIC FILM - Embodiments of mechanisms of monitoring metal impurity in a high-k dielectric film are provided. The method includes forming an interfacial layer over a substrate. The method also includes forming a high-k dielectric film on the interfacial layer, and the interfacial layer and the high-k dielectric film form a stacked structure over the substrate. The method further includes conducting the first thickness measurement on the stacked structure. In addition, the method includes performing a treatment to the stacked structure after the first thickness measurement, and the treatment includes an annealing process. The method also includes conducting the second thickness measurement on the stacked structure after the treatment. | 04-09-2015 |
20150129414 | PROCESS KIT OF PHYSICAL VAPOR DEPOSITION CHAMBER AND FABRICATING METHOD THEREOF - A physical vapor deposition (PVD) chamber, a process kit of a PVD chamber and a method of fabricating a process kit of a PVD chamber are provided. In various embodiments, the PVD chamber includes a sputtering target, a power supply, a process kit, and a substrate support. The sputtering target has a sputtering surface that is in contact with a process region. The power supply is electrically connected to the sputtering target. The process kit has an inner surface at least partially enclosing the process region, and a liner layer disposed on the inner surface. The substrate support has a substrate receiving surface, wherein the liner layer disposed on the inner surface of the process kit has a surface roughness (Rz), and the surface roughness (Rz) is substantially in a range of 50-200 μm. | 05-14-2015 |
20150144982 | LED PACKAGE AND MANUFACTURING PROCESS OF SAME - A LED package is formed of a substrate, an LED chip, an insulated layer, and a fluorescent adhesive layer. The substrate includes a positive contact and a negative contact. The LED chip is fixed to the substrate and includes a positive terminal and a negative terminal, the former of which is electrically connected with the positive contact and latter is electrically connected with the negative contact. The insulated layer is mounted to the surface of the substrate and surrounds the LED chip. The fluorescent adhesive layer is mounted to a surface of the insulated layer and covers the LED chip. In this way, the LED package can reduce the production cost and the whole size. | 05-28-2015 |
20150371847 | METHOD FOR CONTROLLING SEMICONDUCTOR DEPOSITION OPERATION - The present disclosure provides a method for controlling a semiconductor deposition operation. The method includes (i) identifying a first target lifetime in a physical vapor deposition (PVD) system; (ii) inputting the first target lifetime into a processor; (iii) outputting, by the processor, a plurality of first operation parameters according to a plurality of compensation curves; and (iv) performing the first operation parameters in the PVD system. The first operation parameters includes, but not limited to, an RF power tuning, a DC voltage tuning, a target to chamber pedestal spacing tuning, an AC bias tuning, an impedance tuning, a reactive gas flow tuning, an inert gas flow tuning, a chamber pedestal temperature tuning, or a combination thereof. | 12-24-2015 |
Patent application number | Description | Published |
20080317069 | Speed negotiation for multi-speed communication devices - A method includes defining a pattern of time intervals, each time interval having a respective assigned communication speed, which alternates among multiple communication speeds supported by a first communication device. Synchronization requests are transmitted over a communication medium from the first communication device to a second communication device at the respective communication speed that is assigned in each interval in accordance with the pattern. While transmitting the synchronization requests, synchronization replies sent over the communication medium in response to the synchronization requests are received only at the respective communication speed that is assigned in each interval. Responsively to receiving the synchronization replies from the second communication device, one or more common communication speeds that are supported by both the first and the second communication devices are identified. Communication is established between the first and second communication devices over the communication medium using one of the common communication speeds. | 12-25-2008 |
20090289660 | INTERCONNECTION AND INPUT/OUTPUT RESOURCES FOR PROGRAMMABLE LOGIC INTEGRATED CIRCUIT DEVICES - A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device. | 11-26-2009 |
20140078902 | Scalable Low Latency Multi-Protocol Networking Device - A network device receives a packet that includes a plurality of sets of fields. Sets of fields of the packet are parsed and the field sets are evaluated as soon as they are available to determine whether a processing decision can be made on the packet. Additional field sets may be parsed from the packet and obtained in parallel with determining whether a processing decision can be made, but once it is determined that a processing decision can be made, the evaluating of field sets is terminated such that any further field sets of the packet are ignored for purposes of making a processing decision for the packet. | 03-20-2014 |
20140078915 | Exporting Real Time Network Traffic Latency and Buffer Occupancy - Techniques are presented herein to facilitate the monitoring of occupancy of a buffer in a network device. Packets are received at a network device. Information is captured describing occupancy of the buffer caused by packet flow through the buffer in the network device. Analytics packets are generated containing the information. The analytics packets from the network device for retrieval of the information contained therein for analysis, replay of buffer occupancy, etc. | 03-20-2014 |
20140079063 | Low Latency Networking Device Using Header Prediction - A network device receives a packet that includes a plurality of header fields. The packet is parsed to sequentially obtain the plurality of header fields. One or more header fields not yet available at the network device are predicted based on one or more header fields that are available at the network device. A network processing decision is generated for the packet based on the predicted one or more header fields and the one or more header fields that are available at the network device. | 03-20-2014 |
20140082118 | Ultra Low Latency Network Buffer Storage - Buffer designs and write/read configurations for a buffer in a network device are provided. According to one aspect, a first portion of the packet is written into a first cell of a plurality of cells of a buffer in the network device. Each of the cells has a size that is less than a minimum size of packets received by the network device. The first portion of the packet can be read from the first cell while concurrently writing a second portion of the packet to a second cell. | 03-20-2014 |
20150188850 | Ultra Low Latency Network Buffer Storage - Buffer designs and write/read configurations for a buffer in a network device are provided. According to one aspect, a first portion of the packet is written into a first cell of a plurality of cells of a buffer in the network device. Each of the cells has a size that is less than a minimum size of packets received by the network device. The first portion of the packet can be read from the first cell while concurrently writing a second portion of the packet to a second cell. | 07-02-2015 |
20150236933 | Timestamping Packets in a Network - Techniques are presented herein to facilitate latency measurements in a networking environment. A first network device receives a packet for transport within a network domain that comprises a plurality of network devices. The plurality of network devices have a common time reference, that is, they are time synchronized. The first network device generates timestamp information indicating time of arrival of the packet at the first network device. The first network device inserts into the packet a tag that comprises at least a first subfield and a second subfield. The first subfield comprising a type indicator to signify to other network devices in the network domain that the tag includes timestamp information, and the second subfield includes the timestamp information. The first network device sends the packet from to into the network domain to another network device. Other network devices which receive that packet can make latency measurements. | 08-20-2015 |
20150236982 | Scalable Low Latency Multi-Protocol Networking Device - A network device receives a packet that includes a plurality of sets of fields. Sets of fields of the packet are parsed and the field sets are evaluated as soon as they are available to determine whether a processing decision can be made on the packet. Additional field sets may be parsed from the packet and obtained in parallel with determining whether a processing decision can be made, but once it is determined that a processing decision can be made, the evaluating of field sets is terminated such that any further field sets of the packet are ignored for purposes of making a processing decision for the packet. | 08-20-2015 |
20150237177 | Low Latency Networking Device Using Header Prediction - A network device receives a packet that includes a plurality of header fields. The packet is parsed to sequentially obtain the plurality of header fields. One or more header fields not yet available at the network device are predicted based on one or more header fields that are available at the network device. A network processing decision is generated for the packet based on the predicted one or more header fields and the one or more header fields that are available at the network device. | 08-20-2015 |
20150244637 | Exporting Real Time Network Traffic Latency and Buffer Occupancy - Techniques are presented herein to facilitate the monitoring of occupancy of a buffer in a network device. Packets are received at a network device. Information is captured describing occupancy of the buffer caused by packet flow through the buffer in the network device. Analytics packets are generated containing the information. The analytics packets from the network device for retrieval of the information contained therein for analysis, replay of buffer occupancy, etc. | 08-27-2015 |
20150263922 | Measuring Latency within a Networking Device - Presented herein are techniques to measure latency associated with packets that are processed within a network device. A packet is received at a component of a network device comprising one or more components. A timestamp representing a time of arrival of the packet at a first point in the network device is associated with the packet. The timestamp is generated with respect to a clock of the network device. A latency value for the packet is computed based on at least one of the timestamp and current time of arrival at a second point in the network device. One or more latency statistics are updated based on the latency value. | 09-17-2015 |
Patent application number | Description | Published |
20120250334 | LED LAMP - An LED lamp includes a heat sink, a heat pipe and an LED. The heat sink includes a connecting core and fins mounted around the connecting core. Each of the fins includes a plate-shaped main body and a flange extending perpendicularly from a periphery side of the main body. The flanges of the fins cooperatively form an annular planar top surface of the heat sink. The heat pipe includes a condensing section, an evaporating section parallel to and higher than the condensing section and an adiabatic section connected between the condensing section and the evaporating section. The condensing section is fixed to and thermally connects with the top surface of the heat sink. The LED is directly mounted on the evaporating section with a light emitting surface thereof facing outwardly. | 10-04-2012 |
20130153178 | HEAT DISSIPATION DEVICE WITH FAN - A heat dissipation device includes a bracket, a fan with an air inlet and an air outlet, and a heat sink mounted on the bracket. The bracket includes a plurality of rivets and clasps. Each of the clasps includes a mounting portion, an arm extending upwards from the mounting portion, and a hook portion extending from a top end of the arm and towards the mounting portion. The mounting portion is riveted on the bracket by a corresponding rivet. The fan includes a plurality of ears corresponding to the clasps. The hook portions of the clasps abut on top surfaces of the ears to fix the fan on the bracket. The fan defines a plurality of channels communicating the outlet of the fan. | 06-20-2013 |
20130342994 | ELECTRONIC DEVICE HAVING FIXING MEMBER - An exemplary electronic device includes an electronic component, a heat dissipation device, a fixing member and a casing contained the electronic component, the heat dissipation device and the fixing member therein. The heat dissipation device thermally contacts the electronic component. The fixing member includes a main body and an engaging portion extending from the main body. The engaging portion fixes the heat dissipation device to the fixing member. Fasteners extend through the casing and engage the main body of the fixing member to secure the fixing member on the casing. | 12-26-2013 |
Patent application number | Description | Published |
20150137611 | POWER MANAGEMENT UNIT AND WIRELESS POWER SYSTEM USING THE SAME - A power management unit, adapted to a wireless power system, includes: a rectifier, converts an AC power received by an input port thereof to a direct-current (DC) voltage outputted by a rectifying output terminal thereof; a first switch, wherein a first protecting capacitor is coupled between one terminal of the input port and a channel thereof; a second switch, wherein a second protecting capacitor is coupled between the other terminal of the input port and a channel thereof; a reference voltage terminal, for providing a reference voltage; and, a comparator, including two input terminals coupled to the rectifying output terminal and the reference voltage terminal respectively, and including an output terminal coupled to both the control terminals of the first switch and the second switch. | 05-21-2015 |
20150142348 | POWER CALCULATING METHOD ADAPTED TO WIRELESS POWER SYSTEM - A power calculating method, adapted to a wireless power system, includes the following steps: first, multi-sampling input or output current of a regulator in the power receiving end, and performing root-men-square calculation accordingly to derive a current RMS value; second, multi-sampling input or output voltage of the regulator, and performing a root-men-square calculation accordingly to derive a voltage RMS value; third, multiplying the voltage RMS value to the current RMS value and a cosine of an angle to derive a regulating power value; fourth, dividing the regulating power value by a power efficiency value to derive a receiving power value; finally, transmitting the receiving power value to a power transmitting end of the wireless power system for performing foreign object detection. | 05-21-2015 |
Patent application number | Description | Published |
20130228830 | GATE STRUCTURE FOR SEMICONDUCTOR DEVICE - A semiconductor device and method of fabricating thereof is described that includes a substrate having a fin with a top surface and a first and second lateral sidewall. A hard mask layer may be formed on the top surface of the fin (e.g., providing a dual-gate device). A gate dielectric layer and work function metal layer are formed on the first and second lateral sidewalls of the fin. A silicide layer is formed on the work function metal layer on the first and the second lateral sidewalls of the fin. The silicide layer may be a fully-silicided layer and may provide a stress to the channel region of the device disposed in the fin. | 09-05-2013 |
20140284723 | FINFETS WITH DIFFERENT FIN HEIGHT AND EPI HEIGHT SETTING - An integrated circuit structure includes a first semiconductor strip, first isolation regions on opposite sides of the first semiconductor strip, and a first epitaxy strip overlapping the first semiconductor strip. A top portion of the first epitaxy strip is over a first top surface of the first isolation regions. The structure further includes a second semiconductor strip, wherein the first and the second semiconductor strips are formed of the same semiconductor material. Second isolation regions are on opposite sides of the second semiconductor strip. A second epitaxy strip overlaps the second semiconductor strip. A top portion of the second epitaxy strip is over a second top surface of the second isolation regions. The first epitaxy strip and the second epitaxy strip are formed of different semiconductor materials. A bottom surface of the first epitaxy strip is lower than a bottom surface of the second epitaxy strip. | 09-25-2014 |
20150048460 | GATE STRUCTURE FOR SEMICONDUCTOR DEVICE - A semiconductor device and method of fabricating thereof is described that includes a substrate having a fin with a top surface and a first and second lateral sidewall. A hard mask layer may be formed on the top surface of the fin (e.g., providing a dual-gate device). A gate dielectric layer and work function metal layer are formed on the first and second lateral sidewalls of the fin. A silicide layer is formed on the work function metal layer on the first and the second lateral sidewalls of the fin. The silicide layer may be a fully-silicided layer and may provide a stress to the channel region of the device disposed in the fin. | 02-19-2015 |
20150200297 | Strain Enhancement for FinFETs - An integrated circuit device includes a substrate having a first portion in a first device region and a second portion in a second device region. A first semiconductor strip is in the first device region. A dielectric liner has an edge contacting a sidewall of the first semiconductor strip, wherein the dielectric liner is configured to apply a compressive stress or a tensile stress to the first semiconductor strip. A Shallow Trench Isolation (STI) region is over the dielectric liner, wherein a sidewall and a bottom surface of the STI region is in contact with a sidewall and a top surface of the dielectric liner. | 07-16-2015 |
20150303116 | FinFETs with Different Fin Height and EPI Height Setting - An integrated circuit structure includes a first semiconductor strip, first isolation regions on opposite sides of the first semiconductor strip, and a first epitaxy strip overlapping the first semiconductor strip. A top portion of the first epitaxy strip is over a first top surface of the first isolation regions. The structure further includes a second semiconductor strip, wherein the first and the second semiconductor strips are formed of the same semiconductor material. Second isolation regions are on opposite sides of the second semiconductor strip. A second epitaxy strip overlaps the second semiconductor strip. A top portion of the second epitaxy strip is over a second top surface of the second isolation regions. The first epitaxy strip and the second epitaxy strip are formed of different semiconductor materials. A bottom surface of the first epitaxy strip is lower than a bottom surface of the second epitaxy strip. | 10-22-2015 |
20160099244 | Methods of Forming Semiconductor Devices and Structures Thereof - Methods of forming semiconductor devices and structures thereof are disclosed. In some embodiments, a semiconductor device includes a substrate that includes fins. Gates are disposed over the fins, the gates being substantially perpendicular to the fins. A source/drain region is disposed on each of fins between two of the gates. A contact is coupled to the source/drain region between the two of the gates. The source/drain region comprises a first width, and the contact comprises a second width. The second width is substantially the same as the first width. | 04-07-2016 |
20160141205 | FinFETs with Different Fin Height and EPI Height Setting - An integrated circuit structure includes a first semiconductor strip, first isolation regions on opposite sides of the first semiconductor strip, and a first epitaxy strip overlapping the first semiconductor strip. A top portion of the first epitaxy strip is over a first top surface of the first isolation regions. The structure further includes a second semiconductor strip, wherein the first and the second semiconductor strips are formed of the same semiconductor material. Second isolation regions are on opposite sides of the second semiconductor strip. A second epitaxy strip overlaps the second semiconductor strip. A top portion of the second epitaxy strip is over a second top surface of the second isolation regions. The first epitaxy strip and the second epitaxy strip are formed of different semiconductor materials. A bottom surface of the first epitaxy strip is lower than a bottom surface of the second epitaxy strip. | 05-19-2016 |
Patent application number | Description | Published |
20150060929 | CERAMIC CIRCUIT BOARD AND LED PACKAGE MODULE USING THE SAME - A ceramic circuit board includes a substrate made of Al | 03-05-2015 |
20150061814 | FERRITE CIRCUIT BOARD - A ferrite circuit board includes a substrate and a wire. The substrate is made of ferrite and provided with a surface and an elongated groove recessed from the surface. The elongated groove has an inner wall having a roughness Ra ranging from 0.1 μm to 20 μm. The wire is embedded in the elongated groove of the substrate, such that the wire is not easily separated from the substrate. The ferrite circuit board can be used as an inductor to provide abundant functionality. | 03-05-2015 |
20160034083 | TOUCH SENSING DEVICE - A touch sensing device includes a light-transmitting substrate, an edge layer and sensing lines. The light-transmitting substrate has an upper surface and a lower surface opposite to the upper surface, and the edge layer is covered on an edge of the upper surface of the light-transmitting substrate. The edge layer has a main body made of insulated material, and conductive wires. The main body has a first surface attached on the upper surface of the light-transmitting substrate, a second surface opposite and parallel to the first surface, and slots recessed downwardly from the second surface. The conductive wires are embedded in the slots, respectively. The sensing lines are disposed on the upper surface of the light-transmitting substrate and electrically connected with the conductive wires, respectively. Therefore, the touch sensing device can have simple and quick manufacturing process, high yield rate and low cost. | 02-04-2016 |
Patent application number | Description | Published |
20100064369 | METHODS, MEDIA, AND SYSTEMS FOR DETECTING ATTACK ON A DIGITAL PROCESSING DEVICE - Methods, media, and systems for detecting attack are provided. In some embodiments, the methods include: comparing at least part of a document to a static detection model; determining whether attacking code is included in the document based on the comparison of the document to the static detection model; executing at least part of the document; determining whether attacking code is included in the document based on the execution of the at least part of the document; and if attacking code is determined to be included in the document based on at least one of the comparison of the document to the static detection model and the execution of the at least part of the document, reporting the presence of an attack. In some embodiments, the methods include: selecting a data segment in at least one portion of an electronic document; determining whether the arbitrarily selected data segment can be altered without causing the electronic document to result in an error when processed by a corresponding program; in response to determining that the arbitrarily selected data segment can be altered, arbitrarily altering the data segment in the at least one portion of the electronic document to produce an altered electronic document; and determining whether the corresponding program produces an error state when the altered electronic document is processed by the corresponding program. | 03-11-2010 |
20140331324 | METHODS, MEDIA, AND SYSTEMS FOR DETECTING ATTACK ON A DIGITAL PROCESSING DEVICE - Methods, media, and systems for detecting attack are provided. In some embodiments, the methods include: comparing at least part of a document to a static detection model; determining whether attacking code is included in the document based on the comparison of the document to the static detection model; executing at least part of the document; determining whether attacking code is included in the document based on the execution of the at least part of the document; and if attacking code is determined to be included in the document based on at least one of the comparison of the document to the static detection model and the execution of the at least part of the document, reporting the presence of an attack. In some embodiments, the methods include: selecting a data segment in at least one portion of an electronic document; determining whether the arbitrarily selected data segment can be altered without causing the electronic document to result in an error when processed by a corresponding program; in response to determining that the arbitrarily selected data segment can be altered, arbitrarily altering the data segment in the at least one portion of the electronic document to produce an altered electronic document; and determining whether the corresponding program produces an error state when the altered electronic document is processed by the corresponding program. | 11-06-2014 |
Patent application number | Description | Published |
20130087460 | Method for Processing a Surface of a Metal Implant and the Metal Implant Produced by the Method - A method for treating a surface of a metal implant includes a polishing step, a grafting step. The polishing step includes polishing a surface of a metal implant to remove an uneven, natural oxide layer on the surface of the metal implant and to generate an even oxide layer on the surface of the metal implant. The grafting step includes grafting an anti-adhesion macromolecule on an outer face of the even oxide layer. A covalent bond between the anti-adhesion macromolecule and oxygen atoms on the outer face of the even oxide layer is formed, thus that a macromolecular anti-adhesion layer on the outer face of the even oxide layer can be created. The surface modifying step includes changing a property of the surface of the metal implant with the macromolecular anti-adhesion layer by high temperature and high pressure, providing the metal implant with high hydrophilicity. | 04-11-2013 |
20130137922 | Endoscope - An endoscope includes a tube having including a compartment extending in a longitudinal direction. A flexible strip has a diameter smaller than a diameter of the compartment. The flexible strip is received in the compartment and slideable relative to the tube in the longitudinal direction. The flexible strip is made of a super elastomer having an original shape before deformation. The flexible strip is capable of restoring the original shape after larger deformation. An image capturing module is mounted to the flexible strip. The image capturing module can transmit light beam and capture images. | 05-30-2013 |
20130150967 | Interbody Cage for Spine Fusion - An interbody cage including a substrate and a plurality of through holes is disclosed. The substrate has a plurality of curve slits, with each of the curve slits having a plurality of sections, wherein a plurality deformable ribs is formed, with each deformable rib between any two curve slits and having a narrow part and a wide part. The plurality of through holes is formed in the wide part of the deformable rib. In use, any adjacent two of the deformable ribs are capable of being bent to depart from each other to define a filling room. | 06-13-2013 |
20130173000 | Interbody Cage for Spine Fusion - An interbody cage includes a substrate having a plurality of curve slits, with each of the curve slits having a plurality of sections. A plurality of deformable ribs is formed, with each deformable rib between any adjacent two of the curve slits and having a first end and a second end. The first and second ends of each deformable rib respectively connect with two opposite lateral bars of the substrate, and a plurality of folds is formed on the plurality of deformable ribs in places adapted to be bent. In use, any adjacent two of the deformable ribs are capable of being bent to depart from each other to define a filling room. | 07-04-2013 |
20140180289 | Femur Supporting Device - A femur supporting device includes a rod having an insertion groove and a fixing through-hole. Each of the insertion groove and the fixing through-hole extends through an outer periphery of the rod. An insert is engaged in the insertion groove of the rod. A first fastener is engaged with the fixing through-hole of the rod. The femur supporting device provides enhanced stability. | 06-26-2014 |
20140187863 | Endoscope Controlling Device - An endoscope controlling device includes a rigid tube mounted to an end face of a base and in communication with a compartment in the base. A positioning groove is formed in an inner periphery of the base and includes a bottom wall having a slot. A linear displacement control module includes a control member and a movable board. The control member is aligned with a through-hole in a periphery of the base. The control member controls longitudinal movement of the movable board in the compartment along a longitudinal axis of the base via a driving gear. An optical element receiving drum is mounted to the movable board. A rotational movement control module is mounted around the optical element receiving drum and received in the positioning groove of the base. A portion of the rotational movement control module is extended through the slot and exposed outside of the base. | 07-03-2014 |
20150150689 | INTERVERTEBRAL IMPLANT - An intervertebral implant is a porous structure formed of a plurality of metal balls, and the intervertebral implant includes a bone support area and a bone growth area. The bone support area and the bone growth area each have a plurality of connecting holes, and a porosity of the bone support area is smaller than that of the bone growth area. | 06-04-2015 |
20150173905 | Intervertebral Implant - An intervertebral implant, particularly an intervertebral implant comprising local degradable hydroxyl apatite/metal block and based on a support mounting model of porous hydroxyl apatite with metal powders held for sintering and molding, guides osseous tissues to grow in porous metal and is steadily merged in upper and lower bones when the implanted hydroxyl apatite is gradually degraded in a certain period. | 06-25-2015 |