Patent application number | Description | Published |
20120025209 | OPTICAL CONNECTION THROUGH SINGLE ASSEMBLY OVERHANG FLIP CHIP OPTICS DIE WITH MICRO STRUCTURE ALIGNMENT - A system includes an optical transceiver assembly, including a flip chip connection of a semiconductor die with a photonic transceiver that overhangs a substrate to which it is to be connected. The assembly further includes an alignment pin that is held to the semiconductor die at a micro-engineered structure in the semiconductor die. The alignment pin provides passive alignment of the photonic transceiver with an optical lens that interfaces the photonic transceiver to one or more optical channels. | 02-02-2012 |
20130004167 | OPTICAL FRAME ATTACHED WITH ALIGNMENT FEATURES MICROFABRICTATED IN DIE - A photonic device assembly including a photonic device fabricated on a chip substrate, the chip substrate having a physical alignment feature fabricated therein, and a frame to couple an external optical lens or interconnect to the photonic device. The frame has a frame facet abutted to a complementary facet of the physical alignment feature. An adhesive permanently affixes the frame to the photonic device as aligned by the abutted facets. A method of forming a photonic device assembly includes microfabricating a physical alignment feature in a chip substrate of a photonic device and joining a frame to the chip substrate by abutting a facet of the coupling to a complementary facet of the fabricated physical alignment feature. | 01-03-2013 |
20130273672 | SEMICONDUCTOR SUBSTRATE FOR AN OPTICAL TRANSMITTER APPARATUS AND METHOD - Embodiments of the present disclosure describe semiconductor substrate techniques and configurations for an optical receiver. In one embodiment, a system includes a semiconductor substrate having one or more optical alignment features formed in a surface of the semiconductor substrate and an optical receiver assembly coupled with the semiconductor substrate, the optical receiver assembly including a photodetector device coupled with the surface of the semiconductor substrate, wherein the one or more optical alignment features facilitate precise optical alignment between a lens assembly and the photodetector device when the lens assembly is coupled with the semiconductor substrate using the one or more optical alignment features. Other embodiments may be described and/or claimed. | 10-17-2013 |
20140175477 | EDGE COUPLING ALIGNMENT USING EMBEDDED FEATURES - Methods and systems may provide an alignment scheme for components that may reduce positional deviation between the components. The method may include placing a first component on top of a substrate, wherein the first component includes a receiving alignment feature, and coupling a second component to the first component, wherein the coupling includes inserting a protruding alignment feature of the second component into the receiving alignment feature of the first component. In one example, the first component includes an edge-emitting semiconductor die and the second component include one or more of an optical lens and an alignment frame. | 06-26-2014 |
20140270655 | OPTICAL CONNECTOR ASSEMBLY - Methods, apparatuses, and systems related to optical connector assemblies are described. In some embodiments, the connector assemblies may include an optical assembly, having an optical interconnect and an optical module, to be coupled with a host electrical connector. The connector assembly may further include springs, disposed on the optical interconnect or the host electrical connector, to facilitate a coupling of the optical interconnect with the optical module. Other embodiments are described and claimed. | 09-18-2014 |
20150028432 | ASSEMBLY AND PACKAGING OF MEMS DEVICE - A Micro Electro Mechanical systems (MEMS) device includes a solder bump on a substrate, a CMOS-MEMS die comprising a CMOS die and a MEMS die, and stud bumps on the CMOS die. The MEMS die is disposed between the CMOS die and the substrate. The stud bumps and the solder bumps are positioned to provide an electrical connection between the CMOS die and the substrate. | 01-29-2015 |
20160062066 | OPTICAL CONNECTOR ASSEMBLY - Methods, apparatuses, and systems related to optical connector assemblies are described. In some embodiments, the connector assemblies may include an optical assembly, having an optical interconnect and an optical module, to be coupled with a host electrical connector. The connector assembly may further include springs, disposed on the optical interconnect or the host electrical connector, to facilitate a coupling of the optical interconnect with the optical module. Other embodiments are described and claimed. | 03-03-2016 |
20160087172 | EDGE COUPLING ALIGNMENT USING EMBEDDED FEATURES - Methods and systems may provide an alignment scheme for components that may reduce positional deviation between the components. The method may include placing a first component on top of a substrate, wherein the first component includes a receiving alignment feature, and coupling a second component to the first component, wherein the coupling includes inserting a protruding alignment feature of the second component into the receiving alignment feature of the first component. In one example, the first component includes an edge-emitting semiconductor die and the second component include one or more of an optical lens and an alignment frame. | 03-24-2016 |
20160093791 | APPARATUS AND METHOD FOR SEALING A MEMS DEVICE - A method and apparatus for sealing a device with a MEMS device with an active region is disclosed. A substrate with an opening is disposed relative to the MEMS device so as to align the active region of the MEMS device with the opening. A sealant is disposed between the MEMS device and the substrate so as to form a seal around the active region. The device includes one or more flow limiting features to inhibit the flow of sealant to the active region. | 03-31-2016 |
Patent application number | Description | Published |
20080219133 | Probe storage with doped diamond-like carbon medium and current limiter - According to embodiments of the present invention, a probe storage medium includes a conductive layer as an electrode and a metal, metalloid, and/or non-metal doped diamond-like carbon (DLC) layer disposed on the conductive layer. A probe array may be positioned close proximity with the layer of doped DLC. An individual probe in the probe array may have an atomic force microscope tip. The probe storage medium may be written to by applying a current, voltage, and/or power to the tip between a thresholds current, voltage, and/or power value and a limiting current, voltage, and/or power value. The current, voltage, and/or power cause the layer of DLC to change conductance. The probe storage medium may be read by applying a current, voltage, and/or power to the tip below a threshold current, voltage, and/or power value and sensing the conductance. | 09-11-2008 |
20090168637 | Arrangement and Method to Perform Scanning Readout of Ferroelectric Bit Charges - An arrangement, a method and a system to read information stored in a layer of ferroelectric media. The arrangement includes a layer including a ferroelectric media having one or more ferroelectric domains holding bit charges, a domain corresponding to information; a probe having a tip, wherein the media and the tip are adapted to move relative to one another such that the tip scans the ferroelectric domains of the media while applying a contact force to the domains to generate a direct piezoelectric effect within the domains; and circuitry coupled to the tip and adapted to generate a signal in response to an electrical coupling between the tip and the domains while scanning the tip in contact with the domains, the signal corresponding to a readout signal for ferroelectric bit charges stored in the media | 07-02-2009 |
20100002563 | MEDIA WITH TETRAGONALLY-STRAINED RECORDING LAYER HAVING IMPROVED SURFACE ROUGHNESS - A media for storing information comprises a substrate, a conductive layer formed over the substrate, and a ferroelectric layer epitaxially formed on the conductive layer. The ferroelectric layer includes an a-lattice constant that is substantially matched to an a-lattice constant of the conductive layer and an average c-lattice constant that is longer than an average c-lattice constant of a bulk-grown ferroelectric layer. | 01-07-2010 |
20100100991 | Charge-Amp Based Piezoelectric Charge Microscopy (CPCM) Reading of Ferroelectric Bit Charge Signal - A device to detect polarization of a ferroelectric material comprises a probe tip, a charge amplifier electrically connected with the probe tip to convert a charge coupled to the probe tip from the ferroelectric material into an output voltage. The ferroelectric material is oscillated at a reference signal so that a charge is coupled to the probe tip and converted to an output voltage by the charge amplifier. A lock-in amplifier that receives the reference voltage and applies the reference voltage to the output voltage to extract a signal output representing the polarization. | 04-22-2010 |
20130003521 | ARRANGEMENT AND METHOD TO PERFORM SCANNING READOUT OF FERROELECTRIC BIT CHARGES - An arrangement, a method and a system to read information stored in a layer of ferroelectric media. The arrangement includes a layer including a ferroelectric media having one or more ferroelectric domains holding bit charges, a domain corresponding to information; a probe having a tip, wherein the media and the tip are adapted to move relative to one another such that the tip scans the ferroelectric domains of the media while applying a contact force to the domains to generate a direct piezoelectric effect within the domains; and circuitry coupled to the tip and adapted to generate a signal in response to an electrical coupling between the tip and the domains while scanning the tip in contact with the domains, the signal corresponding to a readout signal for ferroelectric bit charges stored in the media | 01-03-2013 |
Patent application number | Description | Published |
20080316897 | METHODS OF TREATING A SURFACE OF A FERROELECTRIC MEDIA - A method of forming a passivation layer over a ferroelectric layer of a ferroelectric media comprises introducing the ferroelectric layer to a plasma comprising one of oxygen, oxygen-helium, and oxygen-nitrogen-helium, etching a surface of the ferroelectric layer, forming one of a substantially oxygen enriched layer and a substantially hydroxyl enriched layer at the surface of the ferroelectric layer, introducing the ferroelectric layer to an environment comprising substantially nitrogen, and maintaining the ferroelectric layer within the environment so that nitrogen enriches the substantially oxygen enriched layer to form a passivation layer. | 12-25-2008 |
20080318086 | SURFACE-TREATED FERROELECTRIC MEDIA FOR USE IN SYSTEMS FOR STORING INFORMATION - A system for storing information comprises a media including a ferroelectric layer and a passivation layer formed over the ferroelectric layer, and a tip arranged in approximate contact with the passivation layer. The tip detects a polarization signal that corresponds to changes in polarization of domains of the ferroelectric layer. | 12-25-2008 |
20090021975 | METHOD AND MEDIA FOR IMPROVING FERROELECTRIC DOMAIN STABILITY IN AN INFORMATION STORAGE DEVICE - A media for an information storage device comprises a substrate of single-crystal silicon, a buffer layer of an epitaxial single crystal insulator formed over the substrate, a bottom electrode layer of an epitaxial single crystal conductor formed over the buffer layer, a ferroelectric layer of an epitaxial single crystal ferroelectric material formed over the bottom electrode layer, and an overlayer of an epitaxial single crystal material formed over the ferroelectric layer. Dipole charges generally having a first orientation exist at an interface between the bottom electrode layer and the ferroelectric layer includes, while dipole charges generally having a second orientation opposite the first orientation exist at an interface between the ferroelectric layer and the overlayer includes. | 01-22-2009 |
Patent application number | Description | Published |
20120033370 | PCIe BUS EXTENSION SYSTEM, METHOD AND INTERFACES THEREFOR - A PCIe bus extension system, method, interface card and cable for connecting a PCIe-compliant peripheral device to a PCIe bus of a computer system. The interface card includes a printed circuit board, an edge connector adapted for insertion into a PCIe expansion slot on a motherboard of the computer system for transmitting PCIe signals between the motherboard and the interface card, an interface port configured to mate with a connector of the cable, and a logic integrated circuit on the printed circuit board, the logic integrated circuit functionally connecting the edge connector with the expansion slot and amplifying and propagating clock and data PCIe signals therebetween that are compliant with a PCIe standard. The interface card and cable lacks the capability of transmitting power therethrough to a PCIe-compliant peripheral device connected to the interface card through the interface port. | 02-09-2012 |
20120170210 | MOUNTING STRUCTURE AND METHOD FOR DISSIPATING HEAT FROM A COMPUTER EXPANSION CARD - A mounting structure adapted for mounting an expansion card within a computer enclosure and configured to directly absorb and conduct heat from a heat source (such as an IC chip) on the card to the ambient atmosphere surrounding the enclosure. The mounting structure includes a mounting bracket, a heat sink adapted to contact a surface of the heat source on the expansion card, an extension interconnecting the heat sink and the mounting bracket, one or more features for conducting heat from the heat sink to the mounting bracket, and one or more features associated with the mounting bracket for dissipating heat from the mounting structure to the ambient atmosphere surrounding the enclosure. | 07-05-2012 |
20140156897 | METHOD OF CONNECTING A PCIe BUS EXTENSION SYSTEM - A PCIe bus extension system, method, interface card and cable for connecting a PCIe-compliant peripheral device to a PCIe bus of a computer system. The interface card includes a printed circuit board, an edge connector adapted for insertion into a PCIe expansion slot on a motherboard of the computer system for transmitting PCIe signals between the motherboard and the interface card, an interface port configured to mate with a connector of the cable, and a logic integrated circuit on the printed circuit board, the logic integrated circuit functionally connecting the edge connector with the expansion slot and amplifying and propagating clock and data PCIe signals therebetween that are compliant with a PCIe standard. The interface card and cable lacks the capability of transmitting power therethrough to a PCIe-compliant peripheral device connected to the interface card through the interface port. | 06-05-2014 |
20140362524 | MOUNTING STRUCTURE AND METHOD FOR DISSIPATING HEAT FROM A COMPUTER EXPANSION CARD - A mounting structure adapted for mounting an expansion card within a computer enclosure and configured to directly absorb and conduct heat from a heat source (such as an IC chip) on the card to the ambient atmosphere surrounding the enclosure. The mounting structure includes a mounting bracket, a heat sink adapted to contact a surface of the heat source on the expansion card, an extension interconnecting the heat sink and the mounting bracket, one or more features for conducting heat from the heat sink to the mounting bracket, and one or more features associated with the mounting bracket for dissipating heat from the mounting structure to the ambient atmosphere surrounding the enclosure. | 12-11-2014 |
20150355691 | MOUNTING STRUCTURE AND METHOD FOR DISSIPATING HEAT FROM A COMPUTER EXPANSION CARD - A mounting structure adapted for mounting an expansion card within a computer enclosure and configured to directly absorb and conduct heat from a heat source (such as an IC chip) on the card to the ambient atmosphere surrounding the enclosure. The mounting structure includes a mounting bracket, a heat sink adapted to contact a surface of the heat source on the expansion card, an extension interconnecting the heat sink and the mounting bracket, one or more features for conducting heat from the heat sink to the mounting bracket, and one or more features associated with the mounting bracket for dissipating heat from the mounting structure to the ambient atmosphere surrounding the enclosure. | 12-10-2015 |
Patent application number | Description | Published |
20090238181 | NETWORK PACKET STEERING VIA CONFIGURABLE ASSOCIATION OF PROCESSING RESOURCES AND NETWORK INTERFACES - Methods and systems are provided for steering network packets. According to one embodiment a method is provided for steering incoming network packets. Each network packet processing resource of a network routing/switching device is dynamically assigned to one or more network interfaces of the network routing/switching device. Each of the network packet processing resources includes one or more processing elements and a memory. Incoming network packets received by the network interfaces are steered to an appropriate network packet processing resource based on the dynamic assignment. | 09-24-2009 |
20120069850 | NETWORK PACKET STEERING VIA CONFIGURABLE ASSOCIATION OF PACKET PROCESSING RESOURCES AND NETWORK INTERFACES - Methods and systems are provided for steering network packets. According to one embodiment, a dynamically configurable steering table is stored within a memory of each network interface of a networking routing/switching device. The steering table represents a mapping that logically assigns each of the network interfaces to one of multiple packet processing resources of the network routing/switching device. The steering table has contained therein information indicative of a unique identifier/address of the assigned packet processing resource. Responsive to receiving a packet on a network interface, the network interface performs Layer 1 or Layer 2 steering of the received packet to the assigned packet processing resource by retrieving the information indicative of the unique identifier/address of the assigned packet processing resource from the steering table based on a channel identifier associated with the received packet and the received packet is processed by the assigned packet processing resource. | 03-22-2012 |
20130166859 | IDENTIFYING UNALLOCATED MEMORY SEGMENTS - A network device that includes a first memory to store packets in segments; a second memory to store pointers associated with the first memory; a third memory to store summary bits and allocation bits, where the allocation bits correspond to the segments. The network device also includes a processor to receive a request for memory resources; determine whether a pointer is stored in the second memory, where the pointer corresponds to a segment that is available to store a packet; and send the pointer when the pointer is stored in the second memory. The processor is further to perform a search to identify other pointers when the pointer is not stored in the second memory, where performing the search includes identifying a set of allocation bits, based on an unallocated summary bit, that corresponds to the other pointers; identify another pointer, of the other pointers, based on an unallocated allocation bit of the set of allocation bits; and send the other pointer in response to the request. | 06-27-2013 |
20140161136 | Network Packet Steering via Configurable Association of Packet Processing Resources and Network Interfaces - Methods and systems are provided for steering network packets. According to one embodiment, a dynamically configurable steering table is stored within a memory of each network interface of a networking routing/switching device. The steering table represents a mapping that logically assigns each of the network interfaces to one of multiple packet processing resources of the network routing/switching device. The steering table has contained therein information indicative of a unique identifier/address of the assigned packet processing resource. Responsive to receiving a packet on a network interface, the network interface performs Layer 1 or Layer 2 steering of the received packet to the assigned packet processing resource by retrieving the information indicative of the unique identifier/address of the assigned packet processing resource from the steering table based on a channel identifier associated with the received packet and the received packet is processed by the assigned packet processing resource. | 06-12-2014 |
Patent application number | Description | Published |
20150221277 | Voltage Reference and Current Source Mixing Method for Video DAC - A method of arranging components in an integrated circuit includes providing two or more circuit cells of a first type and providing two or more circuit cells of a second type. The circuit cells of the first type are configured to operate in conjunction with the circuit cells of the second type. The method further includes arranging the circuit cells of the first and second types in an alternating pattern such that each circuit cell of the first type is adjacent to at least one circuit cell of the second type. The alternating pattern may be an array of rows and columns and may include a repeating pattern of one first type cell and one second type cell in each of the columns. The alternating pattern may include a repeating pattern of one cell of the first type and two cells of the second type in each of the columns. | 08-06-2015 |
20150356915 | Active Matrix LED Pixel Driving Circuit And Layout Method - Embodiments provide an active matrix LED pixel driving circuit and pixel layout for increased uniform illumination of LED display panels. A plurality of sub driving transistors can be located in neighbor pixels of the pixel associated with the prime driver transistor's LED. The sub driving transistors can compensate for the process variations affecting the threshold voltage variation of the prime driver transistor resulting in uniform illumination of LED's on the display panel. | 12-10-2015 |
20160086534 | ACTIVE MATRIX LED PIXEL DRIVING CIRCUIT AND LAYOUT METHOD - A unit pixel driver circuit includes a capacitor configured to store a voltage corresponding to a desired pixel brightness and a control block. The control block may include a first, second third and fourth transistors, all of which are connected together, both in parallel and in series. The control block controls, based on the voltage stored in the capacitor, the amount of current flowing through a pixel LED. The first transistor, second transistor, third transistor and fourth transistor all share a common gate geometry size. | 03-24-2016 |
Patent application number | Description | Published |
20120244576 | COMPOSITIONS AND METHODS FOR IMPROVED PROTEIN PRODUCTION - The present invention relates to the identification of novel nucleic acid sequences, designated herein as 7p, 8k, 7E, 9G, 8Q and 203, in a host cell which effect protein production. The present invention also provides host cells having a mutation or deletion of part or all of the gene encoding 7p, 8k, 7E, 9G, 8Q and 203, which are presented in FIG. | 09-27-2012 |
20140004564 | COMPOSITIONS AND METHODS FOR IMPROVED PROTEIN PRODUCTION | 01-02-2014 |
20150072380 | COMPOSITIONS AND METHODS FOR IMPROVED PROTEIN PRODUCTION - The present invention relates to the identification of novel nucleic acid sequences, designated herein as 7p, 8k, 7E, 9G, 8Q and 203, in a host cell which effect protein production. The present invention also provides host cells having a mutation or deletion of part or all of the gene encoding 7p, 8k, 7E, 9G, 8Q and 203, which are presented in FIG. | 03-12-2015 |