Patent application number | Description | Published |
20080251949 | Molding apparatus, molded semiconductor package using multi-layered film, fabricating and molding method for fabricating the same - Example embodiments include molding apparatuses, semiconductor packages, a fabricating methods for fabricating the same. The molding apparatus may include a first mold die for adhering a partially completed package, a second mold die including a cavity formed such that the partially completed package is positioned inside the cavity and a molding resin for encapsulating the partially completed package inserted into the cavity, and a multi-layered film supply unit for supplying a multi-layered film to the cavity of the second mold die. The semiconductor package may include a substrate, a semiconductor chip electrically connected to the substrate, a molding resin for encapsulating the semiconductor chip and an electrical portion of the substrate, and a marking film, adhered to an outer surface of the molding resin such that a mark is marked in the marking film. | 10-16-2008 |
20080311727 | METHOD OF CUTTING A WAFER - In a method of cutting a wafer, a supporting member is attached to an upper surface of the wafer on which semiconductor chips are formed. An opening is formed at a lower surface of the wafer along a scribe lane of the wafer. The lower surface of the wafer may be plasma-etched to reduce a thickness of the wafer. A tensile tape may be attached to the lower surface of the wafer. Here, the tensile tape includes sequentially stacked tensile films having different tensile modules. The supporting member is then removed. The tensile tape is cooled to increase the tensile modules between the tensile films. The tensile tape is tensed until the tensile films are cut using the tensile modules difference to separate the tensile tape from the semiconductor chips. Thus, the lower surface of the wafer may be plasma-etched without using an etching mask. | 12-18-2008 |
20080315408 | Semiconductor package, semiconductor package module including the semiconductor package, and methods of fabricating the same - Provided are a semiconductor package and a semiconductor package module including the same. The semiconductor package may include a plurality of semiconductor chips, a plurality of leads connected to pads of the semiconductor chips and externally exposed, wherein the plurality of leads may be classified into a plurality of pin groups, and the plurality of semiconductor chips may be classified into a plurality of chip groups, and the pads of the semiconductor chips of like chip groups may be connected to the leads of like pin groups. | 12-25-2008 |
20090200362 | METHOD OF MANUFACTURING A SEMICONDUCTOR PACKAGE - In a lead-free solder, a semiconductor package and a method of manufacturing the semiconductor package, the lead-free solder includes about 3.5 percent by weight to about 6 percent by weight of silver, about 0.05 percent by weight to about 0.5 percent by weight of copper and a remainder of tin. The lead-free solder is employed in the semiconductor package. The lead-free solder has high impact resistance and high heat resistance to reduce failures of the semiconductor package. | 08-13-2009 |
20090278249 | Printed circuit board and method thereof and a solder ball land and method thereof - A printed circuit board and method thereof and a solder ball land and method thereof. The example printed circuit board (PCB) may include a first solder ball land having a first surface treatment portion configured for a first type of resistance and a second solder ball land having a second surface treatment portion configured for a second type of resistance. The example solder ball land may include a first surface treatment portion configured for a first type of resistance and a second surface treatment portion configured for a second type of resistance. A first example method may include first treating a first surface of a first solder ball land to increase a first type of resistance and second treating a second surface of a second solder ball land to increase a second type of resistance other than the first type of resistance. A second example method may include first treating a solder ball land to increase a first type of resistance and second treating the solder ball land to increase a second type of resistance other than the first type of resistance. | 11-12-2009 |
20110024919 | WIRING SUBSTRATE FOR A SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE HAVING THE WIRING SUBSTRATE - A wiring substrate for a semiconductor chip includes a substrate having a first face and a second face opposite to the first face. The substrate has a window from the first face to the second face that exposes chip pads of a semiconductor chip adherable to the first face. A first bonding pad is arranged on the second face along a side portion of the window. The first bonding pad is connected to a bonding wire drawn from the chip pad through the window at a predetermined angle with respect to the side portion. A second bonding pad is adjacent to the first bonding pad on the second face. The second bonding pad includes an end portion having an inclined side portion at an angle corresponding to the drawn angle of the first bonding wire for avoiding an overlap of the second bonding pad with the first bonding wire. | 02-03-2011 |
20110124273 | WAFER POLISHING APPARATUS FOR ADJUSTING HEIGHT OF WHEEL TIP - In a wafer polishing apparatus, the height of the wheel tip can be adjusted. The wafer polishing apparatus includes a wheel tip constructed and arranged to be in direct contact with a wafer; a spindle shaft configured to receive power to enable rotation of the wheel tip; a wheel shank positioned at a lower part of the spindle shaft and supporting the wheel tip, the wheel tip not being directly fixed thereto; and a moving shaft having a first side on which the wheel tip is mounted and an opposite side to which the spindle shaft is connected, and relatively movable with respect to the spindle shaft. | 05-26-2011 |
20120013007 | PACKAGE-ON-PACKAGE SEMICONDUCTOR PACKAGE HAVING SPACERS DISPOSED BETWEEN TWO PACKAGE SUBSTRATES - A Package-on-Package (POP) semiconductor package has a structure in which a second semiconductor package is stacked on a first semiconductor package. A plurality of spacers are disposed between a first substrate of the first semiconductor package and a second substrate of the second semiconductor package so as to maintain a gap between the first substrate and the second substrate. The plurality of spacers may project from a bottom surface of the second substrate toward the first substrate, or may project from a top surface of the first substrate toward the second substrate. When an upper molding layer is formed on the second substrate so as to cover a second semiconductor chip, the plurality of spacers may be connected to the upper molding layer via through holes that vertically pass through the second substrate. When a first semiconductor chip is adhered to the top surface of the first substrate with an adhering layer, the plurality of spacers may be connected to the adhering layer on the top surface of the first substrate. | 01-19-2012 |