Patent application number | Description | Published |
20100206818 | ULTRASONIC FILTRATION FOR CMP SLURRY - The present invention relates to semiconductor processing. In particular, it relates to a tunable ultrasonic filter and a method of using the same for more effective separation of large particles from slurry. In one embodiment a standing wave is produced in the filter and large particles are accumulated at the nodes of the standing waves while the slurry is flowed out of the filter. | 08-19-2010 |
20140264911 | THROUGH SILICON VIAS - A device and methods for forming a device are disclosed. A substrate is provided and a TSV is formed in the substrate through a top surface of the substrate. The TSV and top surface of the substrate is lined with an insulation stack having a first insulation layer, a polish stop layer and a second insulation layer. A conductive layer is formed on the substrate. The TSV is filled with conductive material of the conductive layer. The substrate is planarized to remove excess conductive material of the conductive layer. The planarizing stops on the polish stop layer to form a planar top surface. | 09-18-2014 |
20150111467 | CMP HEAD STRUCTURE - A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table; a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes the retaining ring; a sensor for sensing the step height between the retaining ring and its membrane and a controller for adjusting the movement of the retaining ring based on the step height between the retaining ring and its membrane to ensure the step height remains at a fixed value as the retaining ring wears out. | 04-23-2015 |
20150111469 | CMP HEAD STRUCTURE - A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table, a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes a retaining ring, a sensor for sensing the depth of grooves on the retaining ring and a controller for determining an update pressure to apply to the retaining ring based on the depth of the grooves and applying the updated pressure to the retaining ring during processing. | 04-23-2015 |
Patent application number | Description | Published |
20120126388 | STACKABLE SEMICONDUCTOR ASSEMBLY WITH BUMP/FLANGE HEAT SPREADER AND DUAL BUILD-UP CIRCUITRY - A stackable semiconductor assembly includes a semiconductor device, a heat spreader, an adhesive, a plated through-hole, first build-up circuitry and second build-up circuitry. The heat spreader includes a bump and a flange. The bump defines a cavity. The semiconductor device is mounted on the bump at the cavity, electrically connected to the first build-up circuitry and thermally connected to the bump. The bump extends into an opening in the adhesive and the flange extends laterally from the bump at the cavity entrance. The first build-up circuitry and the second build-up circuitry extend beyond the semiconductor device in opposite vertical directions. The plated through-hole extends through the adhesive and provides signal routing between the first build-up circuitry and the second build-up circuitry. The heat spreader provides heat dissipation for the semiconductor device. | 05-24-2012 |
20120126399 | THERMALLY ENHANCED SEMICONDUCTOR ASSEMBLY WITH BUMP/BASE/FLANGE HEAT SPREADER AND BUILD-UP CIRCUITRY - A semiconductor assembly includes a semiconductor device, a heat spreader, an adhesive and a build-up circuitry. The heat spreader includes a bump, a base and a flange. The bump defines a cavity. The semiconductor device is mounted on the bump at the cavity, electrically connected to the build-up circuitry and thermally connected to the bump. The bump extends from the base into an opening in the adhesive, the base extends vertically from the bump opposite the cavity and the flange extends laterally from the bump at the cavity entrance. The build-up circuitry includes a dielectric layer and conductive traces on the semiconductor device and the flange. The conductive traces provide signal routing for the semiconductor device. | 05-24-2012 |
20120129298 | METHOD OF MAKING STACKABLE SEMICONDUCTOR ASSEMBLY WITH BUMP/FLANGE HEAT SPREADER AND DUAL BUILD-UP CIRCUITRY - A method of making a stackable semiconductor assembly that includes a semiconductor device, a heat spreader, an adhesive, a plated through-hole, first build-up circuitry and second build-up circuitry is disclosed. The heat spreader includes a bump and a flange. The bump defines a cavity. The semiconductor device is mounted on the bump at the cavity, electrically connected to the first build-up circuitry and thermally connected to the bump. The bump extends into an opening in the adhesive and the flange extends laterally from the bump at the cavity entrance. The first build-up circuitry and the second build-up circuitry extend beyond the semiconductor device in opposite vertical directions. The plated through-hole extends through the adhesive and provides signal routing between the first build-up circuitry and the second build-up circuitry. The heat spreader provides heat dissipation for the semiconductor device. | 05-24-2012 |
20150118794 | SEMICONDUCTOR DEVICE WITH FACE-TO-FACE CHIPS ON INTERPOSER AND METHOD OF MANUFACTURING THE SAME - A method of making a semiconductor device with face-to-face chips on interposer includes the step of attaching a chip-on-interposer subassembly on a heat spreader with the chip inserted into a cavity of the heat spreader so that the heat spreader provides mechanical support for the interposer. The heat spreader also provides thermal dissipation, electromagnetic shielding and moisture barrier for the enclosed chip. In the method, a second chip is also electrically coupled to a second surface of the interposer and an optional second heat spreader is attached to the second chip. | 04-30-2015 |
20150130046 | SEMICONDUCTOR PACKAGE WITH PACKAGE-ON-PACKAGE STACKING CAPABILITY AND METHOD OF MANUFACTURING THE SAME - The present invention relates to a method of making a semiconductor package with package-on-package stacking capability. In accordance with a preferred embodiment, the method is characterized by the step of attaching a chip-on-interposer subassembly on a metallic carrier with the chip inserted into a cavity of the metallic carrier, and the step of selectively removing portions of the metallic carrier to define a heat spreader for the chip. The heat spreader can provide thermal dissipation, electromagnetic shielding and moisture barrier, whereas the interposer provides a CTE-matched interface and fan-out routing for the chip. | 05-14-2015 |
20150137338 | SEMICONDUCTOR ASSEMBLY AND METHOD OF MANUFACTURING THE SAME - A method of making a semiconductor assembly is characterized by the step of attaching a chip-on-interposer subassembly on a base carrier with the chip inserted into a through opening of the base carrier and the interposer laterally extending beyond the through opening. The base carrier provides a platform for the chip-on-interposer subassembly attachment, whereas the interposer provides primary fan-out routing for the chip. In the method, a buildup circuitry is electrically coupled to the interposer and an optional cover sheet or additional buildup circuitry can be provided on the chip. | 05-21-2015 |
20150155256 | SEMICONDUCTOR PACKAGE WITH PACKAGE-ON-PACKAGE STACKING CAPABILITY AND METHOD OF MANUFACTURING THE SAME - A method of making a semiconductor package with package-on-package stacking capability is characterized by the step of attaching a chip-on-interposer subassembly on a base carrier with the chip inserted into a through opening of the base carrier and the interposer laterally extending beyond the through opening. The interposer provides primary fan-out routing for the chip whereas dual buildup circuitries formed on both opposite sides of the base carrier provides further fan-out routing and are electrically connected to each other by plated through holes to provide the package with stacking capacity. | 06-04-2015 |
20150235935 | SEMICONDUCOR DEVICE AND METHOD OF MANUFACTURING THE SAME - A method of making a semiconductor device is characterized by the step of attaching a chip-on-interposer subassembly to a heat spreader with the chip inserted into a cavity of the heat spreader and the interposer laterally extending beyond the cavity. The interposer backside process is executed after the chip-on-interposer attachment and encapsulation to form the finished interposer. The heat spreader provides thermal dissipation, and the finished interposer provides primary fan-out routing for the chip. In the method, a buildup circuitry is electrically coupled to the interposer to provide further fan-out routing. | 08-20-2015 |
20150257316 | METHOD OF MAKING THERMALLY ENHANCED WIRING BOARD HAVING ISOLATOR INCORPORATED THEREIN - A method of making a wiring board having a low CTE isolator incorporated in a resin core is characterized by the provision of an adhesive substantially coplanar with the metallized isolator and the metal layers on two opposite sides of the resin core at smoothed lapped top and bottom surfaces so that a metal bridge can be deposited on the adhesive at the smoothed lapped bottom surface and connect the metallized isolator with a surrounding heat spreader on the bottom surface of the resin core. In the method, routing circuitries are also deposited on the adhesive at the smoothed lapped top surface so as to provide electrical connections between contact pads on the isolator and terminal pads on the resin core. | 09-10-2015 |
20150382444 | THERMALLY ENHANCED WIRING BOARD HAVING METAL SLUG AND MOISTURE INHIBITING CAP INCORPORATED THEREIN AND METHOD OF MAKING THE SAME - A method of making a wiring board having a metal slug incorporated in a resin core is characterized by the provision of a moisture inhibiting cap covering interfaces between metal and plastic. In a preferred embodiment, the metal slug is bonded to the resin core by an adhesive substantially coplanar with the metal slug and the metal layers on two opposite sides of the resin core at smoothed lapped top and bottom surfaces so that a metal bridge can be deposited on the adhesive at the smoothed lapped bottom surface to completely cover interfaces between the metal slug and the surrounding plastic material. In the method, conductive traces are also deposited on the resin core at the smoothed lapped top surface so as to provide electrical contacts for chip connection. | 12-31-2015 |
20150382468 | WIRING BOARD HAVING ELECTRICAL ISOLATOR AND MOISTURE INHIBITING CAP INCORPORATED THEREIN AND METHOD OF MAKING THE SAME - A method of making a wiring board having an electrical isolator and metal posts incorporated in a resin core is characterized by the provision of moisture inhibiting caps covering interfaces between the electrical isolator/metal posts and a surrounding plastic material. In a preferred embodiment, the electrical isolator and metal posts are bonded to the resin core by an adhesive substantially coplanar with the metal films on the electrical isolator, the metal posts and the metal layers on two opposite sides of the resin core at smoothed lapped top and bottom surfaces so that a metal bridge can be deposited on the adhesive at the smoothed lapped bottom surface to completely cover interfaces between the electrical isolator/metal posts and the surrounding plastic material. Conductive traces are also deposited on the smoothed lapped top surface to provide electrical contacts for chip connection and electrically coupled to the metal posts. | 12-31-2015 |
20160005717 | SEMICONDUCTOR DEVICE WITH FACE-TO-FACE CHIPS ON INTERPOSER AND METHOD OF MANUFACTURING THE SAME - A method of making a semiconductor device with face-to-face chips on interposer includes the step of attaching a chip-on-interposer subassembly on a heat spreader with the chip inserted into a cavity of the heat spreader so that the heat spreader provides mechanical support for the interposer. The heat spreader also provides thermal dissipation, electromagnetic shielding and moisture barrier for the enclosed chip. In the method, a second chip is also electrically coupled to a second surface of the interposer and an optional second heat spreader is attached to the second chip. | 01-07-2016 |
Patent application number | Description | Published |
20100102307 | Method of zinc oxide film grown on the epitaxial lateral overgrowth gallium nitride template - A growth method is proposed for high quality zinc oxide comprising the following steps: (1) growing a gallium nitride layer on a sapphire substrate around a temperature of 1000° C.; (2) patterning a SiO | 04-29-2010 |
20100135899 | PROCESS FOR RELEASING HYDROGEN GAS - A process for releasing hydrogen gas is disclosed. The process comprises the step of irradiating hydrogen storage particles dispersed within thermal promoter particles under conditions to release said hydrogen from said hydrogen storage particles. A system for implementing the process as well as uses for the hydrogen gas released from the above process are disclosed. | 06-03-2010 |
20110053050 | METHOD OF FUNCTIONALIZING A CARBON MATERIAL - The present invention relates to a method of functionalizing a carbon material. A carbon material is contacted with a carboxylic acid, whereby a mixture is formed. The mixture is heated for a suitable period of time at a temperature below the thermal decomposition temperature of the carbon material. | 03-03-2011 |
20120018699 | METHOD OF ZINC OXIDE FILM GROWN ON THE EPITAXIAL LATERAL OVERGROWTH GALLIUM NITRIDE TEMPLATE - A growth method is proposed for high quality zinc oxide comprising the following steps: (1) growing a gallium nitride layer on a sapphire substrate around a temperature of 1000° C.; (2) patterning a SiO | 01-26-2012 |
20140087192 | CONDUCTING POLYMER/GRAPHENE-BASED MATERIAL COMPOSITES, AND METHODS FOR PREPARING THE COMPOSITES - A composite comprising a conducting polymer and a graphene-based material is provided. The composite includes a graphene-based material doped with nitrogen or having a nitrogen-containing species grafted thereon, and a conducting polymer arranged on the graphene-based material. Methods of preparing the composite, and electrodes formed from the composite are also provided. | 03-27-2014 |
Patent application number | Description | Published |
20150140555 | METHOD OF IDENTIFYING FOETAL ERYTHROBLAST - There is provided a method for identifying at least one foetal erythroblast the method comprising: (a) detecting the expression of at least one foetal erythroblast specific marker selected from the group consisting of neutral amino acid transporter B (SLC1A5), solute carrier family 3 (activators of dibasic and neutral amino acid transport) member 2 isoform A (SLC3A2), Splice Isoform A of Chloride channel protein 6, Transferrin receptor protein 1, Splice Isoform 3 of Protein GPR107 precursor, Olfactory receptor 11H4, Splice Isoform 1 of Protein C9orf5, Cleft lip and palate transmembrane protein 1, BCG induced integral membrane protein BIGM103, Antibacterial protein FALL-39 precursor, CAAX prenyl protease 1 homolog, Splice Isoform 2 of Synaptophysin-like protein, Vitamin K epoxide reductase complex subunit 1-like protein 1, Splice Isoform 1 of Protein C20orf22 (ABHD12), Hypothetical protein DKFZp564K247 (Hypoxia induced gene 1 protein) (IPI Accession No. IPI00295621), Hypothetical protein DK-FZp586C1924 (IPI Accession No. IPI00031064), ALEX3 protein variant, Hypothetical protein MGC14288 (IPI Accession No. IPI00176708), protein with IPI Accession No. IPI00639803 and protein with IPI Accession No. IPI00646289, wherein detection of the marker indicates the presence of the foetal erythroblast. | 05-21-2015 |
Patent application number | Description | Published |
20080217726 | INTEGRATED CIRCUIT SYSTEM EMPLOYING DIPOLE MULTIPLE EXPOSURE - An integrated circuit system that includes: providing a first mask including a first feature; exposing the first mask to a radiation source to form an image of the first feature on a photoresist material that is larger than a structure to be formed, the photoresist material being formed over a substrate that includes the integrated circuit system; providing a second mask including a second feature; aligning the second mask over the image of the first mask to form an overlap region; and exposing the second mask to the radiation source to form an image of the second feature on the photoresist material that is larger than the structure to be formed. | 09-11-2008 |
20090102069 | INTEGRATED CIRCUIT SYSTEM WITH ASSIST FEATURE - An integrated circuit system comprising: providing a substrate; forming a main feature using a first non-cross-junction assist feature over the substrate; forming the main feature using a second non-cross-junction assist feature, adjacent a location of the first non-cross-junction feature, over the substrate; and forming an integrated circuit having the substrate with the main feature thereover. | 04-23-2009 |
20090181551 | INTEGRATED CIRCUIT SYSTEM EMPLOYING MULTIPLE EXPOSURE DUMMY PATTERNING TECHNOLOGY - An integrated circuit system that includes: providing a substrate coated with a photoresist material; exposing the photoresist material to an energy source through a first mask to form a first substrate feature and a second substrate feature therein; and exposing the photoresist material to the energy source through a second mask to transform the second substrate feature into another one of the first substrate feature therein. | 07-16-2009 |
20090214984 | METHODS FOR ENHANCING PHOTOLITHOGRAPHY PATTERNING - A method for fabricating a a semiconductor device that includes: providing a substrate prepared with a photoresist layer; providing a photomask comprising a first and a second pattern having a respective first and second pitch range; providing a composite aperture comprising a first and a second off-axis illumination aperture pattern, the first off-axis aperture pattern having a configuration that improves the process window of the first pitch range and the second off-axis aperture pattern having a configuration that improves the process window for a second pitch range; exposing the photoresist layer on the substrate with radiation from an exposure source through the composite aperture and the photomask; and developing the photoresist layer to pattern the photoresist layer. | 08-27-2009 |
20100197140 | ANGLED-WEDGE CHROME-FACE WALL FOR INTENSITY BALANCE OF ALTERNATING PHASE SHIFT MASK - A method for forming a semiconductor device is presented. The method includes providing a substrate having a photoresist thereon and transmitting a light source through a mask having a pattern onto the photoresist. The mask comprises a mask substrate having first, second and third regions, the third region is disposed between the first and second regions. The mask also includes a light reducing layer over the mask substrate having a first opening over the first region and a second opening over the second region. The first and second openings have layer sidewalls. The sidewalls of the light reducing layer are slanted at an angle less than 90 degrees with the plane of a top surface of the mask substrate. The method also includes developing the photoresist to transfer the pattern of the mask to the photoresist. | 08-05-2010 |
Patent application number | Description | Published |
20100196805 | MASK AND METHOD TO PATTERN CHROMELESS PHASE LITHOGRAPHY CONTACT HOLE - A method of making a mask is disclosed. The method includes providing a first and a second mask layers and disposing a first phase shift region on the first mask layer. A second phase shift region is disposed on the second mask layer, wherein the first and second phase shift regions are out of phase. A continuous unit cell is formed in the first phase shift region. The unit cell comprises a center section and distinct extension sections. The extension sections are contiguous to and extend outwards from the center section. The distinct extension sections have a same width as the center section. The second phase shift region is adjacent to the unit cell in the first phase shift region. | 08-05-2010 |
20140019927 | WAFERLESS MEASUREMENT RECIPE - Embodiments relate to a method for manufacturing and processing semiconductor devices or integrated circuits (IC) and in particular to the generation of measurement recipes in the manufacturing of the semiconductor devices or ICs. The method comprises defining a sampling plan, mapping target locations of a device contained in the sampling plan to an article/a wafer having a plurality of said devices, verifying the mapping file and processing the verification to produce a measurement recipe. In one embodiment, the measurement recipe is created without having the actual processed wafer. | 01-16-2014 |
20140050439 | LITHO SCANNER ALIGNMENT SIGNAL IMPROVEMENT - A method and a device are provided for diffracting incident light from a lithographic scanner in an IC process flow. Embodiments include forming a diffraction grating in a first layer on a semiconductor substrate; and forming a plurality of lithographic alignment marks in a second layer, overlying the first layer, wherein the diffraction grating has a width and a length greater than or equal to a width and length, respectively, of the plurality of lithographic alignment marks. | 02-20-2014 |
20140170539 | DETERMINATION OF LITHOGRAPHY TOOL PROCESS CONDITION - A method for forming an integrated circuit (IC) is presented. The method includes providing a wafer having a substrate prepared with a photoresist layer. The photoresist layer is processed by passing a radiation from an exposure source of a lithography tool through a mask having a pattern. The process parameters of the lithography tool are determined by performing a pattern matching process. The photoresist layer is developed to transfer the pattern on the mask to the photoresist layer. | 06-19-2014 |
Patent application number | Description | Published |
20130030122 | ELASTOMERS CROSSLINKED BY POLYLACTIC ACID - A composition is provided, which comprises chains comprising a first graft copolymer of a first elastomer and a poly(L-lactic acid), and chains comprising a second graft copolymer of a second elastomer and a poly(D-lactic acid). At least some of the poly(L-lactic acid) and poly(D-lactic acid) crosslink the chains. Poly(L-lactic acid) and poly(D-lactic acid) may form stereocomplexes that crosslink the chains. The chains may be crosslinked by crystalline structures formed from at least some of the poly(L-lactic acid) and poly(D-lactic acid) in discrete regions. The crosslinked chains may form a matrix. In a method of forming the composition, the first and second graft copolymers are mixed, such as by melt blending or solution casting, to form the composition. The graft copolymers may be formed by a “grafting-though” or “grafting-from” process. The composition may be useful under a relatively wide range of temperatures. | 01-31-2013 |
20130030128 | THERMOPLASTIC COMPOSITION FORMED FROM POLYLACTIC ACID AND ELASTOMERIC GRAFT COPOLYMER - The brittleness of a thermoplastic material containing a polylactic acid may be reduced by melting and mixing the thermoplastic material and a graft copolymer to link the graft copolymer to thermoplastic polymer to form a new thermoplastic material with reduced brittleness. The graft copolymer comprises an elastomeric backbone and a side chain grafted to the backbone. The side chain comprises a enantiomer of lactic acid opposite to the enantiomer in the thermoplastic material. A composition comprises a thermoplastic polymer and the graft copolymer, where the graft copolymer is linked to the thermoplastic polymer by the enantiomers. A method of forming the composition may comprise melting precursors for the thermoplastic polymer and the graft copolymer, and mixing the precursors to allow the lactic acids to link the graft copolymer to the thermoplastic polymer. | 01-31-2013 |
20140046005 | HYBRID POLYMERS - Described herein are polymers comprising a polyester and at least one polyhedral oligomeric silsesquioxane, wherein the polyester is capable of forming a stereocomplex with a polymer comprising a complimentary polyester and composites thereof. | 02-13-2014 |
Patent application number | Description | Published |
20080315317 | SEMICONDUCTOR SYSTEM HAVING COMPLEMENTARY STRAINED CHANNELS - A semiconductor system is provided including providing a semiconductor substrate; forming PMOS and NMOS transistors in and on the semiconductor substrate; forming a tensile strained layer on the semiconductor substrate; and relaxing the tensile strained layer around the PMOS transistor. | 12-25-2008 |
20090026549 | METHOD TO REMOVE SPACER AFTER SALICIDATION TO ENHANCE CONTACT ETCH STOP LINER STRESS ON MOS - An example process to remove spacers from the gate of a NMOS transistor. A stress creating layer is formed over the NMOS and PMOS transistors and the substrate. In an embodiment, the spacers on gate are removed so that stress layer is closer to the channel of the device. The stress creating layer is preferably a tensile nitride layer. The stress creating layer is preferably a contact etch stop liner layer. In an embodiment, the gates, source and drain region have a silicide layer thereover before the stress creating layer is formed. The embodiment improves the performance of the NMOS transistors. | 01-29-2009 |
20090085122 | POLY PROFILE ENGINEERING TO MODULATE SPACER INDUCED STRESS FOR DEVICE ENHANCEMENT - The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate. | 04-02-2009 |
20090315115 | Implantation for shallow trench isolation (STI) formation and for stress for transistor performance enhancement - A method (and semiconductor device) of fabricating a semiconductor device provides a shallow trench isolation (STI) structure or region by implanting ions in the STI region. After implantation, the region (of substrate material and ions of a different element) is thermally annealed producing a dielectric material operable for isolating two adjacent field-effect transistors (FET). This eliminates the conventional steps of removing substrate material to form the trench and refilling the trench with dielectric material. Implantation of nitrogen ions into an STI region adjacent a p-type FET applies a compressive stress to the transistor channel region to enhance transistor performance. Implantation of oxygen ions into an STI region adjacent an n-type FET applies a tensile stress to the transistor channel region to enhance transistor performance. | 12-24-2009 |
20100041242 | Double Anneal with Improved Reliability for Dual Contact Etch Stop Liner Scheme - A method for forming a device with both PFET and NFET transistors using a PFET compressive etch stop liner and a NFET tensile etch stop liner and two anneals in a deuterium containing atmosphere. The method comprises: providing a NFET transistor in a NFET region and a PFET transistor in a PFET region. We form a NFET tensile contact etch-stop liner over the NFET region. Then we perform a first deuterium anneal. We form a PFET compressive etch stop liner over the PFET region. We form a (ILD) dielectric layer with contact openings over the substrate. We perform a second deuterium anneal. The temperature of the second deuterium anneal is less than the temperature of the first deuterium anneal. | 02-18-2010 |
20100059831 | Spacer-less Low-K Dielectric Processes - A first example embodiment provides a method of removing first spacers from gates and incorporating a low-k material into the ILD layer to increase device performance. A second example embodiment comprises replacing the first spacers after silicidation with low-k spacers. This serves to reduce the parasitic capacitances. Also, by implementing the low-k spacers only after silicidation, the embodiments' low-k spacers are not compromised by multiple high dose ion implantations and resist strip steps. The example embodiments can improve device performance, such as the performance of a rim oscillator. | 03-11-2010 |
20110266628 | POLY PROFILE ENGINEERING TO MODULATE SPACER INDUCED STRESS FOR DEVICE ENHANCEMENT - The present invention provides a method of inducing stress in a semiconductor device substrate by applying an ion implantation to a gate region before a source/drain annealing process. The source/drain region may then be annealed along with the gate which will cause the gate to expand in certain areas due to said ion implantation. As a result, stress caused by said expansion of the gate is transferred to the channel region in the semiconductor substrate. | 11-03-2011 |
Patent application number | Description | Published |
20100228798 | GEOGRAPHICAL DISTRIBUTED STORAGE SYSTEM BASED ON HIERARCHICAL PEER TO PEER ARCHITECTURE - A geographically distributed storage system including a global Peer-To-Peer (P2P) ring and a local P2P ring. The global P2P ring includes all storage nodes and the local P2P ring includes a group of the storage nodes. Each of the group of storage node belongs to the global P2P ring and the local P2P ring and each storage node includes global and local management information. The global management information includes a node table for managing topology information of a network connecting the group, a metadata table for managing locations of stored data objects, and a global routing table for managing routing in the global P2P ring. The local management information includes an object management table for managing stored data objects in the group, a Logical Unit (LU) management table for managing logical units in the group and a local routing table used for managing routing in the local P2P ring. | 09-09-2010 |
20130218934 | METHOD FOR DIRECTORY ENTRIES SPLIT AND MERGE IN DISTRIBUTED FILE SYSTEM - A distributed storage system has MDSs (metadata servers). Directories of file system namespace are distributed to the MDSs based on hash value of inode number of each directory. Each directory is managed by a master MDS. When a directory grows with a file creation rate greater than a preset split threshold, the master MDS constructs a consistent hashing overlay with one or more slave MDSs and splits directory entries of the directory to the consistent hashing overlay based on hash values of file names under the directory. The number of MDSs in the consistent hashing overlay is calculated based on the file creation rate. When the directory continues growing with a file creation rate that is greater than the preset split threshold, the master MDS adds a slave MDS into the consistent hashing overlay and splits directory entries to the consistent hashing overlay based on hash values of file names. | 08-22-2013 |
20130332608 | LOAD BALANCING FOR DISTRIBUTED KEY-VALUE STORE - According to one embodiment of load balancing, a system comprises a plurality of nodes being configured to allow input/output (I/O) access to a plurality of data, each data being accessed as a value via a unique key which is associated with the value as a key-value pair, the data being distributed and stored among the plurality of nodes based on hush values of the keys. Each node includes an I/O module to record a number of I/O accesses to each key of a plurality of keys associated with the plurality of data as values, respectively, to form key-value pairs. If resource utilization of a node exceeds a preset threshold, then the node is an overloaded node, and the overloaded node migrates out a part of the key-value pairs in the overloaded node in order to reduce the resource utilization to a level below the preset threshold. | 12-12-2013 |
20140188953 | DIRECTORY-LEVEL REFERRAL METHOD FOR PARALLEL NFS WITH MULTIPLE METADATA SERVERS - An aspect of the invention is directed to a plurality of MDSs (metadata servers) in a distributed storage system which includes data servers storing file contents, each MDS having a processor and a memory and storing file system metadata. Directories of a file system namespace are distributed to the MDSs through referral directories referring to real directories using hash value of inode number of each of the referral directories. During a process to create a directory in the file system namespace, a first MDS dynamically creates a referral directory in the first MDS, and creates a real directory in a second MDS, the referral directory in the first MDS referring to the real directory in the second MDS by maintaining location information of the real directory in the second MDS, the real directory in the second MDS containing the file system metadata for the directory in the file system namespace. | 07-03-2014 |
20140379722 | SYSTEM AND METHOD TO MAXIMIZE SERVER RESOURCE UTILIZATION AND PERFORMANCE OF METADATA OPERATIONS - An MDS (metadata server) in a distributed storage system includes data servers (DSs) storing file contents and one or more MDSs performing metadata operations in response to metadata requests of different types, the MDS including a controller having a processor and a memory, the MDS storing file system metadata. The controller is configured to: classify the metadata operations into different categories, which include a normal category and one or more special categories different from the normal category, the normal category having a primary stage which does not involve communication between the MDS and a component external to the MDS; for each special category, partition each metadata operation into a plurality of stages at least one of which involves communication between the MDS and a component external to the MDS; and dynamically assign resources to each of the partitioned stage based on monitored workloads of the different types of metadata requests. | 12-25-2014 |
20150227540 | SYSTEM AND METHOD FOR CONTENT-AWARE DATA COMPRESSION - Exemplary embodiments provide a data compression technique which chooses a compression method without compressing data. A storage system comprises a storage media and a controller. The controller is operable to: determine a compression method to be used to compress a data block of uncompressed data based on one or more characteristics of data content of the uncompressed data prior to compressing the data block; and compress the data block of the uncompressed data using the determined compression method. In some embodiments, the controller is operable to determine the compression method based on a compression rule which relates one or more characteristics of data content and compression methods. In specific embodiments, the storage system further comprises a flash memory device which includes the controller to determine the compression method and to compress the data block. | 08-13-2015 |
Patent application number | Description | Published |
20130187231 | ESD PROTECTION CIRCUIT - A device having a substrate defined with a device region which includes an ESD protection circuit is disclosed. The ESD protection circuit has first and second transistors. A transistor includes a gate having first and second sides, a first diffusion region in the device region adjacent to the first side of the gate, and a second diffusion region in the device region displaced away from the second side of the gate. The first and second diffusion regions include dopants of a first polarity type. The device includes a first device well which encompasses the device region and second device wells which are disposed within the first device well. A well contact is coupled to the second device wells. The well contact surrounds the gates of the transistors and abuts the first diffusion regions of the transistors. | 07-25-2013 |
20130207179 | ESD PROTECTION CIRCUIT - A device which includes a substrate defined with a device region with an ESD protection circuit having at least first and second transistors is disclosed. Each of the transistors includes a gate having first and second sides, a first diffusion region in the device region adjacent to the first side of the gate, a second diffusion region in the device region displaced away from the second side of the gate, and a drift isolation region disposed between the gate and the second diffusion region. A first device well encompasses the device region and a second device well is disposed within the first device well. The device also includes a drift well which encompasses the second diffusion region. Edges of the drift well do not extend below the gate and is away from a channel region. A drain well is disposed under the second diffusion region and within the drift well. | 08-15-2013 |
20130235496 | ESD-ROBUST I/O DRIVER CIRCUITS - An ESD-robust I/O driver circuit is disclosed. Embodiments include providing a first NMOS transistor having a first source, a first drain, and a first gate; coupling the first source to a ground rail and the first drain to an I/O pad; coupling a gate driver control circuit to the first drain and the first gate; and providing a ground potential to the first gate, via the gate driver control circuit, during an ESD event occurring from the I/O pad to the ground rail. | 09-12-2013 |
20130235498 | CROSS-DOMAIN ESD PROTECTION SCHEME - A cross-domain ESD protection scheme is disclosed. Embodiments include coupling a first power clamp to a first power rail and a first ground rail; providing a first NMOS transistor having a first source, a first drain, and a first gate; coupling the first source to a second ground rail; providing a first PMOS transistor having a second source, a second drain, and a second gate; coupling the second source to the first power rail; and providing, via the first power clamp, a signal to turn on the first NMOS transistor during an ESD event that occurs at the first power rail. | 09-12-2013 |
20130279052 | ESD PROTECTION DEVICE WITH A TUNABLE HOLDING VOLTAGE FOR A HIGH VOLTAGE PROGRAMMING PAD - An ESD protection device with a tunable holding voltage is disclosed. Embodiments include: providing a silicon-controlled rectifier (SCR) having a first n-type layer with a cathode connection, a first p-type layer with a first control connection, a second n-type layer with a second control connection, and a second p-type layer with an anode connection; coupling the anode connection to a power rail; coupling the cathode connection to a ground rail; providing a tunable holding voltage control unit including a first NMOS having a first gate, a first drain, and a first source, wherein during an ESD event, the first NMOS is turned off and a holding voltage of the SCR is low; coupling the first drain to the first control connection; coupling the first source to the ground rail; and coupling the first gate to a program circuit. | 10-24-2013 |
20130321961 | ESD PROTECTION DEVICE FOR CIRCUITS WITH MULTIPLE POWER DOMAINS - A ESD protection scheme is disclosed for circuits with multiple power domains. Embodiments include: coupling a first power clamp to a first power rail and a first ground rail of a first domain; coupling a second power clamp to a second power rail and a second ground rail of a second domain; providing a blocking circuit for blocking current from an ESD event; providing an I/O interface connection in the first domain for transmitting signals from the first domain to the blocking circuit; providing a core interface connection in the second domain for transmitting signals from the blocking circuit to the second domain; coupling an input connection of the blocking circuit to the I/O interface connection; and coupling an output connection of the blocking circuit to a core interface connection. | 12-05-2013 |
20130321962 | ESD-ROBUST I/O DRIVER CIRCUITS - An ESD-robust I/O driver circuit is disclosed. Embodiments include providing a first NMOS transistor having a first source, a first drain, and a first gate; coupling the first source is coupled to a ground rail, and the first drain to an I/O pad; providing a gate driver control circuit including a second NMOS transistor having a second source, a second drain, and a second gate; and coupling the second drain to the first gate, the second source to the ground rail, wherein the gate driver control circuit provides a ground potential to the first gate during an ESD event occurring from the I/O pad to the ground rail. | 12-05-2013 |
20140160604 | LATCH-UP FREE RC-BASED NMOS ESD POWER CLAMP IN HV USE - An RC-based electrostatic discharge protection device provides an extended snapback trigger voltage range, thereby avoiding latch-up. Two parallel current discharge paths are provided between supply terminals during an electrostatic discharge event by virtue of an added external resistor. The first current discharge path includes body resistance of the protection device and the second current discharge path includes the external resistor. | 06-12-2014 |
20140160605 | HIGH NOISE IMMUNITY WITH LATCH-UP FREE ESD CLAMP - A triple stack NMOS integrated circuit structure protection circuit for a plurality of terminals operative at respective voltage levels is coupled between the plurality of terminals. First and second NMOS elements of the triple stack NMOS share a common active region. A third NMOS element, vertically positioned with respect to the first and second NMOS elements, has an active region separate from the active region of the first and second NMOS elements. The first, second and third NMOS elements are connected in series between two terminals of the plurality of terminals. | 06-12-2014 |
Patent application number | Description | Published |
20110224565 | METHOD OF PREDICTING ACUTE CARDIOPULMONARY EVENTS AND SURVIVABILITY OF A PATIENT - According to embodiments of the invention, there is provided a method of producing an artificial neural network capable of predicting the survivability of a patient, the method including: storing in an electronic database patient health data, the patient health data comprising a plurality of sets of data, each set having at least one of a first parameter relating to heart rate variability data and a second parameter relating to vital sign data, each set further having a third parameter relating to patient survivability; providing a network of nodes interconnected to form an artificial neural network, the nodes comprising a plurality of artificial neurons, each artificial neuron having at least one input with an associated weight; and training the artificial neural network using the patient health data such that the associated weight of the at least one input of each artificial neuron of the plurality of artificial neurons is adjusted in response to respective first, second and third parameters of different sets of data from the patient health data, such that the artificial neural network is trained to produce a prediction on the survivability of a patient. | 09-15-2011 |
20130237776 | METHOD OF PREDICTING ACUTE CARDIOPULMONARY EVENTS AND SURVIVABILITY OF A PATIENT - A method of producing an artificial neural network capable of predicting the survivability of a patient, including: storing in an electronic database patient health data comprising a plurality of sets of data, each set having at least one of a first parameter relating to heart rate variability data and a second parameter relating to vital sign data, each set further having a third parameter relating to patient survivability; providing a network of nodes interconnected to form an artificial neural network, the nodes comprising a plurality of artificial neurons, each artificial neuron having at least one input with an associated weight; and training the artificial neural network using the patient health data such that the associated weight of the at least one input of each artificial neuron is adjusted in response to respective first, second and third parameters of different sets of data from the patient health data. | 09-12-2013 |
20140187988 | METHOD OF PREDICTING ACUTE CARDIOPULMONARY EVENTS AND SURVIVABILITY OF A PATIENT - A method of producing an artificial neural network capable of predicting the survivability of a patient, including: storing in an electronic database patient health data comprising a plurality of sets of data, each set having at least one of a first parameter relating to heart rate variability data and a second parameter relating to vital sign data, each set further having a third parameter relating to patient survivability; providing a network of nodes interconnected to form an artificial neural network, the nodes comprising a plurality of artificial neurons, each artificial neuron having at least one input with an associated weight; and training the artificial neural network using the patient health data such that the associated weight of the at least one input of each artificial neuron is adjusted in response to respective first, second and third parameters of different sets of data from the patient health data. | 07-03-2014 |
20140257063 | METHOD OF PREDICTING ACUTE CARDIOPULMONARY EVENTS AND SURVIVABILITY OF A PATIENT - A method of producing an artificial neural network capable of predicting the survivability of a patient, including: storing in an electronic database patient health data comprising a plurality of sets of data, each set having at least one of a first parameter relating to heart rate variability data and a second parameter relating to vital sign data, each set further having a third parameter relating to patient survivability; providing a network of nodes interconnected to form an artificial neural network, the nodes comprising a plurality of artificial neurons, each artificial neuron having at least one input with an associated weight; and training the artificial neural network using the patient health data such that the associated weight of the at least one input of each artificial neuron is adjusted in response to respective first, second and third parameters of different sets of data from the patient health data. | 09-11-2014 |
20150150468 | SYSTEM AND METHOD FOR PREDICTING ACUTE CARDIOPULMONARY EVENTS AND SURVIVABILITY OF A PATIENT - A method of producing an artificial neural network capable of predicting the survivability of a patient, including: storing in an electronic database patient health data comprising a plurality of sets of data, each set having at least one of a first parameter relating to heart rate variability data and a second parameter relating to vital sign data, each set further having a third parameter relating to patient survivability; providing a network of nodes interconnected to form an artificial neural network, the nodes comprising a plurality of artificial neurons, each artificial neuron having at least one input with an associated weight; and training the artificial neural network using the patient health data such that the associated weight of the at least one input of each artificial neuron is adjusted in response to respective first, second and third parameters of different sets of data from the patient health data. | 06-04-2015 |
20150223759 | PREDICTING ACUTE CARDIOPULMONARY EVENTS AND SURVIVABILITY OF A PATIENT - A method of predicting survivability of a patient. The method includes storing in an electronic database patient health data comprising a plurality of sets of data, each set having a first parameter relating to heart rate variability data including at least one of ST segment elevation and depression, a second parameter relating to vital sign data, and a third parameter relating to patient survivability; providing a network of nodes interconnected to form an artificial neural network, the nodes comprising a plurality of neurons, each having at least one input with an associated weight; and training the neural network using the patient health data such that the associated weight of the at least one input of each neuron is adjusted in response to respective first, second and third parameters of different sets of data from the patient health data, such that the neural network is trained to produce a prediction on the survivability of a patient within the next 72 hours. | 08-13-2015 |
Patent application number | Description | Published |
20150100238 | LARGE SCALE DEMAND RESPONSIVE TRANSIT FRAMEWORK - Described herein is a descriptive framework to facilitate large scale demand responsive transit. In accordance with one aspect of the framework, one or more trip requests from one or more commuter devices are received. A trip request indicates at least one start location and at least one end location. In addition, vehicle information is received from one or more available vehicles. The vehicle information indicates at least one current location of a vehicle. An adaptive route for the vehicle may be planned based on the one or more trip requests and the vehicle information. Update information of the adaptive route may be communicated to the vehicle and the one or more commuter devices. | 04-09-2015 |
20150154810 | VIRTUAL TRANSPORTATION STANDS - Described herein is a framework for coordinating transportation. In accordance with one implementation, the framework creates or selects a virtual transportation stand in response to a commuter request. The virtual transportation stand may be created or selected based at least in part on current location information associated with a mobile device. Information associated with the virtual transportation stand may then be provided to the commuter mobile device and a vehicle notification device. The virtual transportation stand may further be removed if it is no longer in demand. | 06-04-2015 |
20150269642 | INTEGRATED SHOPPING ASSISTANCE FRAMEWORK - Described herein is a framework for an integrated shopping assistance. In accordance with one aspect, the framework may detect a customer in an establishment. The framework may detect the customer by determining location proximity data of one or more detected customer-registered devices in an establishment. The framework may further perform, based on one or more data sources, image recognition of a captured image of a customer. Information associated to the customer may be retrieved from the one or more data sources. Real-time analytics may further be performed based at least in part on the location proximity data and the retrieved customer information. The framework may present, via a client device, a notification based on the location proximity data, a verification of the customer, the associated customer information, and results of the analytics. | 09-24-2015 |