Patent application number | Description | Published |
20080314521 | DEVICE WITH SELF ALIGNED GAPS FOR CAPACITANCE REDUCTION - A method for reducing capacitances between semiconductor device wirings is provided. A sacrificial layer is formed over a dielectric layer. A plurality of features are etched into the sacrificial layer and dielectric layer. The features are filled with a filler material. The sacrificial layer is removed, so that parts of the filler material remain exposed above a surface of the dielectric layer, where spaces are between the exposed parts of the filler material, where the spaces are in an area formerly occupied by the sacrificial layer. Widths of the spaces between the parts of the filler material are shrunk with a shrink sidewall deposition. Gaps are etched into the dielectric layer through the shrink sidewall deposition. The filler material and shrink sidewall deposition are removed. | 12-25-2008 |
20090121324 | ETCH WITH STRIATION CONTROL - A method for etching a feature in an etch layer is provided. A patterned photoresist mask is formed over the etch layer with photoresist features with sidewalls wherein the sidewalls of the photoresist features have striations forming peaks and valleys. The striations of the sidewalls of the photoresist features are reduced. The reducing the striations comprises at least one cycle, wherein each cycle comprises etching back peaks formed by the striations of the sidewalls of the photoresist features and depositing on the sidewalls of the photoresist features. Features are etched into the etch layer through the photoresist features. The photoresist mask is removed. | 05-14-2009 |
20090140380 | DEVICE WITH GAPS FOR CAPACITANCE REDUCTION - A method for reducing capacitances between semiconductor devices is provided. A plurality of contact structures is formed in a dielectric layer. A mask is formed to cover the contact structures wherein the mask has mask features for exposing parts of the dielectric layer wherein the mask features have widths. The widths of the mask features are shrunk with a sidewall deposition. Gaps are etched into the dielectric layer through the sidewall deposition. The gaps are closed to form pockets in the gaps. | 06-04-2009 |
20090162553 | PROTECTIVE LAYER FOR IMPLANT PHOTORESIST - A method for implanting a dopant in a substrate is provided. A patterned photoresist mask is formed over the substrate, wherein the patterned photoresist mask has patterned photoresist mask features. A protective layer is deposited on the patterned photoresist mask by performing a cyclical deposition, wherein each cycle, comprises a depositing phase for depositing a deposition layer over surfaces of the patterned mask of photoresist material and a profile shaping phase for providing vertical sidewalls. A dopant is implanted into the substrate using an ion beam. The protective layer and photoresist mask are removed. | 06-25-2009 |
20090163035 | ETCH WITH HIGH ETCH RATE RESIST MASK - A method for etching features into an etch layer is provided. A patterned mask is formed over the etch layer, wherein the patterned mask is of a high etch rate photoresist material, wherein the patterned mask has patterned mask features. A protective layer is deposited on the patterned mask of high etch rate photoresist material by performing a cyclical deposition, wherein each cycle, comprises a depositing phase for depositing a deposition layer over the exposed surfaces, including sidewalls of the patterned mask of high etch rate photoresist material and a profile shaping phase for providing vertical sidewalls. Features are etched into the etch layer using the protective layer as a mask. The protective layer is removed. | 06-25-2009 |
20090215272 | DOUBLE MASK SELF-ALIGNED DOUBLE PATTERNING TECHNOLOGY (SADPT) PROCESS - A method for providing features in an etch layer is provided by forming an organic mask layer over the inorganic mask layer, forming a silicon-containing mask layer over the organic mask layer, forming a patterned mask layer over the silicon-containing mask layer, etching the silicon-containing mask layer through the patterned mask, depositing a polymer over the etched silicon-containing mask layer, depositing a silicon-containing film over the polymer, planarizing the silicon-containing film, selectively removing the polymer leaving the silicon-containing film, etching the organic layer, and etching the inorganic layer. | 08-27-2009 |
20090286397 | SELECTIVE INDUCTIVE DOUBLE PATTERNING - An inductively coupled power (ICP) plasma processing chamber for forming semiconductor features is provided. A plasma processing chamber is provided, comprising a vacuum chamber, at least one antenna adjacent to the vacuum chamber for providing inductively coupled power in the vacuum chamber, a substrate support for supporting a silicon substrate within the plasma processing chamber, a pressure regulator, a gas inlet for providing gas into the plasma processing chamber, and a gas outlet for exhausting gas from the plasma processing chamber. A gas distribution system is in fluid connection with the gas inlet for providing a first gas and a second gas, wherein the gas distribution system can substantially replace one of the first gas and the second gas in the plasma zone with the other of the first gas and the second gas within a period of less than 5 seconds. | 11-19-2009 |
20090311871 | ORGANIC ARC ETCH SELECTIVE FOR IMMERSION PHOTORESIST - A method for forming etch features in an etch layer over a substrate and below an organic ARC layer, which is below an immersion lithography photoresist mask is provided. The substrate with the etch layer, organic ARC layer, and immersion lithography photoresist mask is placed into a processing chamber. The organic ARC layer is opened. The organic ARC layer opening comprises flowing an organic ARC open gas mixture into the processing chamber, wherein the organic ARC open gas mixture comprises an etchant gas and a polymerization gas comprising CO, forming an organic ARC open plasma from the organic ARC open gas mixture, etching the organic ARC layer with the organic ARC open plasma until the organic ARC layer is opened, and stopping the flow of organic ARC open gas mixture into the processing chamber before the etch layer is completely etched. | 12-17-2009 |
20100178769 | SPACER FORMATION FOR ARRAY DOUBLE PATTERNING - A method for forming an array area with a surrounding periphery area, wherein a substrate is disposed under an etch layer, which is disposed under a patterned organic mask defining the array area and covers the entire periphery area is provided. The patterned organic mask is trimmed. An inorganic layer is deposited over the patterned organic mask where a thickness of the inorganic layer over the covered periphery area of the organic mask is greater than a thickness of the inorganic layer over the array area of the organic mask. The inorganic layer is etched back to expose the organic mask and form inorganic spacers in the array area, while leaving the organic mask in the periphery area unexposed. The organic mask exposed in the array area is stripped, while leaving the inorganic spacers in place and protecting the organic mask in the periphery area. | 07-15-2010 |
20110281435 | FAST GAS SWITCHING PLASMA PROCESSING APPARATUS - A plasma chamber with a plasma confinement zone with an electrode is provided. A gas distribution system for providing a first gas and a second gas is connected to the plasma chamber, wherein the gas distribution system can substantially replace one gas in the plasma zone with the other gas within a period of less than 1 s. A first frequency tuned RF power source for providing power to the electrode in a first frequency range is electrically connected to the at least one electrode wherein the first frequency tuned RF power source is able to minimize a reflected RF power. A second frequency tuned RF power source for providing power to the plasma chamber in a second frequency range outside of the first frequency range wherein the second frequency tuned RF power source is able to minimize a reflected RF power. | 11-17-2011 |
20120138227 | SPACER FORMATION FOR ARRAY DOUBLE PATTERNING - A method for forming an array area with a surrounding periphery area, wherein a substrate is disposed under an etch layer, which is disposed under a patterned organic mask defining the array area and covers the entire periphery area is provided. The patterned organic mask is trimmed. An inorganic layer is deposited over the patterned organic mask where a thickness of the inorganic layer over the covered periphery area of the organic mask is greater than a thickness of the inorganic layer over the array area of the organic mask. The inorganic layer is etched back to expose the organic mask and form inorganic spacers in the array area, while leaving the organic mask in the periphery area unexposed. The organic mask exposed in the array area is stripped, while leaving the inorganic spacers in place and protecting the organic mask in the periphery area. | 06-07-2012 |
20120205819 | DEVICE WITH GAPS FOR CAPACITANCE REDUCTION - A method for reducing capacitances between semiconductor devices is provided. A plurality of contact structures is formed in a dielectric layer. A mask is formed to cover the contact structures wherein the mask has mask features for exposing parts of the dielectric layer wherein the mask features have widths. The widths of the mask features are shrunk with a sidewall deposition. Gaps are etched into the dielectric layer through the sidewall deposition. The gaps are closed to form pockets in the gaps. | 08-16-2012 |
20120282780 | ETCH WITH HIGH ETCH RATE RESIST MASK - A method for etching features into an etch layer is provided. A patterned mask is formed over the etch layer, wherein the patterned mask is of a high etch rate photoresist material, wherein the patterned mask has patterned mask features. A protective layer is deposited on the patterned mask of high etch rate photoresist material by performing a cyclical deposition, wherein each cycle, comprises a depositing phase for depositing a deposition layer over the exposed surfaces, including sidewalls of the patterned mask of high etch rate photoresist material and a profile shaping phase for providing vertical sidewalls. Features are etched into the etch layer using the protective layer as a mask. The protective layer is removed. | 11-08-2012 |
20120298301 | MINIMIZATION OF MASK UNDERCUT ON DEEP ETCH - A method for forming features in a silicon layer is provided. A mask is formed with a plurality of mask openings over the silicon layer. A polymer layer is deposited over the mask by flowing a hydrogen free deposition gas comprising C | 11-29-2012 |
20120328781 | PROTECTIVE LAYER FOR IMPLANT PHOTORESIST - A method for implanting a dopant in a substrate is provided. A patterned photoresist mask is formed over the substrate, wherein the patterned photoresist mask has patterned photoresist mask features. A protective layer is deposited on the patterned photoresist mask by performing a cyclical deposition, wherein each cycle, comprises a depositing phase for depositing a deposition layer over surfaces of the patterned mask of photoresist material and a profile shaping phase for providing vertical sidewalls. A dopant is implanted into the substrate using an ion beam. The protective layer and photoresist mask are removed. | 12-27-2012 |
20130074769 | APPARATUS FOR THE DEPOSITION OF A CONFORMAL FILM ON A SUBSTRATE AND METHODS THEREFOR - A method for depositing a conformal film on a substrate in a plasma processing chamber of a plasma processing system, the substrate being disposed on a chuck, the chuck being coupled to a cooling apparatus, is disclosed. The method includes flowing a first gas mixture into the plasma processing chamber at a first pressure, wherein the first gas mixture includes at least carbon, and wherein the first gas mixture has a condensation temperature. The method also includes cooling the chuck below the condensation temperature using the cooling apparatus thereby allowing at least some of the first gas mixture to condense on a surface of the substrate. The method further includes venting the first gas mixture from the processing chamber; flowing a second gas mixture into the plasma processing chamber, the second gas mixture being different in composition from the first gas mixture; and striking a plasma to form the conformal film. | 03-28-2013 |