Harris, Cambridge
Dave Harris, Cambridge GB
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20120226240 | SYRINGE - A syringe ( | 09-06-2012 |
David Stuart Harris, Cambridge GB
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20080314384 | Dry Powder Inhalers - A dry powder inhaler comprises a main airflow path including a cyclone chamber ( | 12-25-2008 |
20090013874 | Beverage Making Device - A beverage making device comprising a brewing chamber for enclosing a pad ( | 01-15-2009 |
20090320837 | DRY POWDER INHALERS - A dry powder inhaler comprises: a cyclone chamber having a cyclone chamber outlet ( | 12-31-2009 |
20100000531 | DRY POWDER INHALERS - A dry powder inhaler comprises two parts ( | 01-07-2010 |
20100163042 | INHALATION DEVICE - The present invention relates to an inhalation-activatable device for administration of medicament in powder form to the respiratory system of a patient. | 07-01-2010 |
20100212667 | DRUG CAPSULES FOR DRY POWDER INHALERS - A method of filling a drug capsule ( | 08-26-2010 |
Euan David Harris, Cambridge GB
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20120144026 | Monitoring Connections - Apparatus for processing requests from a plurality of connected clients for data stored by a plurality of connected servers comprising a processor, memory, storage, a network interface, and a user input device is disclosed. The processor is configured to receive requests from the connected clients via the network interface, select a connected server to route each requests to, thereby defining a selected server per request, create a connection per request to its selected server using the network interface, route the requests to their selected servers using the connections, and monitor the connections whilst the selected servers service the requests, so as to create monitored connection data for each connection. The monitored connection data is stored in data structures that are referenced by a buffer, and upon creation of a data structure relating to the most recently created connection, reference to the oldest data structure in the buffer is removed. | 06-07-2012 |
Laura Harris, Cambridge GB
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20130224221 | BIOMARKERS FOR SCHIZOPHRENIA - The invention relates to a method of diagnosing or monitoring schizophrenia or other psychotic disorder. | 08-29-2013 |
Neal Harris, Cambridge GB
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20090015433 | REMOTE CONTROL FRAMEWORK - A remote control framework enables a plurality of target devices to be controlled by a plurality of remote control devices irrespective of bearer types. In a preferred embodiment any target device may also act as a control device and any control device may also act as a target device. The framework also enables any application running on any target device to be controlled by any controller device. | 01-15-2009 |
Neil Harris, Cambridge GB
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20100302184 | Touch-sensitive device - A user/machine interface comprising a panel having a surface, the panel being capable of supporting bending waves, a touch-sensitive input device associated with the surface, and means including a force transducer for providing force feedback to the input device. The force is in the form of pulses to the panel, the pulses being in the form of a modulated signal shaped as a damped sinusoid whereby a button click sensation is provided to the user's finger tip. The modulated signal may be produced by a narrow-band sine wave having a carrier frequency in the range 150 to 750 Hz and being of a duration of at least 10 ms. | 12-02-2010 |
Neil John Harris, Cambridge GB
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20150130323 | Panel For Use in Vibratory Panel Device - A panel for use in a vibratory panel device comprises a substrate, a layer of electroactive material applied to the substrate and a layer of material applied to the electroactive material forming separate active areas whereby signals may be applied to or received from respective areas of the electroactive material, wherein the layer of material forming the active areas forms at least three active areas comprising at least two primary active areas and at least one secondary active area, the secondary active area being positioned relative to the two primary active areas such that one or both of the following conditions is provided: at least one secondary active area can be driven to at least partially offset any net displacement of the panel caused by driving two of the primary active areas; and the at least one secondary active area can sense vibrations of the panel affecting both of the two primary active areas. | 05-14-2015 |
Peter William Harris, Cambridge GB
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20080288789 | Reducing information leakage between processes sharing a cache - A method of impeding leakage of cache access behavioural information of a section of a sensitive process to an untrusted process, said sensitive and untrusted processes being performed by a processor within a data processing apparatus, said data processing apparatus further comprising at least one cache operable to store information required by said processor while performing said sensitive and untrusted processes, the method comprising the steps of: prior to commencing processing of a section of said sensitive process by said processor, evicting information stored in locations of said at least one cache which may otherwise be evicted by said sensitive process loading information that may be required by said section of said sensitive process in said at least one cache; commencing processing of said section of said sensitive process by said processor; switching said processor during processing of said section of said sensitive process to said untrusted process in response to a switching request; on switching back to said section of said sensitive process from said untrusted process, evicting information stored in locations of said at least one cache which may otherwise be evicted by said sensitive process loading information that may be required by said section of said sensitive process in said at least one cache prior to recommencing processing of said section of said sensitive process. | 11-20-2008 |
20080294848 | Control data modification within a cache memory - A data processing system is provided with at least one processor | 11-27-2008 |
20090210874 | Non-native program execution across multiple execution environments - A data processing system | 08-20-2009 |
20090254986 | Method and apparatus for processing and displaying secure and non-secure data - A data processing apparatus is disclosed that comprises: at least one processor; a display for displaying data processed by said at least one processor; at least one display buffer for storing an array of display elements for subsequent output to said display, said display elements being secure display elements for displaying secure data and non-secure display elements; and a user interface; wherein said at least one processor is operable to execute at least one untrusted process and at least one secure process, said at least one secure process having access to secure data; said data processing apparatus further comprising: a secure user input for receiving a user input, said received user input not being accessible to said at least one untrusted process; and said data processing apparatus being responsive to an input received at said secure user input to transform data to be displayed on said display such that said secure display elements and said non-secure display elements are transformed differently to each other. | 10-08-2009 |
20090307770 | APPARATUS AND METHOD FOR PERFORMING INTEGRITY CHECKS ON SOFWARE - An apparatus and method are provided for performing integrity checking of software code executing on a processing unit of the apparatus. The apparatus further includes debug logic used when debugging program code executed by the processing unit, and trusted logic for performing trusted integrity checking operations on less-trusted program code executed by the processing unit. The debug logic has an interface via which the trusted logic can program one or more control registers, that interface not being accessible by the less-trusted program code. The trusted logic programs the control registers so as to cause the debug logic to be re-used to detect one or more activities of the processing logic during execution of the less-trusted program code, and the trusted integrity checking operations performed by the trusted logic are influenced by the activities detected by the debug logic. Such an approach has been found to provide an efficient and secure technique for performing run-time integrity checking of program code. | 12-10-2009 |
Reuben Harris, Cambridge GB
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20110136922 | ACTIVATION INDUCED DEAMINASE (AID) - The invention is directed to a cell comprising a nucleic acid encoding an Activation Induced Deaminase (AID) polypeptide, a fusion protein comprising an AID polypeptide, and methods of using a nucleic acid encoding an AID polypeptide. | 06-09-2011 |
20130059931 | ACTIVATION INDUCED DEAMINASE (AID) - The invention is directed to a cell comprising a nucleic acid encoding an Activation Induced Deaminase (AID) polypeptide, a fusion protein comprising an AID polypeptide, and methods of using a nucleic acid encoding an AID polypeptide. | 03-07-2013 |
Tim Harris, Cambridge GB
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20090282393 | Securing Software By Enforcing Data Flow Integrity - The majority of such software attacks exploit software vulnerabilities or flaws to write data to unintended locations. For example, control-data attacks exploit buffer overflows or other vulnerabilities to overwrite a return address in the stack, a function pointer, or some other piece of control data. Non-control-data attacks exploit similar vulnerabilities to overwrite security critical data without subverting the intended control flow in the program. We describe a method for securing software against both control-data and non-control-data attacks. A static analysis is carried out to determine data flow information for a software program. Data-flow tracking instructions are formed in order to track data flow during execution or emulation of that software. Also, checking instructions are formed to check the tracked data flow against the static analysis results and thereby identify potential attacks or errors. Optional optimisations are described to reduce the resulting additional overheads. | 11-12-2009 |
20100274937 | PROVIDING LOCK-BASED ACCESS TO NODES IN A CONCURRENT LINKED LIST - A method of providing lock-based access to nodes in a concurrent linked list includes providing a plurality of striped lock objects. Each striped lock object is configured to lock at least one of the nodes in the concurrent linked list. An index is computed based on a value stored in a first node to be accessed in the concurrent linked list. A first one of the striped lock objects is identified based on the computed index. The first striped lock object is acquired, thereby locking and providing protected access to the first node. | 10-28-2010 |
20120254139 | PROVIDING LOCK-BASED ACCESS TO NODES IN A CONCURRENT LINKED LIST - A method of providing lock-based access to nodes in a concurrent linked list includes providing a plurality of striped lock objects. Each striped lock object is configured to lock at least one of the nodes in the concurrent linked list. An index is computed based on a value stored in a first node to be accessed in the concurrent linked list. A first one of the striped lock objects is identified based on the computed index. The first striped lock object is acquired, thereby locking and providing protected access to the first node. | 10-04-2012 |
Timothy Harris, Cambridge GB
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20100070727 | Transactional Memory System - A transactional memory system is described for reporting memory access violations which occur when memory accesses made from instructions within a transaction conflict with memory accesses to the same memory location made from a non-transactional instruction. In an embodiment this is achieved by creating two mappings of a physical heap being used by a thread. The thread (which may be part of a multi-threaded process) comprises instructions for both transactional and non-transactional accesses to the physical heap which may execute concurrently as part of that thread. One of the mappings is used for non-transactional memory accesses to the physical heap. The other mapping is used for transactional memory accesses to the physical heap. Access permissions associated with the mappings are controlled to enable attempted memory access violations to be detected and reported. | 03-18-2010 |
20120151252 | Memory Management to Accommodate Non-Maskable Failures - Methods of memory management are described which can accommodate non- maskable failures in pages of physical memory. In an embodiment, when an impending non-maskable failure in a page of memory is identified, a pristine page of physical memory is used to replace the page containing the impending failure and memory mappings are updated to remap virtual pages from the failed page to the pristine page. When a new page of virtual memory is then allocated by a process, the failed page may be reused if the process identifies that it can accommodate failures and the process is provided with location information for impending failures. In another embodiment, a process may expose information on failure-tolerant regions of virtual address space such that a physical page of memory containing failures only in failure-tolerant regions may be used to store the data instead of using a pristine page. | 06-14-2012 |
20120210071 | Remote Core Operations In A Multi-Core Computer - A multi-core processor with a shared physical memory is described. In an embodiment a sending core sends a memory write request to a destination core so that the request may be acted upon by the destination core as if it originated from the destination core. In an example, a data structure is configured in the shared physical memory and mapped to be accessible to the sending and destination cores. In an example, the shared data structure is used as a message channel between the sending and destination cores to carry data using the memory write request. In an embodiment a notification mechanism is enabled using the shared physical memory in order to notify the destination core of events by updating a notification data structure. In an example, the notification mechanism triggers a notification process at the destination core to inform a receiving process of a notification. | 08-16-2012 |
Timothy L. Harris, Cambridge GB
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20090204969 | TRANSACTIONAL MEMORY WITH DYNAMIC SEPARATION - Strong semantics are provided to programs that are correctly synchronized in their use of transactions by using dynamic separation of objects that are accessed in transactions from those accessed outside transactions. At run-time, operations are performed to identify transitions between these protected and unprotected modes of access. Dynamic separation permits a range of hardware-based and software-based implementations which allow non-conflicting transactions to execute and commit in parallel. A run-time checking tool, analogous to a data-race detector, may be provided to test dynamic separation of transacted data and non-transacted data. Dynamic separation may be used in an asynchronous I/O library. | 08-13-2009 |
20090210457 | TRANSACTIONAL MEMORY WITH DYNAMIC SEPARATION - Strong semantics are provided to programs that are correctly synchronized in their use of transactions by using dynamic separation of objects that are accessed in transactions from those accessed outside transactions. At run-time, operations are performed to identify transitions between these protected and unprotected modes of access. Dynamic separation permits a range of hardware-based and software-based implementations which allow non-conflicting transactions to execute and commit in parallel. A run-time checking tool, analogous to a data-race detector, may be provided to test dynamic separation of transacted data and non-transacted data. Dynamic separation may be used in an asynchronous I/O library. | 08-20-2009 |
20100211931 | STM WITH GLOBAL VERSION OVERFLOW HANDLING - A software transactional memory system is provided with overflow handling. The system includes a global version counter with an epoch number and a version number. The system accesses the global version counter prior to and subsequent to memory accesses of transactions to validate read accesses of the transaction. The system includes mechanisms to detect global version number overflow and may allow some or all transactions to execute to completion subsequent to the global version number overflowing. The system also provides publication, privatization, and granular safety properties. | 08-19-2010 |
Timothy Lawrence Harris, Cambridge GB
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20080256073 | Transactional memory using buffered writes and enforced serialization order - Various technologies and techniques are disclosed that support buffered writes and enforced serialization order in a software transactional memory system. A buffered write process is provided that performs writes to shadow copies of objects and writes content back to the objects after validating a respective transaction during commit. When a write lock is first obtained for a particular transaction, a shadow copy is made of a particular object. Writes are performed to and reads from the shadow copy. After validating the particular transaction during commit, content is written from the shadow copy to the particular object. A transaction ordering process is provided that ensures that an order in which the transactions are committed matches an abstract serialization order of the transactions. Transactions are not allowed to commit until their ticket number matches a global number that tracks the next transaction that should commit. | 10-16-2008 |
20100191930 | TRANSACTIONAL MEMORY COMPATIBILITY MANAGEMENT - Transactional memory compatibility type attributes are associated with intermediate language code to specify, for example, that intermediate language code must be run within a transaction, or must not be run within a transaction, or may be run within a transaction. Attributes are automatically produced while generating intermediate language code from annotated source code. Default rules also generate attributes. Tools use attributes to statically or dynamically check for incompatibility between intermediate language code and a transactional memory implementation. | 07-29-2010 |