Patent application number | Description | Published |
20080206231 | Compositions and Methods for Treating Disease - The present invention discloses for the first time that the insulin receptor (IR) is a target of Herstatin, which modulates IR and IR-mediated intracellular signaling. In preferred aspects, Herstatin binds at nM concentrations to cell-surface IR, up-regulates basal IR expression by several-fold, induces the accumulation of pro-IR, and stimulates insulin activation of the ERK pathway. Moreover, these changes in insulin signaling are accompanied by alterations in IGF-IR expression, IRS-2 levels, and the serine phosphorylation state of both IRS-1 and IRS-2. Preferred aspects provide novel therapeutic methods and pharmaceutical compositions for treatment of conditions associated with altered IR expression or IR-mediated signaling, including but not limited to insulin resistance syndrome, pre-diabetic conditions, metabolic syndrome, type 1 and type 2 diabetes, cardiac disease, diabetes-associated vascular disease, atherosclerosis, hypertension, diabetes-associated lipid metabolism disorders (dyslipidemia), obesity, critical illness, neurodegenerative disorders, and combinations thereof, and cancer. | 08-28-2008 |
20090270316 | HER-2 BINDING ANTAGONISTS - There is disclosed a pharmaceutical composition for treating solid tumors that overexpress HER-2, comprising an agent selected from the group consisting of (a) an isolated polypeptide having from about 50 to 79 amino acids taken from the sequence of SEQ ID NO:1, wherein the polypeptide binds to the extracellular domain ECD of HER-2 at an affinity of at least 108, (b) an isolated and glycosylated polypeptide having from about 300 to 419 amino acids taken from the sequence of SEQ ID NO:2, wherein the C terminal 79 amino acids are present, and wherein at least three N-linked glycosylation sites are present, (c) a monoclonal antibody that binds to the ECD of HER-2, and (d) combinations thereof, with the proviso that the agent cannot be the monoclonal antibody alone, and pharmaceutically acceptable carrier. | 10-29-2009 |
20100119521 | COMPOSITIONS AND METHODS FOR TREATING CANCER BY MODULATING HER-2 AND EGF RECEPTORS - An alternative HER-2/neu product, herstatin, consists of subdomains I and II from the ectodomain of p185HER-2 and a unique 79 amino acid C-terminus encoded by intron 8. Recombinant herstatin added to cells was found to bind to and inhibit p185HER-2. The effects of ectopic expression of herstatin in combination with either p185HER-2 or with its homolog, the EGF receptor, in several cell lines was studied. Cotransfection of herstatin with HER-2 inhibited p185HER-2 levels and caused an approximate 8-fold reduction in p185 tyrosine phosphorylation. Inhibition of p185HER-2 tyrosine phosphorylation corresponded to a dramatic decline in colony formation by cells that coexpressed p185HER-2 and herstatin. Herstatin also interferred with EGF activation of the EGF receptor in cotransfected cells as demonstrated by impaired receptor tyrosine phosphorylation, reduced receptor down-regulation, and growth suppression. For both p185HER-2 and the EGF receptor, the extent of inhibition was affected by the expression levels of herstatin relative to the receptor. Herstatin is an autoinhibitor of p185HER-2 and expands its inhibitory activity to another member of the group I family of receptor tyrosine kinases, the EGF receptor. Herstatin blocked the activated Akt-mediated EGF survival signal, as well as transforming growth factor alpha (TGFα)-mediated EGF receptor activation, survival signal and proliferation signal. Purified recombinant herstatin specifically inhibited human carcinoma cells that over-express HER-2, and was effectively absorbed into the blood of intraperitoneally injected mice, where it was not proteolytically degraded and was present for between one and three hours. | 05-13-2010 |
20100267027 | HER-2 BINDING ANTAGONISTS - There is disclosed a a pharmaceutical composition for treating solid tumors that overexpress HER-2, comprising an agent selected from the group consisting of (a) an isolated polypeptide having from about 50 to 79 amino acids taken from the sequence of SEQ ID NO:1, wherein the polypeptide binds to the extracellular domain ECD of HER-2 with an affinity binding constant of at least 10 | 10-21-2010 |
20120045755 | HER-2 BINDING ANTAGONISTS - There is disclosed a pharmaceutical composition for treating solid tumors that overexpress HER-2, comprising an agent selected from the group consisting of (a) an isolated polypeptide having from about 50 to 79 amino acids taken from the sequence of SEQ ID NO. 1 or SEQ ID NO:12, wherein the polypeptide binds to the extracellular domain ECD of HER-2 at an affinity of at least 10 | 02-23-2012 |
20120088255 | HER-2 BINDING ANTAGONISTS - There is disclosed a pharmaceutical composition for treating solid tumors that overexpress HER-2, comprising an agent selected from the group consisting of (a) an isolated polypeptide having from about 50 to 79 amino acids taken from the sequence of SEQ ID NO:1, wherein the polypeptide binds to the extracellular domain ECD of HER-2 at an affinity of at least 10 | 04-12-2012 |
Patent application number | Description | Published |
20090147603 | MEMORY WITH LOW POWER MODE FOR WRITE - The present invention describes circuitry and a method of providing a low power WRITE mode of operation for an integrated circuit comprising an SRAM memory to provide a reduced IDDQ relative to the IDDQ of a full active mode. In one aspect, the circuitry includes an SRAM memory array, mode control circuitry coupled to the array and configured to alter a supply voltage level to the SRAM array based on a mode of operation. The circuitry also includes control inputs coupled to the mode control circuitry for selecting one of the low power write mode, the full active mode, and optionally a retention mode of operation. The mode control circuitry is configured to receive the control inputs to select one of the three modes of operation, and to alter one or more supply voltage levels to the array, for example, the Vss supply voltage using a Vss supply circuit and the Vdd supply voltage using a Vdd supply circuit, based on the selected mode of operation. The mode control circuitry may also comprise a bitline precharge circuit configured to alter a bitline precharge voltage. | 06-11-2009 |
20090316500 | Memory Cell Employing Reduced Voltage - A memory array is provided having a memory cell coupled to a read word line and a write word line of the memory array and peripheral circuits for reading and writing to the memory cell. The memory cell comprises a storage element for storing a logical state of the memory cell powered at a reduced voltage during at least one functional operation and a write access circuit configured to connect the storage element to at least a first write bit line in the memory array in response to a write signal on the write word line for writing the logical state to the memory cell. The memory cell further comprises a read access circuit including an input node connected to the storage element and an output node connected to a read bit line of the memory array. The read access circuit is enabled and configured to read the logic state of the storage element in response to a read signal on the read word line. The reduced voltage is a voltage that is reduced relative to a peripheral operating voltage of at least one peripheral circuit associated with reading and/or writing of the memory cell. | 12-24-2009 |
20110069565 | MEMORY CELL EMPLOYING REDUCED VOLTAGE - A memory array is provided having a memory cell coupled to a read word line and a write word line of the memory array and peripheral circuits for reading and writing to the memory cell. The memory cell comprises a storage element for storing a logical state of the memory cell powered at a reduced voltage during at least one functional operation and a write access circuit configured to connect the storage element to at least a first write bit line in the memory array in response to a write signal on the write word line for writing the logical state to the memory cell. The memory cell further comprises a read access circuit including an input node connected to the storage element and an output node connected to a read bit line of the memory array. The read access circuit is enabled and configured to read the logic state of the storage element in response to a read signal on the read word line. The reduced voltage is a voltage that is reduced relative to a peripheral operating voltage of at least one peripheral circuit associated with reading and/or writing of the memory cell. | 03-24-2011 |
20110261632 | Combined Write Assist and Retain-Till-Accessed Memory Array Bias - Bias circuitry for a static random-access memory (SRAM) with a retain-till-accessed (RTA) mode and with write assist bias in a normal operating mode. The memory is constructed of multiple memory array blocks of SRAM cells. Bias devices are associated with each memory array block, and associated with one or more columns. Each bias device includes a diode-connected transistor in parallel with a shorting transistor, between a power supply voltage and a power supply bias node for cells in its column or columns. The shorting transistor receives control signals from control logic so that the diode-connected transistor for each column is shorted during read cycles, and in write cycles in which its columns are not selected; in write cycles in which its columns are selected, the shorting transistor in the bias device is turned off, so that a reduced power supply voltage is applied to the selected column. The shorting transistors for all columns in the block are turned off in the RTA mode. An additional transistor in series with the diode-connected transistor may be included, to enable a floating power supply bias mode. | 10-27-2011 |
20120168837 | Ferroelectric Memory Electrical Contact - A ferroelectric apparatus includes a circuit having a first capacitor electrically coupled to a plate line via a top terminal connection of the first ferroelectric capacitor and to a storage node via a bottom terminal connection of the first ferroelectric capacitor. The circuit also includes a second ferroelectric capacitor electrically coupled to a second plate line via a second bottom terminal connection of the second ferroelectric capacitor and to the storage node via a second top terminal connection of the second ferroelectric capacitor. | 07-05-2012 |
20120170348 | Ferroelectric Memory Write-Back - A self-timed sense amplifier read buffer pulls down a pre-charged high global bit line, which then feeds data into a tri state write back buffer that is connected directly to the bit line. The bit line provides charge to a ferroelectric capacitor to write a logical “one” or “zero” while by-passing an isolator switch disposed between the sense amplifier and the ferroelectric capacitor. Because the sense amplifier uses grounded bit line sensing, the read buffer will not start pulling down the global bit line until after the sense amplifier signal amplification, which makes the timing of the control signal for this read buffer non-critical. The write-back buffer enable timing is also self-timed off of the sense amplifier. Therefore, the read data write-back to a ferroelectric memory cell is locally controlled and begins quickly after reading data from the ferroelectric memory cell, thereby allowing a quick cycle time. | 07-05-2012 |
20120170349 | Ferroelectric Memory with Shunt Device - A ferroelectric memory device includes a shunt switch configured to short both sides of the ferroelectric capacitor of the ferroelectric memory device. The shunt switch is configured therefore to remove excess charge from around the ferroelectric capacitor prior to or after reading data from the ferroelectric capacitor. By one approach, the shunt switch is connected to operate in reaction to signals from the same line that controls accessing the ferroelectric capacitor. So configured, the high performance cycle time of the ferroelectric memory device is reduced by eliminating delays used to otherwise drain excess charge from around the ferroelectric capacitor, for example by applying a precharge voltage. The shunt switch also improves reliability of the ferroelectric memory device by ensuring that excess charge does not affect the reading of the ferroelectric capacitor during a read cycle. | 07-05-2012 |
20120170350 | METHOD AND APPARATUS PERTAINING TO A FERRO-MAGNETIC RANDOM ACCESS MEMORY - An FRAM device can comprise a sense amplifier, at least a first bitcell, a first control line, and a second control line. The first bitcell can have a bit line that connects to the sense amplifier via a first isolator and a complimentary bit line that connects to the sense amplifier via a second isolator that is different from the first isolator. The first control line can connect to and control the aforementioned first isolator. And the second control line can connect to and control the second isolator such that the second isolator is independently controlled with respect to the first isolator to facilitate testing the device. | 07-05-2012 |
20120170351 | METHOD AND APPARATUS PERTAINING TO A FERRO-MAGNETIC RANDOM ACCESS MEMORY - An FRAM device can comprise a sense amplifier and at least a first bitcell. The first bitcell can have a bit line and a complimentary bit line that connects to the sense amplifier. A first precharge circuit responds to a first control signal during a test mode of operation to precharge the bit line with respect to a first voltage while a second precharge circuit responds to a second control signal (that is different from the first control signal) during the test mode of operation to precharge the complimentary bit line with respect to a test voltage that is different than the first voltage (such as, but not limited to, a test voltage of choice such as a voltage that is greater than ground but less than the first voltage). | 07-05-2012 |
20130003471 | MEMORY CELL EMPLOYING REDUCED VOLTAGE - A memory array has a memory cell that comprises a storage element storing a logical state at a reduced voltage during at least one functional operation and a write access circuit configured to connect the storage element to at least a first write bit line in response to a write signal on the write word line for writing the logical state to the memory cell. The memory cell further comprises a read access circuit including an input node connected to the storage element and an output node connected to a read bit line of the memory array. The read access circuit is enabled and configured to read the logic state of the storage element in response to a read signal on the read word line. The reduced voltage is reduced relative to an operating voltage of at least one peripheral circuit associated with reading and/or writing of the memory cell. | 01-03-2013 |
20130128680 | READ ASSIST CIRCUIT FOR AN SRAM - A memory circuit includes a bit cell that receives a word line, complementary bit lines and an array supply voltage; a word line driver coupled to the word line, the word line driver receiving one of the array supply voltage and a periphery supply voltage; and a word line suppression circuit coupled to the word line. The word line suppression circuit includes a diode and a switch coupled in series. The switch is responsive to the array supply voltage. The word line suppression circuit limits a word line voltage to a value lower than the array supply voltage such that the static noise margin (SNM) of the bit cell is increased. | 05-23-2013 |
Patent application number | Description | Published |
20140140121 | High-Performance Scalable Read-Only-Memory Cell - A two-bit read-only-memory (ROM) cell and method of sensing its data state. Each ROM cell in an array includes a single n-channel metal-oxide-semiconductor (MOS) transistor with a source biased to a reference voltage, and its drain connected by a contact or via to one or none of first, second, and third bit lines associated with its column in the array. Each row in the array is associated with a word line serving as the transistor gates for the cells in that row. In response to a column address, a column select circuit selects one pair of the three bit lines to be applied to a sense line in wired-NOR fashion for sensing. | 05-22-2014 |
20140241083 | READ ASSIST CIRCUIT FOR AN SRAM TECHNICAL FIELD - A memory circuit includes a bit cell that receives a word line, complementary bit lines and an array supply voltage; a word line driver coupled to the word line, the word line driver receiving one of the array supply voltage and a periphery supply voltage; and a word line suppression circuit coupled to the word line. The word line suppression circuit includes a diode and a switch coupled in series. The switch is responsive to the array supply voltage. The word line suppression circuit limits a word line voltage to a value lower than the array supply voltage such that the static noise margin (SNM) of the bit cell is increased. | 08-28-2014 |
20140241089 | READ ASSIST CIRCUIT FOR AN SRAM TECHNICAL FIELD - A memory circuit includes a bit cell that receives a word line, complementary bit lines and an array supply voltage; a word line driver coupled to the word line, the word line driver receiving one of the array supply voltage and a periphery supply voltage; and a word line suppression circuit coupled to the word line. The word line suppression circuit includes a diode and a switch coupled in series. The switch is responsive to the array supply voltage. The word line suppression circuit limits a word line voltage to a value lower than the array supply voltage such that the static noise margin (SNM) of the bit cell is increased. | 08-28-2014 |