Patent application number | Description | Published |
20080261128 | Methods and structures for protecting one area while processing another area on a chip - Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided which exhibit an interface of a chemical reaction, grain or material type which can be exploited to enhance either or both types of protection. Structures of such masks include TERA material which can be converted or hydrated and selectively etched using a mixture of hydrogen fluoride and a hygroscopic acid or organic solvent, and two layer structures of similar or dissimilar materials. | 10-23-2008 |
20080286545 | MASK HAVING IMPLANT STOPPING LAYER - Methods of forming a mask for implanting a substrate and implanting using an implant stopping layer with a photoresist provide lower aspect ratio masks that cause minimal damage to trench isolations in the substrate during removal of the mask. In one embodiment, a method of forming a mask includes: depositing an implant stopping layer over the substrate; depositing a photoresist over the implant stopping layer, the implant stopping layer having a density greater than the photoresist; forming a pattern in the photoresist by removing a portion of the photoresist to expose the implant stopping layer; and transferring the pattern into the implant stopping layer by etching to form the mask. The implant stopping layer may include: hydrogenated germanium carbide, nitrogenated germanium carbide, fluorinated germanium carbide, and/or amorphous germanium carbon hydride (GeHX), where X includes carbon. The methods/mask reduce scattering during implanting because the mask has higher density than conventional masks. | 11-20-2008 |
20090004869 | MASK FORMING AND IMPLANTING METHODS USING IMPLANT STOPPING LAYER - Methods of forming a mask for implanting a substrate and implanting using an implant stopping layer with a photoresist provide lower aspect ratio masks that cause minimal damage to trench isolations in the substrate during removal of the mask. In one embodiment, a method of forming a mask includes: depositing an implant stopping layer over the substrate; depositing a photoresist over the implant stopping layer, the implant stopping layer having a density greater than the photoresist; forming a pattern in the photoresist by removing a portion of the photoresist to expose the implant stopping layer; and transferring the pattern into the implant stopping layer by etching to form the mask. The implant stopping layer may include: hydrogenated germanium carbide, nitrogenated germanium carbide, fluorinated germanium carbide, and/or amorphous germanium carbon hydride (GeHX), where X includes carbon. The methods/mask reduce scattering during implanting because the mask has higher density than conventional masks. | 01-01-2009 |
20120235119 | Method to Improve Nucleation of Materials on Graphene and Carbon Nanotubes - Techniques for forming a thin coating of a material on a carbon-based material are provided. In one aspect, a method for forming a thin coating on a surface of a carbon-based material is provided. The method includes the following steps. An ultra thin silicon nucleation layer is deposited to a thickness of from about two angstroms to about 10 angstroms on at least a portion of the surface of the carbon-based material to facilitate nucleation of the coating on the surface of the carbon-based material. The thin coating is deposited to a thickness of from about two angstroms to about 100 angstroms over the ultra thin silicon layer to form the thin coating on the surface of the carbon-based material. | 09-20-2012 |
Patent application number | Description | Published |
20080311508 | PROCESS OF MAKING A SEMICONDUCTOR DEVICE USING MULTIPLE ANTIREFLECTIVE MATERIALS - A lithographic structure consisting essentially of: an organic antireflective material disposed on a substrate; a vapor-deposited RCHX material, wherein R is one or more elements selected from the group consisting of Si, Ge, B, Sn, Fe and Ti, and wherein X is not present or is one or more elements selected from the group consisting of O, N, S and F; and a photoresist material disposed on the RCHX material. The invention is also directed to methods of making the lithographic structure, and using the structure to pattern a substrate. | 12-18-2008 |
20090061355 | PROCESS OF MAKING A LITHOGRAPHIC STRUCTURE USING ANTIREFLECTIVE MATERIALS - A lithographic structure comprising: an organic antireflective material disposed on a substrate; and a silicon antireflective material disposed on the organic antireflective material. The silicon antireflective material comprises a crosslinked polymer with a SiO | 03-05-2009 |
20100038715 | THIN BODY SILICON-ON-INSULATOR TRANSISTOR WITH BORDERLESS SELF-ALIGNED CONTACTS - A method for fabricating a thin-silicon-on-insulator transistor with borderless self-aligned contacts is disclosed. A gate stack is formed on a silicon layer that is above a buried oxide layer. The gate stack includes a gate oxide layer on the silicon layer and a gate electrode layer on the gate oxide layer. A hard mask on top of the gate stack is formed. An off-set spacer is formed surrounding the gate stack. A raised source/drain region is epitaxially formed adjacent to the off-set spacer. The raised source/drain region is grown slightly about a height of the gate stack including the hard mask. The raised source/drain region forms borderless self-aligned contact. | 02-18-2010 |
20100038723 | SELF-ALIGNED BORDERLESS CONTACTS FOR HIGH DENSITY ELECTRONIC AND MEMORY DEVICE INTEGRATION - A method for fabricating a transistor having self-aligned borderless electrical contacts is disclosed. A gate stack is formed on a silicon region. An off-set spacer is formed surrounding the gate stack. A sacrificial layer that includes a carbon-based film is deposited overlying the silicon region, the gate stack, and the off-set spacer. A pattern is defined in the sacrificial layer to define a contact area for the electrical contact. The pattern exposes at least a portion of the gate stack and source/drain. A dielectric layer is deposited overlying the sacrificial layer that has been patterned and the portion of the gate stack that has been exposed. The sacrificial layer that has been patterned is selectively removed to define the contact area at the height that has been defined. The contact area for the height that has been defined is metalized to form the electrical contact. | 02-18-2010 |
20110048930 | SELECTIVE NANOTUBE GROWTH INSIDE VIAS USING AN ION BEAM - A method of selectively growing one or more carbon nano-tubes includes forming an insulating layer on a substrate, the insulating layer having a top surface; forming a via in the insulating layer; forming an active metal layer over the insulating layer, including sidewall and bottom surfaces of the via; and removing the active metal layer at portions of the top surface with an ion beam to enable the selective growth of one or more carbon nano-tubes inside the via. | 03-03-2011 |
20110254138 | LOW-TEMPERATURE ABSORBER FILM AND METHOD OF FABRICATION - An improved low-temperature absorber, amorphous carbonitride (ACN) with an extinction coefficient (k) of greater than 0.15, and an emissivity of greater than 0.8 is disclosed. The ACN film can also be characterized as having a minimum of hydrocarbon content as observed by FTIR. The ACN film can be used as an effective absorbing layer that absorbs a wide range of electromagnetic radiation from different sources including lasers or flash lamps. A method of forming such an ACN film at a deposition temperature of less than, or equal to, 450° C. is also provided. | 10-20-2011 |
20120217590 | Filling Narrow Openings Using Ion Beam Etch - Generally, the subject matter disclosed herein relates to modern sophisticated semiconductor devices and methods for forming the same, wherein a multilayer metal fill may be used to fill narrow openings formed in an interlayer dielectric layer. One illustrative method disclosed herein includes forming an opening in a dielectric material layer of a semiconductor device formed above a semiconductor substrate, the opening having sidewalls and a bottom surface. The method also includes forming a first layer of first fill material above the semiconductor device by forming the first layer inside the opening and at least above the sidewalls and the bottom surface of the opening. Furthermore, the method includes performing a first angled etching process to at least partially remove the first layer of first fill material from above the semiconductor device by at least partially removing a first portion of the first layer proximate an inlet of the opening without removing a second portion of the first layer proximate the bottom of said opening, and forming a second layer of second fill material above the semiconductor device by forming the second layer inside the opening and above the first layer. | 08-30-2012 |
20120295417 | SELECTIVE EPITAXIAL GROWTH BY INCUBATION TIME ENGINEERING - A method of controlling the nucleation rate (i.e., incubation time) of dissimilar materials in an epitaxial growth chamber that can favor high growth rates and can be compatible with low temperature growth is provided. The nucleation rate of dissimilar materials is controlled in an epitaxial growth chamber by altering the nucleation rate for the growth of a given material film, relative to single crystal growth of the same material film, by choosing an appropriate masking material with a given native nucleation characteristic, or by modifying the surface of the masking layer to achieve the appropriate nucleation characteristic. Alternatively, nucleation rate control can be achieved by modifying the surface of selected areas of a semiconductor substrate relative to other areas in which an epitaxial semiconductor material will be subsequently formed. | 11-22-2012 |
20120299101 | THIN BODY SILICON-ON-INSULATOR TRANSISTOR WITH BORDERLESS SELF-ALIGNED CONTACTS - A thin-silicon-on-insulator transistor with borderless self-aligned contacts includes a buried oxide layer above a substrate. A silicon layer overlays the buried oxide layer. A gate stack is on the silicon layer. The gate stack includes a gate oxide layer on the silicon layer and a gate electrode on the gate oxide layer. An off-set spacer surrounds the gate stack. Raised source/drain regions each have a first part overlying a portion of the silicon layer, a second part adjacent to off-set spacer, and a third part extending about a top portion of the gate stack. | 11-29-2012 |
20130017486 | PROCESS OF MAKING A LITHOGRAPHIC STRUCTURE USING ANTIREFLECTIVE MATERIALS - A lithographic structure comprising: an organic antireflective material disposed on a substrate, and a silicon antireflective material disposed on the organic antireflective material. The silicon antireflective material comprises a crosslinked polymer with a SiO | 01-17-2013 |
Patent application number | Description | Published |
20080284580 | VIDEO ALARM VERIFICATION - A method for monitoring an alarm zone within a perimeter, border and/or building includes capturing video image data of an alarm event detected in the alarm zone, and automatically establishing a cell phone session with an end-user to verify a true or false nature of the detected alarm. The end-user may use the cell phone display to review the video during the cell phone session, and may use the cell phone's key for the verifying. The novel monitoring method with end-user alarm event verification avoids false alarms being raised where the nature of the detected alarm event is false, and the verifying occurs before a false alarm is raised/communicated. | 11-20-2008 |
20090072961 | METHOD FOR DYNAMICALLY ADJUSTING THE SENSITIVITY OF A SENSOR IN A SECURITY SYSTEM - A method for dynamically changing a control panel response to a transmission from one or more multi-output sensors. The transmission includes a state of a plurality of sensitivity levels for each multi-output sensor indicating multiple outputs. The method comprising the steps of receiving a transmission from the multi-output sensor, determining a source of the transmission, determining a state of each of the sensitivity levels determining if at least one selection criterion is set for selecting one of the plurality of sensitivity levels included in the transmission based upon the determined source. One of the sensitivity levels is selected based upon the determination and an alarm is generated based upon said selected sensitivity level. If more than one selection criterion is set, a priority for the selection criterion is determined. | 03-19-2009 |
20120318879 | APPARATUS AND METHOD FOR SELF-TEST OF THERMOSTAT - An environmental control system includes at least one of a security monitoring system, or a building automation control system. A thermostat coupled to the at least one system, where the thermostat provides feedback as to output signals therefrom to evaluate functioning of the thermostat. The output signals would be coupled to a heating, ventilating and air conditioning system. | 12-20-2012 |
20150107816 | APPARATUS AND METHOD FOR SELF-TEST OF THERMOSTAT - An environmental control system includes at least one of a security monitoring system, or a building automation control system. A thermostat coupled to the at least one system, where the thermostat provides feedback as to output signals therefrom to evaluate functioning of the thermostat. The output signals would be coupled to a heating, ventilating and air conditioning system. | 04-23-2015 |