Patent application number | Description | Published |
20080310227 | SEMICONDUCTOR MEMORY DEVICE AND RELATED PROGRAMMING METHOD - A NOR flash memory device and related programming method are disclosed. The programming method includes programming data in a memory cell and, during a program verification operation, controlling the supply of current from a sense amplifier to the memory cell in relation to the value of the programmed data. Wherein a program verification operation is indicated, current is provided from the sense amplifier to the memory cell. Where a program verification operation is not indicated, current is cut off from the sense amplifier. | 12-18-2008 |
20090085680 | OSCILLATOR GENERATING NORMAL CLOCK SIGNAL - Disclosed is an oscillator including a reference voltage generator generating a reference voltage, and a logic combination circuit generating complementary first and second internal clock signals in response to the reference voltage and complementary first and second output voltages. One of the first and second output voltages—the one going high—is provided to the logic combination circuit before the other one of the first and second output voltages—the one going low. | 04-02-2009 |
20090273983 | NONVOLATILE MEMORY DEVICE AND PROGRAMMING METHOD - Disclosed is a programming method for a nonvolatile memory device. The method includes; charging word-line signal lines to a pass voltage during a pass voltage charge operation, simultaneously executing an initial precharge operation for strings including program-inhibited cells during the pass voltage charge operation, and applying the pass voltage to word lines from the word-line signal lines in response to a block-selection enabling signal | 11-05-2009 |
20100001710 | REFERENCE VOLTAGE GENERATING CIRCUIT - A reference voltage generating circuit provides a stabilized reference voltage and includes; a clock generator providing a clock signal, a high voltage generator providing a pumping voltage in response to the clock signal, a ripple eradicator providing a static voltage by removing voltage ripple from the pumping voltage, and a reference voltage generator providing the reference voltage. | 01-07-2010 |
20110058427 | FLASH MEMORY DEVICE CONFIGURED TO REDUCE COMMON SOURCE LINE NOISE, METHODS OF OPERATING SAME, AND MEMORY SYSTEM INCORPORATING SAME - A flash memory device comprises memory cells connected between a bit line and a common source line, word lines connected to the memory cells, a common source line feedback circuit connected to a common source line (CSL) to detect the voltage level of the common source line, and a CSL feedback control logic configured to control a voltage level of a selected word line or a selected bit line to be compensated to a substantially constant value during a sensing operation of the memory cells based on the detected voltage level of the CSL. | 03-10-2011 |
20110080791 | NONVOLATILE MEMORY DEVICE AND RELATED METHOD OF OPERATION - A method of programming a nonvolatile memory device comprises programming memory cells by performing a plurality of program loops with bitline precharging inactivated during program verification operations of some of the program loops, and with bitline precharging activated during program verification operations of some of the program loops. | 04-07-2011 |
Patent application number | Description | Published |
20110194346 | FLASH MEMORY DEVICE USING ADAPTIVE PROGRAM VERIFICATION SCHEME AND RELATED METHOD OF OPERATION - A method of programming a flash memory device comprises programming selected memory cells, performing a verification operation to determine whether the selected memory cells have reached a target program state, and determining a start point of the verification operation based on a programming characteristic associated with a detection of a pass bit during programming of an initial program state. | 08-11-2011 |
20110205817 | METHOD AND APPARATUS FOR MANAGING OPEN BLOCKS IN NONVOLATILE MEMORY DEVICE - A memory system comprises a multi-bit memory device and a memory controller that controls the multi-bit memory device. The memory system determines whether a requested program operation is a random program operation or a sequential program operation. Where the requested program operation is a random program operation, the memory controller controls the multi-bit memory device to perform operations according to a fine program close policy or a fine program open policy. | 08-25-2011 |
20110280070 | NONVOLATILE MEMORY DEVICE, SYSTEM COMPRISING NONVOLATILE MEMORY DEVICE, AND READ OPERATION OF NONVOLATILE MEMORY DEVICE - A nonvolatile memory device comprises a memory cell array, a page buffer, and a control circuit. The memory cell array comprises multi-level cells configured to store hard decision data bits. The page buffer is configured to sense whether each of the multi-level cells assumes an on-cell state or an off-cell state in response to a first read voltage applied to a selected wordline during a first read operation, to set first soft decision data bits according to the first read operation, and to sense one or more hard decision data bits from each of the multi-level cells in response to a second read voltage applied to the selected wordline in a second read operation. The control circuit is configured to control the first read operation and the second read operation to be performed in succession. | 11-17-2011 |
20110305091 | SEMICONDUCTOR MEMORY DEVICE AND RELATED METHODS FOR PERFORMING READ AND VERIFICATION OPERATIONS - A semiconductor memory device comprises a memory cell array configured to store data, a sensing unit configured to perform a read operation the memory cell array by sensing a bitline in a plurality of reading steps in response to a single read command, and a sensing time controller configured to generate a control signal to control a variable reading time for each reading step of the sensing unit. | 12-15-2011 |
20120134213 | METHOD COMPENSATION OPERATING VOLTAGE, FLASH MEMORY DEVICE, AND DATA STORAGE DEVICE - Disclosed is a method generating a compensated operating voltage, such as a read voltage, in a non-volatile memory device, and a related non-volatile memory device. The operating voltage is compensated in response to one or more memory cell conditions such as temperature variation, programmed data state or physical location of a selected memory cell, page information for selected memory cell, or the location of a selected word line. | 05-31-2012 |
20120221880 | MEMORY SYSTEM AND METHOD OF CONTROLLING SAME - A memory system comprises a controller that generates a processor clock, and a plurality of memory devices each comprising an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times. | 08-30-2012 |
20130124783 | METHOD OF OPERATING NONVOLATILE MEMORY DEVICES STORING RANDOMIZED DATA GENERATED BY COPYBACK OPERATION - In an operating method for a nonvolatile memory device, first random data is sensed from a source area of the memory cell array, the first random data having been generated using first random sequence data. While sensing the first random data, third random sequence data is loaded to a page buffer circuit, the third random sequence data being generated from the first random sequence data and second random sequence data. A logical operation is performed on the sensed first random data and the third random sequence data in the page buffer circuit to generate second random data, and the second random data is programmed to a target area in the memory cell array different from the source area. | 05-16-2013 |
20130208541 | FLASH MEMORY DEVICE USING ADAPTIVE PROGRAM VERIFICATION SCHEME AND RELATED METHOD OF OPERATION - A method of programming a flash memory device comprises programming selected memory cells, performing a verification operation to determine whether the selected memory cells have reached a target program state, and determining a start point of the verification operation based on a programming characteristic associated with a detection of a pass bit during programming of an initial program state. | 08-15-2013 |
20140043904 | MEMORY SYSTEM COMPRISING NONVOLATILE MEMORY DEVICE AND RELATED METHOD OF OPERATION - A memory system performs a first sensing operation to sense whether multi-level cells assume an on-cell state or an off-cell state in response to a first read voltage applied to a selected word line. It then supplies a pre-charge voltage to bit lines corresponding to multi-level cells that have been sensed as assuming the off-cell state in response to the first read voltage, and it performs a second sensing operation with the supplied pre-charge voltage to sense whether each of the multi-level cells that have been sensed as assuming the off-cell state assumes an on-cell state or an off-cell state in response to a second read voltage applied to the selected word line. | 02-13-2014 |
20140129902 | APPARATUS AND METHOD OF OPERATING MEMORY DEVICE - A memory device useable with a memory system includes a voltage generator to a plurality of first candidate voltages and a plurality of second candidate voltages, and an X decoder to sequentially apply each of the plurality of first candidate voltages and each of the plurality of second candidate voltages to one or more cells of a memory cell array, and then to apply one of the plurality of first candidate voltages and one of the plurality of second candidate voltages as a first read voltage and a second voltage, respectively, to read data from the cells of the memory cell array according to a characteristic of the cells of the memory cell array. | 05-08-2014 |
20140129903 | METHOD OF OPERATING MEMORY DEVICE - A method of operating a memory device includes changing a first read voltage, which determines a first voltage state or a second voltage state, to a voltage within a first range and determining the voltage as a first select read voltage, and changing a second read voltage, which is used to determine whether the data stored in the memory cells is a third different voltage state or a fourth different voltage state, to a voltage within a second different range and determining the voltage as a second select read voltage. The first voltage state overlaps the second voltage. The third voltage state overlaps the fourth voltage state. A difference between a voltage at an intersection of the third and fourth voltage states and the second read voltage is greater than a difference between a voltage at an intersection of the first and second voltage states and the first read voltage. | 05-08-2014 |
20140153338 | MEMORY SYSTEM AND METHOD OF OPERATING MEMORY SYSTEM USING SOFT READ VOLTAGES - A method is provided for operating a memory system. The method includes reading nonvolatile memory cells using a first soft read voltage, a voltage level difference between the first soft read voltage and a first hard read voltage being indicated by a first voltage value; and reading the nonvolatile memory cells using a second soft read voltage paired with the first soft read voltage, a voltage level difference between the second soft read voltage and the first hard read voltage being indicated by a second voltage value. The second voltage value is different than the first voltage value. Also, a difference between the first voltage value and the second voltage value corresponds to the degree of asymmetry of adjacent threshold voltage distributions among multiple threshold voltage distributions set for the nonvolatile memory cells of the memory system. | 06-05-2014 |
20140160831 | Nonvolatile Memory Devices Using Variable Resistive Elements and Related Driving Methods Thereof - Driving methods of a nonvolatile memory device are provided. The driving method includes providing a start pulse adjusted based on a previous write operation to a resistive memory cell to write data, verifying whether the data has accurately been written using the start pulse, and executing a write operation on the resistive memory cell by an incremental one-way write method or a decremental one-way write method according to the verify result. Related nonvolatile memory devices are also provided. | 06-12-2014 |
20140169068 | NONVOLATILE MEMORY DEVICE HAVING VARIABLE RESISTIVE ELEMENTS AND METHOD OF DRIVING THE SAME - A method is provided for driving a nonvolatile memory device. The method includes selecting first write drivers based on a predetermined current, performing a first program operation on resistive memory cells corresponding to the first write drivers, verifying whether the resistive memory cells have passed or failed in the first program operation and sorting information regarding failed bit memory cells that failed in the first program operation, selecting second write drivers based on the sorted failed bit memory cell information, and performing a second program operation on resistive memory cells corresponding to the second write drivers. | 06-19-2014 |
20140169101 | METHOD COMPENSATION OPERATING VOLTAGE, FLASH MEMORY DEVICE, AND DATA STORAGE DEVICE - Disclosed is a method generating a compensated operating voltage, such as a read voltage, in a non-volatile memory device, and a related non-volatile memory device. The operating voltage is compensated in response to one or more memory cell conditions such as temperature variation, programmed data state or physical location of a selected memory cell, page information for selected memory cell, or the location of a selected word line. | 06-19-2014 |
20140204650 | NONVOLATILE RESISTIVE MEMORY DEVICE AND WRITING METHOD - A writing method for a resistive nonvolatile memory device includes writing data to a resistive nonvolatile memory cell using an up/down write pulse signal when the data is first data type, and writing data to the resistive nonvolatile memory cell using only one of an up write pulse signal and a down write pulse signal when the data is second data type. | 07-24-2014 |
20150262700 | FLASH MEMORY DEVICE USING ADAPTIVE PROGRAM VERIFICATION SCHEME AND RELATED METHOD OF OPERATION - A method of programming a flash memory device comprises programming selected memory cells, performing a verification operation to determine whether the selected memory cells have reached a target program state, and determining a start point of the verification operation based on a programming characteristic associated with a detection of a pass bit during programming of an initial program state. | 09-17-2015 |
20160116939 | MEMORY SYSTEM AND METHOD OF CONTROLLING SAME - A memory system including a controller that generates a processor clock, and a plurality of memory devices each including an internal clock generator that generates an internal clock in synchronization with the processor clock, and a memory that performs a peak current generation operation in synchronization with the internal clock, wherein at least two of the memory devices generate their respective internal clocks at different times such that the corresponding peak current generation operations are performed at different times. | 04-28-2016 |