Patent application number | Description | Published |
20080309537 | PSEUDO-DIFFERENTIAL CLASS-AB DIGITAL-TO-ANALOG CONVERTER WITH CODE DEPENDENT DC CURRENT - A digital-to-analog converter, RF transmit channel and method, for converting a digital signal of N bits having a set M of most significant bits and a set L of least significant bits to an analog signal, are disclosed. The digital signal defines a set of coded values which are converted to analog values and modulated on to a RF signal. The digital-to-analog converter includes a plurality of switches and an output stage, for providing at least a first differential output signal and a second differential output signal. The output stage modifies currents received from the plurality of switches, such that the value of the average output current of the first and second differential outputs signals is steered to a relatively low current value at the mid-point of the coded values. | 12-18-2008 |
20090074106 | MULTI-MODE AND MULTI-BAND TRANSMITTERS FOR WIRELESS COMMUNICATION - Transmitters supporting multiple modulation modes and/or multiple frequency bands are described. A transmitter may perform large signal polar modulation, small signal polar modulation, and/or quadrature modulation, which may support different modulation schemes and systems. Circuit blocks may be shared by the different modulation modes to reduce cost and power. For example, a single modulator and a single power amplifier may be used for small signal polar modulation and quadrature modulation. The transmitter may apply pre-distortion to improve performance, to allow a power amplifier to support multiple frequency bands, to allow the power amplifier to operate at higher output power levels, etc. Envelope and phase distortions due to non-linearity of the power amplifier may be characterized for different input levels and different bands and stored at the transmitter. Thereafter, envelope and phase signals may be pre-distorted based on the stored characterizations to compensate for non-linearity of the power amplifier. | 03-19-2009 |
20090075689 | MIXER WITH HIGH OUTPUT POWER ACCURACY AND LOW LOCAL OSCILLATOR LEAKAGE - A circuit receives a first signal (for example, a baseband signal) and mixes it with a local oscillator (LO) signal, and outputs a second signal (for example, an RFOUT signal). The circuit includes multiple identical Mixer and Frequency Divider Pair (MFDP) circuits. Each MFDP can be enabled separately. Each MFDP includes a mixer and a frequency divider that provides the mixer with a local version of the LO signal. The MFDP outputs are coupled together so that the output power of the second signal (RFOUT) is the combined output powers of the various MFDPs. By controlling the number of enabled MFDPs, the output power of the second signal is controlled. Because the MFDPs all have identical layouts, accuracy of output power step size is improved. Because LO signal power within the circuit automatically changes in proportion to the number of enabled MFDPs, local oscillator leakage problems are avoided. | 03-19-2009 |
20090111409 | DYNAMIC BIASING OF A VCO IN A PHASE-LOCKED LOOP - A local oscillator includes a phase-locked loop. The phase-locked loop includes voltage controlled oscillator (VCO) and a novel VCO control circuit. The VCO control circuit may be programmable and configurable. In one example, an instruction is received onto the VCO control circuit to change the power state of the VCO. The instruction is issued by other circuitry in response to a detected change in RF channel conditions (for example, a change in a signal-to-noise determination) in a cellular telephone. In response, the VCO control circuit outputs control signals that gradually widen the loop bandwidth of the PLL, then gradually change the VCO bias current to change the VCO power state, and then narrow the loop bandwidth of the PLL back to its original bandwidth. The entire process of widening the PLL bandwidth, changing the VCO power state, and narrowing the PLL bandwidth occurs while the PLL remains locked. | 04-30-2009 |
20090141845 | DIGITAL PHASE-LOCKED LOOP OPERATING BASED ON FRACTIONAL INPUT AND OUTPUT PHASES - In one aspect, a digital PLL (DPLL) operates based on fractional portions of input and output phases. The DPLL accumulates at least one input signal to obtain an input phase. The DPLL determines a fractional portion of an output phase based on a phase difference between an oscillator signal from an oscillator and a reference signal, e.g., using a time-to-digital converter (TDC). The DPLL determines a phase error based on the fractional portion of the input phase and the fractional portion of the output phase. The DPLL then generates a control signal for the oscillator based on the phase error. In another aspect, a DPLL includes a synthesized accumulator that determines a coarse output phase by keeping tracking of the number of oscillator signal cycles based on the reference signal. | 06-04-2009 |
20090153248 | AMPLIFIER WITH DYNAMIC BIAS - Techniques are provided for dynamically biasing an amplifier to extend the amplifier's operating range while conserving power. In an embodiment, a detector is provided to measure the amplifier output to determine an operating region of the amplifier. The output of the detector may be input to a bias adjuster, which outputs a dynamic voltage level supplied to at least one bias transistor in the amplifier. Multiple embodiments of the detector and bias adjuster are disclosed. | 06-18-2009 |
20090161588 | SYSTEMS AND METHODS FOR CONTROLLING THE VOLTAGE OF SIGNALS USED TO CONTROL POWER AMPLIFIERS - A method for controlling the voltage of signals used to control power amplifiers is described. A first multiplexer and a second multiplexer are set to an enabling signal. The first multiplexer is on a first integrated circuit and the second multiplexer is on a second integrated circuit. A command is written to the first multiplexer to set the first multiplexer to one of a plurality of control signals used to control a power amplifier. A command is written to the second multiplexer to select one of the plurality of control signals that maps to the first multiplexer. The second integrated circuit is connected to a power supply. | 06-25-2009 |
20090175399 | DIGITAL PHASE-LOCKED LOOP WITH GATED TIME-TO-DIGITAL CONVERTER - A digital PLL (DPLL) includes a time-to-digital converter (TDC) and a control unit. The TDC is periodically enabled for a short duration to quantize phase information and disabled for the remaining time to reduce power consumption. The TDC receives a first clock signal and a first reference signal and provides a TDC output indicative of the phase difference between the first clock signal and the first reference signal. The control unit generates an enable signal based on a main reference signal and enables and disables the TDC with the enable signal. In one design, the control unit delays the main reference signal to obtain the first reference signal and a second reference signal, generates the enable signal based on the main reference signal and the second reference signal, and gates a main clock signal with the enable signal to obtain the first clock signal for the TDC. | 07-09-2009 |
20090219073 | HIGH RESOLUTION TIME-TO-DIGITAL CONVERTER - A time-to-digital converter (TDC) can have a resolution that is finer than the propagation delay of an inverter. In one example, a fractional-delay element circuit receives a TDC input signal and generates therefrom a second signal that is a time-shifted facsimile of a first signal. The first signal is supplied to a first delay line timestamp circuit (DLTC) and the second signal is supplied to a second DLTC. The first DLTC generates a first timestamp indicative of a time between an edge of a reference input signal to the TDC and an edge of the first signal. The second DLTC generates a second timestamp indicative of a time between the edge of the reference input signal and an edge of the second signal. The first and second timestamps are combined and together constitute a high-resolution overall TDC timestamp that has a finer resolution than either the first or second timestamps. | 09-03-2009 |
20090219187 | HIGH-SPEED TIME-TO-DIGITAL CONVERTER - Techniques for enabling a time-to-digital (TDC) to sample with sub-inverter delay resolution are disclosed. In an embodiment, the inputs to a differential D-Q flip-flop in the TDC are coupled to a single-ended signal and a delayed and inverted version of that signal to allow time interpolation of the signal. Further disclosed are techniques to balance the loads of a first delay line and a complementary delay line within the TDC. | 09-03-2009 |
20090262878 | SYSTEM AND METHOD OF CALIBRATING POWER-ON GATING WINDOW FOR A TIME-TO-DIGITAL CONVERTER (TDC) OF A DIGITAL PHASE LOCKED LOOP (DPLL) - A system and method are disclosed related to calibrating a power-on gating window for a time-to-digital converter (TDC) of a digital phase locked loop (DPLL). The gating window is calibrated to ensure proper operation of the DPLL, while at the same time operating the TDC in a power efficient manner. In particular, the technique entails setting the width of the TDC gating window to a default value; operating the DPLL until the control loop is substantially locked; decreasing the width of the TDC gating window by a predetermined amount, while monitoring the phase error signal generated by the phase error device of the DPLL; determining the current width of the TDC gating window at substantially a time when the phase error arrives at or crosses a predetermined threshold; and increasing the current width of the TDC gating window by a predetermined amount to build in a margin of error for the operating width of the TDC gating window. | 10-22-2009 |
20090267657 | METHOD AND APPARATUS FOR DIVIDER UNIT SYNCHRONIZATION - A method an apparatus for synchronizing phases of one or more divider units comprise powering on a master divider unit to provide a reference signal. A phase of a slave divider unit is synchronized to the reference signal from the master divider unit by providing a power on pulse at the slave divider unit, synchronizing the phase of the slave divider unit to the reference signal using a digitally controlled oscillator, and powering on the slave divider unit after a first predetermined delay period following a rising edge of the power on pulse. By synchronizing a slave divider unit to the reference signal from the master divider unit, any number of slave divider units may be powered on and in-phase with each other. | 10-29-2009 |
20090268859 | SYSTEM AND METHOD OF CONTROLLING POWER CONSUMPTION IN A DIGITAL PHASE LOCKED LOOP (DPLL) - An apparatus comprising a programmable frequency device adapted to generate a reference clock selected from a set of distinct frequency clocks, wherein the programmable frequency device is further adapted to maintain the same temporal relationship of the triggering edges of the reference clock when switching between the distinct frequency clocks. The apparatus further comprises a phase locked loop (PLL), such as a digital PLL (DPLL), that uses the selected reference clock to establish a predetermined phase relationship between an input signal and an output signal. By maintaining substantially the same temporal relationship of the reference clock when switching between distinct frequency clocks, the continual and effective operation of the phase locked loop (PLL) is not significantly disturbed while changing the reference clock. This may be used to control the power consumption of the apparatus. | 10-29-2009 |
20090302963 | BI-POLAR MODULATOR - A bi-polar modulator that can perform quadrature modulation using amplitude modulators is described. In one design, the bi-polar modulator includes first and second amplitude modulators and a summer. The first amplitude modulator amplitude modulates a first carrier signal with a first input signal and provides a first amplitude modulated signal. The second amplitude modulator amplitude modulates a second carrier signal with a second input signal and provides a second amplitude modulated signal. The summer sums the first and second amplitude modulated signals and provides a quadrature modulated signal that is both amplitude and phase modulated. The first and second input signals may be obtained based on absolute values of first and second modulating signals, respectively. The first and second carrier signals have phases determined based on the sign of the first and second modulating signals, respectively. Each amplitude modulator may be implemented with a class-E amplifier. | 12-10-2009 |
20090309666 | DYNAMIC CALIBRATION TECHNIQUES FOR DIGITALLY CONTROLLED OSCILLATOR - Techniques for calibrating digitally controlled oscillators (DCOs) are disclosed. In an aspect of the disclosure, an initial set of control codes for operating the DCO is determined. A range of output frequencies produced from the initial set is identified. Gaps or instances of overlap are identified in the frequency range. For the overlap case, control codes are removed from the initial set that correspond to the overlap instance to establish a revised set. For the gap case, control codes are added to the initial set for producing frequencies values that fill the gap. An apparatus for performing the same is also disclosed. | 12-17-2009 |
20100102894 | DIGITALLY CONTROLLED OSCILLATOR WITH IMPROVED DIGITAL FREQUENCY CALIBRATION - Techniques for calibrating digitally controlled oscillators (DCOS) are disclosed. In one aspect of the disclosure, an initial set of control codes for operating the DCO with a coarse frequency tuning bank with multiple overlapping coarse frequency tuning segments (LTBs) and one fine main frequency tuning bank (MTB) is determined. A range of output frequencies produced from the initial set is identified. Instances of overlap are identified in the frequency range between consecutive LTB segments. An offset in the MTB is added that corresponds to the overlap instance between consecutive LTBs to establish a revised set. The revised control codes are utilized to tune the DCO over the desired frequency range. | 04-29-2010 |
20100182090 | ULTRA LOW NOISE HIGH LINEARITY LNA FOR MULTI-MODE TRANSCEIVER - An amplifier for operating at low, middle or high linearity modes, the amplifier comprising a first low noise amplifier (LNA) coupled to a second low noise amplifier for providing amplification; a first degeneration inductor coupled to the first LNA for providing impedance matching; a −g | 07-22-2010 |
20100231315 | WIDEBAND PHASE MODULATOR - An apparatus for phase modulation includes a delay locked loop configured to generate from a reference signal a plurality of phase shifted signals, each of the phase shifted signals being locked to the reference signal and having a different phase shift from the other phase shifted signals with respect to the reference signal, and a multiplexer configured to select one of the phase shifted signals. | 09-16-2010 |
20110304368 | WIDEBAND PHASE MODULATOR - An apparatus for phase modulation includes a delay locked loop configured to generate from a reference signal a plurality of phase shifted signals, each of the phase shifted signals being locked to the reference signal and having a different phase shift from the other phase shifted signals with respect to the reference signal, and a multiplexer configured to select one of the phase shifted signals. | 12-15-2011 |
20130287065 | ULTRA-WIDE BAND FREQUENCY MODULATOR - An ultra-wide band frequency modulator is disclosed. The frequency modulator includes a direct modulation phase lock loop that receives a small component. The frequency modulator also includes a delay module that produces a plurality of delay lines. The frequency modulator further includes an edge selector that receives a large component and the plurality of delay lines. | 10-31-2013 |
20140253206 | SYSTEMS AND METHODS FOR PROVIDING LOW-PASS FILTERING - A low-pass filter circuit is described. The low-pass filter circuit includes a pseudo-resistor. The pseudo-resistor includes at least one metal-oxide-semiconductor field-effect transistor. The at least one metal-oxide-semiconductor field-effect transistor receives a digital power supply domain signal. The low-pass filter circuit also includes a capacitor. The capacitor is coupled to the pseudo-resistor. The capacitor provides a filtered signal. The low-pass filter circuit may pass digital signal transitions and provide low-pass filtering when there is no signal transition. | 09-11-2014 |
20140266127 | LOW POWER AND DYNAMIC VOLTAGE DIVIDER AND MONITORING CIRCUIT - A voltage divider circuit is provided that automatically and dynamically adjusts its voltage divider chains as a supply voltage changes. The voltage divider circuit includes a plurality of voltage divider branches having different divider factors to divide the supply voltage and obtain a divided supply voltage. Additionally, a control circuit is coupled to the plurality of voltage divider branches and adapted to automatically monitor the supply voltage and dynamically select a voltage divider branch from among the plurality of voltage divider branches to maintain a selected divided supply voltage within a pre-determined voltage range. | 09-18-2014 |
20140266353 | MIXED SIGNAL TDC WITH EMBEDDED T2V ADC - A time-to-digital converter converts the difference between transition times of a reference clock signal and an oscillating signal to a digital signal whose value is proportional to the transitions timing difference. The time-to-digital converter includes an edge detector, a time-to-voltage converter, and an analog-to-digital converter. The edge detector is adapted to detect, during each period of the reference clock signal, the edge (transition) of the oscillating signal that is closest to the edge of the reference clock signal. The time-to-voltage converter is adapted to generate an analog signal proportional to a difference in time between the detected edge of the oscillating signal and the edge of the reference clock signal. The analog-to-digital converter is adapted to convert the analog signal to a digital signal whose value is proportional the difference between the occurrence of the detected edge of the oscillating signal and the edge of the reference clock signal. | 09-18-2014 |
20150015343 | DEVICES AND METHODS FOR REDUCING NOISE IN DIGITALLY CONTROLLED OSCILLATORS - One feature pertains to a digitally controlled oscillator (DCO) that comprises a variable capacitor and noise reduction circuitry. The variable capacitor has a variable capacitance value that controls an output frequency of the DCO. The variable capacitance value is based on a first bank capacitance value provided by a first capacitor bank, a second bank capacitance value provided by a second capacitor bank, and an auxiliary bank capacitance value provided by an auxiliary capacitor bank. The noise reduction circuitry is adapted to adjust the variable capacitance value by adjusting the auxiliary bank capacitance value while maintaining at least one of the first bank capacitance value and/or the second bank capacitance value substantially unchanged. Prior to adjusting the variable capacitance value, the noise reduction circuitry may determine that a received input DCO control word transitions across a capacitor bank sensitive boundary. | 01-15-2015 |
20150085902 | RFDAC Transmitter Using Multiphase Image Select FIR DAC and Delta Sigma Modulator with Multiple Rx Band NTF Zeros - A transmitter includes a delta-sigma modulator characterized by a noise transfer function having a multitude of zeroes positioned substantially near a frequency band of a receive signal. The transmitter further includes, in part, a multi-phase digital-to-analog (DAC) converter converting an output signal of the delta-sigma modulator to an analog signal. The DAC is characterized by a transfer function that passes the desired signal to its output and attenuates a multitude of images of the sampling clock signal. The transmitter transmits at a frequency defined by an odd multiple of a fraction of the sampling clock signal frequency. The DAC includes a number of stages each pair of which is associated with one of the images being attenuated. The delta-sigma modulator includes a multitude of stages each associated with a different one of the zeroes. Each stage of said delta-sigma modulator optionally receives three tap coefficients. | 03-26-2015 |