Patent application number | Description | Published |
20110003421 | METHOD OF FORMING MONOLITHIC CMOS-MEMS HYBRID INTEGRATED, PACKAGED STRUCTURES - A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures includes the steps of providing: providing at least one semiconductor substrate having a CMOS device area including dielectric layers and metallization layers; applying at least one protective layer overlying the CMOS device area; forming at least one opening on the protective layer and patterning the dielectric and metallization layers to access the semiconductor substrate; forming at least one opening on the semiconductor substrate by etching the dielectric and metallization layers; applying at least one filler layer in the at least one opening on the semiconductor substrate; positioning at least one chip on the filler layer, the chip including a prefabricated front face and a bare backside; applying a first insulating layer covering the front face of the chip providing continuity from the semiconductor substrate to the chip; forming at least one via opening on the insulating layer covering the chip to access at least one contact area; applying at least one metallization layer overlying the insulating layer on the substrate and the chip connecting the metallization layer on the substrate to the at least one another contact area on the chip; applying a second insulating layer overlying the metallization layer on the at least one chip; applying at least one interfacial layer; applying at least one rigid substrate overlying the interfacial layer; and applying at least one secondary protective layer overlying the rigid substrate. | 01-06-2011 |
20110003422 | METHOD OF FORMING MONOLITHIC CMOS-MEMS HYBRID INTEGRATED, PACKAGED STRUCTURES - A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures includes the steps of providing: providing at least one semiconductor substrate having a CMOS device area including dielectric layers and metallization layers; applying at least one protective layer overlying the CMOS device area; forming at least one opening on the protective layer and patterning the dielectric and metallization layers to access the semiconductor substrate; forming at least one opening on the semiconductor substrate by etching the dielectric and metallization layers; applying at least one filler layer in the at least one opening on the semiconductor substrate; positioning at least one chip on the filler layer, the chip including a prefabricated front face and a bare backside; applying a first insulating layer covering the front face of the chip providing continuity from the semiconductor substrate to the chip; forming at least one via opening on the insulating layer covering the chip to access at least one contact area; applying at least one metallization layer overlying the insulating layer on the substrate and the chip connecting the metallization layer on the substrate to the at least one another contact area on the chip; applying a second insulating layer overlying the metallization layer on the at least one chip; applying at least one interfacial layer; applying at least one rigid substrate overlying the interfacial layer; and applying at least one secondary protective layer overlying the rigid substrate. | 01-06-2011 |
20110027941 | METHOD OF FORMING MONOLITHIC CMOS-MEMS HYBRID INTEGRATED, PACKAGED STRUCTURES - A method of forming Monolithic CMOS-MEMS hybrid integrated, packaged structures includes the steps of providing: providing a semiconductor substrate with pre-fabricated cmos circuits on the front side and a polished back-side with through substrate conductive vias; forming at least one opening in the polished backside of the semiconductor substrate by appropriately protecting the front-side; applying at least one filler material in the at least one opening on the semiconductor substrate; positioning at least one prefabricated mems, nems or cmos chip on the filler material, the chip including a front face and a bare back face with the prefabricated mems/nems chips containing mechanical and dielectric layers; applying at least one planarization layer overlying the substrate, filler material and the chip; forming at least one via opening on a portion of the planarization layer interfacing pads on the chip and the through substrate conductive vias; applying at least one metallization layer overlying the planarization layer on the substrate and the chip connecting the through substrate conductive vias to the at least one chip; applying at least one second insulating layer overlying the metallization layer; performing at least one micro/nano fabrication etching step to release the mechanical layer on the prefabricated mems/nems chips; positioning protective cap to package the integrated device over the mems/nems device area on the pre-fabricated chips. | 02-03-2011 |
20110054579 | FLEXIBLE PENETRATING ELECTRODES FOR NEURONAL STIMULATION AND RECORDING AND METHOD OF MANUFACTURING SAME - A flexible penetrating array for neuronal applications includes an insulating layer. A conductive layer is formed on the insulating layer. A flexible polymer substrate is formed on the conductive layer; the polymer substrate includes defined penetrating electrodes. A first metallization layer is formed on the polymer substrate. A second flexible polymer layer is formed on the first metallization layer. A second metallization layer is formed on the second flexible polymer layer. A third flexible polymer layer is formed on the second metallization layer. The third flexible polymer layer is patterned to expose the second metallization layer that is integrated with the out of plane conductive layer and first metallization layer. Also disclosed is a method of forming the array. | 03-03-2011 |
Patent application number | Description | Published |
20090075620 | LOCAL OSCILLATOR BUFFER AND MIXER HAVING ADJUSTABLE SIZE - Selectable sizes for a local oscillator (LO) buffer and mixer are disclosed. In an exemplary embodiment, LO buffer and/or mixer size may be increased when a receiver or transmitter operates in a high gain mode, while LO buffer and/or mixer size may be decreased when the receiver or transmitter operates in a low gain mode. In an exemplary embodiment, LO buffer and mixer sizes are increased and decreased in lock step. Circuit topologies and control schemes for specific exemplary embodiments of LO buffers and mixers having adjustable size are disclosed. | 03-19-2009 |
20090111414 | LOCAL OSCILLATOR BUFFER AND MIXER HAVING ADJUSTABLE SIZE - Selectable sizes for a local oscillator (LO) buffer and mixer are disclosed. In an embodiment, LO buffer and/or mixer size may be increased when a receiver operates in a high gain mode, while LO buffer and/or mixer size may be decreased when the receiver operates in a low gain mode. In an embodiment, LO buffer and mixer sizes are increased and decreased in lock step. Circuit topologies and control schemes for specific embodiments of LO buffers and mixers having adjustable size are disclosed. | 04-30-2009 |
20090154595 | I-Q MISMATCH CALIBRATION AND METHOD - Techniques are provided for reducing mismatch between the in-phase (I) and quadrature (Q) channels of a communications transmitter or receiver. In an exemplary embodiment, separate voltages are applied to bias the gates or bulks of the transistors in a mixer of the I channel versus a mixer of the Q channel. In another exemplary embodiment, separate voltages are applied to bias the common-mode reference voltage of a transimpedance amplifier associated with each channel. Techniques are further provided for deriving bias voltages to minimize a measured residual sideband in a received or transmitted signal, or to optimize other parameters of the received or transmitted signal. Techniques for generating separate bias voltages using a bidirectional and unidirectional current digital-to-analog converter (DAC) are also disclosed. | 06-18-2009 |
20100321137 | PROGRAMMABLE VARACTOR AND METHODS OF OPERATION THEREOF - Exemplary embodiments are directed to a programmable varactor device. A varactor device may include an input device configured to receive a tuning voltage and generate a bias voltage at least partially dependent on the tuning voltage. The varactor device may also include a varactor pair coupled to the input device and having a first variable capacitor and a second variable capacitor, wherein each of the first variable capacitor and a second variable capacitor are configured for operable coupling to each of the bias voltage and the tuning voltage. | 12-23-2010 |
20110001539 | MIXER-TRANSCONDUCTANCE INTERFACE - Techniques for providing an efficient interface between a mixer block and a transconductance (Gm) block. In an exemplary embodiment, the output currents of at least two unit cells of the transconductance block are conductively coupled together, and coupled to the mixer block using a single conductive path. For a differential signal, the conductive path may include two conductive leads. Within the mixer block, the single conductive path may be fanned out to at least two unit cells of the mixer block. At least one Gm unit cell may be selectively enabled or disabled to control the gain setting of the mixer-transconductance block. The techniques may further be applied to transceiver architectures supporting in-phase and quadrature mixing, as well as multi-mode and/or multi-band operation. | 01-06-2011 |
20130234799 | SHARED BYPASS CAPACITOR MATCHING NETWORK - A receiver is described. The receiver includes a first amplifier on an integrated circuit. The receiver also includes a second amplifier on the integrated circuit. The receiver further includes a first inductor coupled to the first amplifier. The receiver also includes a second inductor coupled to the second amplifier. The receiver further includes a first capacitor coupled to the first inductor, the second inductor, and to ground. The first capacitor is shared between a first matching network for the first amplifier and a second matching network for the second amplifier. | 09-12-2013 |
20130258911 | HYBRID TRANSFORMER BASED INTEGRATED DUPLEXER FOR MULTI-BAND/MULTI-MODE RADIO FREQUENCY (RF) FRONT END - An integrated duplexer based on electrical balance is described. The duplexer module includes a hybrid transformer. The hybrid transformer includes a primary coil and a secondary coil. The primary coil is coupled between an output of a power amplifier and an antenna. The secondary coil is coupled between an input of a low noise amplifier and ground. The duplexer also includes a balancing impedance that is coupled between the primary coil and the secondary coil. | 10-03-2013 |
20130259099 | TUNABLE NOTCH FILTER USING FEEDBACK THROUGH AN EXISTING FEEDBACK RECEIVER - A wireless communication device configured for reducing Tx leakage in a receive signal is described. The wireless communication device includes a transceiver chip. The transceiver chip includes a receiver, a feedback receiver and a transmitter. The wireless communication device also includes a Tx leakage signal reduction module. The Tx leakage signal reduction module reuses the feedback receiver. | 10-03-2013 |
20130259102 | TUNABLE NOTCH FILTER USING FEEDBACK THROUGH AN EXISTING FEEDBACK RECEIVER - A wireless communication device configured for reducing Tx leakage in a receive signal is described. The wireless communication device includes a transceiver chip. The transceiver chip includes a receiver, a feedback receiver and a transmitter. The wireless communication device also includes a Tx leakage signal reduction module. The Tx leakage signal reduction module reuses the feedback receiver. | 10-03-2013 |
20130281041 | IMPEDANCE BALANCING FOR POWER SUPPLY REJECTION IN SINGLE-ENDED RECEIVERS - Power supply rejection in a single-ended receiver, through impedance balancing, is described. The single-ended receiver includes a first low noise amplifier and a second low noise amplifier. The single-ended receiver also includes a multi-port coupled transformer that outputs a differential signal. The multi-port coupled transformer includes a first primary coil that is coupled to an output of the first low noise amplifier and a second primary coil. The single-ended receiver also includes balancing impedances at the output of each of the low noise amplifiers. These impedances can be configured such that the on impedance of the first low noise amplifier equals the combined impedance of the off impedance of the second low noise amplifier and the balancing impedance. This balancing of impedances on the first and second primary coils results in power supply rejection of noise and spurious signals. | 10-24-2013 |
20130295870 | SINGLE-ENDED RECEIVER WITH A MULTI-PORT TRANSFORMER AND SHARED MIXER - A single-ended receiver is described. The single-ended receiver includes a multi-port transformer that outputs a differential signal. The multi-port transformer includes a first primary coil that is coupled to an output of a first low noise amplifier. The multi-port transformer also includes a second primary coil that is coupled to an output of a second low noise amplifier. The multi-port transformer further includes a first secondary coil. The single-ended receiver also includes a shared mixer that receives the differential signal from the multi-port transformer. | 11-07-2013 |
20140111252 | THRESHOLD TRACKING BIAS VOLTAGE FOR MIXERS - Bias voltage generators that can generate variable bias voltages for transistors in mixers and other circuits are disclosed. In an exemplary design, an apparatus (e.g., a wireless device or an integrated circuit (IC)) includes at least one transistor and a bias voltage generator. The transistor(s) have a threshold voltage and receive a bias voltage. The bias voltage generator generates the bias voltage based on changes to the threshold voltage of the transistor(s), e.g., due to IC process and/or temperature. In an exemplary design, the bias voltage generator includes a replica transistor that tracks the transistor(s) and an op-amp that provides a gate voltage for the replica transistor. The bias voltage is generated based on the gate voltage. The bias voltage generator may generate the bias voltage (i) to track the threshold voltage of the transistor(s) in a first mode or (ii) based on a fixed voltage in a second mode. | 04-24-2014 |
20140113573 | AMPLIFIERS WITH SHUNT SWITCHES - Amplifiers with shunt switches to mitigate interference are disclosed. In an exemplary design, an apparatus includes an amplifier and a shunt switch. The amplifier has an input operatively coupled to an input/output (I/O) pad of an integrated circuit (IC) chip. The shunt switch grounds the amplifier when the shunt switch is closed. The shunt switch is isolated from the I/O pad and the amplifier input. The amplifier may be a low noise amplifier (LNA) or some other type of amplifier. In an exemplary design, the shunt switch is isolated from the I/O pad by a series switch. The series switch and the shunt switch may be closed when the amplifier is disabled and may be opened when the amplifier is enabled. | 04-24-2014 |
20140139042 | PORT ISOLATION IN SHARED TRANSFORMERS - Techniques for improving performance of a transformer shared amongst a plurality of operating modes. In an aspect, first and second primary windings of a transformer are coupled to an AC ground voltage. Primary windings are mutually coupled to a secondary winding of the transformer. To render the second primary winding inactive, e.g., when operating in a first mode, a switch coupling the second primary winding to the common reference voltage is opened. Similarly, when it is desired to render the first primary winding inactive, e.g., when operating in a second mode, a switch coupling the first primary winding to the common reference voltage is opened. In this manner, the inactive primary winding advantageously does not load the secondary winding. Further aspects provide for, e.g., extending the techniques to more than two modes, and alternative techniques to mutually couple the signal from the primary to the secondary winding. | 05-22-2014 |
20140167862 | ELECTROSTATIC DISCHARGE PROTECTION OF AMPLIFIER CASCODE DEVICES - Exemplary embodiments are directed to providing electrostatic discharge (ESD) protection of a cascode device of an amplifier. In an exemplary embodiment, a transistor is configured to receive a bias voltage and at least one circuit element coupled to the transistor and configured to receive an input voltage via an input pad. Additionally at least one diode can be coupled to a drain of the first transistor and configured to limit a voltage potential at an internal node of the amplifier caused by the input pad. | 06-19-2014 |
Patent application number | Description | Published |
20130328707 | I-Q MISMATCH CALIBRATION AND METHOD - Techniques are provided for reducing mismatch between the in-phase (I) and quadrature (Q) channels of a communications transmitter or receiver. In an exemplary embodiment, separate voltages are applied to bias the gates or bulks of the transistors in a mixer of the I channel versus a mixer of the Q channel. In another exemplary embodiment, separate voltages are applied to bias the common-mode reference voltage of a transimpedance amplifier associated with each channel. Techniques are further provided for deriving bias voltages to minimize a measured residual sideband in a received or transmitted signal, or to optimize other parameters of the received or transmitted signal. Techniques for generating separate bias voltages using a bidirectional and unidirectional current digital-to-analog converter (DAC) are also disclosed. | 12-12-2013 |
20130336143 | I-Q MISMATCH CALIBRATION AND METHOD - Techniques are provided for reducing mismatch between the in-phase (I) and quadrature (Q) channels of a communications transmitter or receiver. In an exemplary embodiment, separate voltages are applied to bias the gates or bulks of the transistors in a mixer of the I channel versus a mixer of the Q channel. In another exemplary embodiment, separate voltages are applied to bias the common-mode reference voltage of a transimpedance amplifier associated with each channel. Techniques are further provided for deriving bias voltages to minimize a measured residual sideband in a received or transmitted signal, or to optimize other parameters of the received or transmitted signal. Techniques for generating separate bias voltages using a bidirectional and unidirectional current digital-to-analog converter (DAC) are also disclosed. | 12-19-2013 |
20160072441 | INPUT SWITCH LEAKAGE COMPENSATION - An apparatus including: a first switch configured to provide a feed-forward path at an input of a first amplifier of a plurality of amplifiers coupled together at a single port, the feed-forward path configured to substantially reduce a leakage current into an input of a second amplifier of the plurality of amplifiers. | 03-10-2016 |
20160080018 | ON-CHIP LINEARITY CALIBRATION - An apparatus including: at least one receiver having injection points and having at least an amplifier and a transformer; and a plurality of isolation switches coupled to injection points of the at least one receiver, the plurality of isolation switches configured to route a calibration signal generated by a transmitter to one of the injection points. | 03-17-2016 |
Patent application number | Description | Published |
20080238370 | BATTERY PACK FOR CORDLESS POWER TOOLS - A battery pack which includes a battery pack electronic control circuit adapted to control an attached power tool and/or an attached charger. The battery pack includes additional protection circuits, methodologies and devices to protect against fault conditions within the pack, as the pack is operatively attached to and providing power to the power tool, and/or as the pack is operatively attached to and being charged by the charger. | 10-02-2008 |
20080315834 | Battery pack chargers and charging method - A method of charging a battery pack is provided. The method includes: electronically connecting a battery pack to a charger; detecting information regarding the battery pack; determining an appropriate charging regime based on the detected information; and applying the charging regime to the battery pack. A battery charger may also provided. The battery charger includes: a first terminal for connecting to a battery pack; a second terminal for connecting to a battery pack, a microprocessor operatively connected to the terminals and configured to receive a signal from at least one terminal regarding a battery pack connected to the terminal and control the charger to select and apply a charging regime to the battery pack according to the signal. | 12-25-2008 |
20100213900 | BATTERY PACK FOR CORDLESS POWER TOOLS - A battery pack which includes a battery pack electronic control circuit adapted to control an attached power tool and/or an attached charger. The battery pack includes additional protection circuits, methodologies and devices to protect against fault conditions within the pack, as the pack is operatively attached to and providing power to the power tool, and/or as they pack is operatively attached to and being charged by the charger. | 08-26-2010 |
20110163701 | Battery Pack for Cordless Power Tools - A battery pack which includes a battery pack electronic control circuit adapted to control an attached power tool and/or an attached charger. The battery pack includes additional protection circuits, methodologies and devices to protect against fault conditions within the pack, as the pack is operatively attached to and providing power to the power tool, and/or as the pack is operatively attached to and being charged by the charger. | 07-07-2011 |
20130265766 | LIGHT MODULE AND LIGHT STAND ASSEMBLY - A light stand assembly with a base having pivoting legs and a power supply circuit. An adjustable post detachably connects to the base. The adjustable post is configured for telescoping movement between a lower position and a raised position, and secures at a selected position with latches. An adjustable post connector moveably connects to the adjustable post. A pair of light modules detachably connect to the adjustable post connector and operatively connects to the power supply circuit. | 10-10-2013 |
20130265780 | LIGHT MODULE AND LIGHT STAND ASSEMBLY - A light stand assembly with a base having pivoting legs and a power supply circuit. An adjustable post detachably connects to the base. The adjustable post is configured for telescoping movement between a lower position and a raised position, and secures at a selected position with latches. An adjustable post connector moveably connects to the adjustable post. A pair of light modules detachably connect to the adjustable post connector and operatively connects to the power supply circuit. | 10-10-2013 |
Patent application number | Description | Published |
20130102625 | Artemisinin with Berberine Compositions and Methods of Making - An all-natural herbal composition and methods of preparing the same are provided. The novel Artemisinin Combination Therapy (ACT) consists of artemisinin and its derivatives and berberine, the two active substances mixed with various selected excipient compounds to form a single pill, tablet or capsule for treatment and prevention of malaria, dengue fever, yellow fever, dysentery, Lyme disease, babesiosis, progressive multifocal leukoencephalopathy, | 04-25-2013 |
20150148364 | Artemisinin with Berberine Compositions and Methods of Making - An all-natural herbal composition and methods of preparing the same are provided. The novel Artemisinin Combination Therapy (ACT) consists of artemisinin and its derivatives and berberine, the two active substances mixed with various selected excipient compounds to form a single pill, tablet or capsule for treatment and prevention of malaria, dengue fever, yellow fever, dysentery, Lyme disease, babesiosis, progressive multifocal leukoencephalopathy, | 05-28-2015 |