Patent application number | Description | Published |
20090230463 | INTEGRATED CIRCUIT LONG AND SHORT CHANNEL METAL GATE DEVICES AND METHOD OF MANUFACTURE - A method is provided for manufacturing an integrated circuit including a short channel (SC) device and a long channel (LC) device each overlaid by an interlayer dielectric. The SC device has an SC gate stack and the LC device initially has a dummy gate. In one embodiment, the method includes the steps of removing the dummy gate to form an LC device trench, and depositing metal gate material over the SC device and the LC device. The metal gate material contacts the SC gate stack and substantially fills the LC device trench. | 09-17-2009 |
20100044782 | INTEGRATED CIRCUIT HAVING LONG AND SHORT CHANNEL METAL GATE DEVICES AND METHOD OF MANUFACTURE - Embodiments of an integrated circuit are provided. In one embodiment, the integrated circuit includes a substrate, a short channel (SC) device, and a long channel (LC) device. The short channel device includes an SC gate insulator overlying a first portion of the substrate, an SC metal gate overlying the SC gate insulator, a polycrystalline silicon layer overlying the metal gate, and a silicide layer formed on the polycrystalline silicon layer. The long channel (LC) device includes an LC gate insulator overlying a second portion of the substrate and an LC metal gate overlying the LC gate insulator. An etch stop layer overlies an upper surface of the substrate, and an interlayer dielectric overlies an upper surface of the etch stop layer. An SC cap is disposed in the interlayer dielectric, overlies the device, and is formed substantially from the same metal as is the LC metal gate. | 02-25-2010 |
20100052094 | SEMICONDUCTOR DEVICE WITH ISOLATION TRENCH LINER, AND RELATED FABRICATION METHODS - A method of manufacturing a semiconductor device is provided herein, where the width effect is reduced in the resulting semiconductor device. The method involves providing a substrate having semiconductor material, forming an isolation trench in the semiconductor material, and lining the isolation trench with a liner material that substantially inhibits formation of high-k material thereon. The lined trench is then filled with an insulating material. Thereafter, a layer of high-k gate material is formed over at least a portion of the insulating material and over at least a portion of the semiconductor material. The liner material divides the layer of high-k gate material, which prevents the migration of oxygen over the active region of the semiconductor material. | 03-04-2010 |
20100072623 | SEMICONDUCTOR DEVICE WITH IMPROVED CONTACT PLUGS, AND RELATED FABRICATION METHODS - Semiconductor device structures and related fabrication methods are provided herein. One fabrication method relates to the formation of conductive contact plugs for a semiconductor device. The method begins by providing a semiconductor device structure having a conductive contact region, a layer of insulating material overlying the conductive contact region, and a via formed in the layer of insulating material and terminating at the conductive contact region. The fabrication process then deposits a first electrically conductive material on the semiconductor device structure such that the first electrically conductive material at least partially fills the via. Then, the process anisotropically etches a portion of the first electrically conductive material located in the filled via, resulting in a lined via. Thereafter, the process deposits a second electrically conductive material on the semiconductor device structure such that the second electrically conductive material at least partially fills the lined via. | 03-25-2010 |
20100213553 | METAL OXIDE SEMICONDUCTOR DEVICES HAVING BURIED GATE CHANNELS AND METHODS FOR FABRICATING THE SAME - Methods for forming a semiconductor device comprising a semiconductor substrate are provided. In accordance with an exemplary embodiment, a method comprises forming a channel layer overlying the semiconductor substrate, forming a channel capping layer having a first surface overlying the channel layer, oxidizing the first surface of the channel capping layer, and depositing a high-k dielectric layer overlying the channel capping layer. | 08-26-2010 |
20100213555 | METAL OXIDE SEMICONDUCTOR DEVICES HAVING CAPPING LAYERS AND METHODS FOR FABRICATING THE SAME - Methods for forming a semiconductor device comprising a semiconductor substrate are provided. In accordance with an exemplary embodiment, a method comprises forming a silicon oxide layer overlying the semiconductor substrate, forming a metal oxide gate capping layer overlying the silicon oxide layer, depositing a first metal gate electrode layer overlying the metal oxide gate capping layer, and removing a portion of the first metal gate electrode layer and the metal oxide gate capping layer to form a gate stack. | 08-26-2010 |
20110260263 | SEMICONDUCTOR DEVICE WITH ISOLATION TRENCH LINER - A method of manufacturing a semiconductor device is provided herein, where the width effect is reduced in the resulting semiconductor device. The method involves providing a substrate having semiconductor material, forming an isolation trench in the semiconductor material, and lining the isolation trench with a liner material that substantially inhibits formation of high-k material thereon. The lined trench is then filled with an insulating material. Thereafter, a layer of high-k gate material is formed over at least a portion of the insulating material and over at least a portion of the semiconductor material. The liner material divides the layer of high-k gate material, which prevents the migration of oxygen over the active region of the semiconductor material. | 10-27-2011 |
20120223399 | SEMICONDUCTOR DEVICE WITH ISOLATION TRENCH LINER - A semiconductor device includes a layer of semiconductor material having an active transistor region defined therein, an isolation trench formed in the semiconductor material adjacent the active transistor region, and a trench liner lining the isolation trench, wherein the trench liner is formed from a material that substantially inhibits formation of high-k material thereon, and wherein the isolation trench and the trench liner together form a lined trench. The device has an insulating material in the lined trench, and high-k gate material overlying at least a portion of the insulating material and overlying at least a portion of the active transistor region, such that the trench liner divides and separates the high-k gate material overlying the at least a portion of the insulating material from the high-k gate material overlying the at least a portion of the active transistor region. | 09-06-2012 |
Patent application number | Description | Published |
20090294754 | NOVEL TECHNIQUES FOR PRECISION PATTERN TRANSFER OF CARBON NANOTUBES FROM PHOTO MASK TO WAFERS - A method for patterning CNTs on a wafer wherein a CNT layer is provided on a substrate, a hard mask film is deposited on the CNT layer, a BARC layer (optional) is coated on the hard mask film, and a resist is patterned on the BARC layer (or directly on the hard mask film if the BARC layer is not included). Then, the resist pattern is effectively transferred to the hard mask film by etching the BARC layer (if provided) and etching partly into, but not entirely through, the hard mask film (i.e., etching is stopped before reaching the CNT layer). Then, the resist and the BARC layer (if provided) is stripped, and the hard mask pattern is effectively transferred to the CNTs by etching away (preferably by using C1, F plasma) the portions of the hard mask which have been already partially etched away. | 12-03-2009 |
20100148277 | ISOLATED METAL PLUG PROCESS FOR USE IN FABRICATING CARBON NANOTUBE MEMORY CELLS - The present invention is directed to structures and methods of fabricating electromechanical memory cells having nanotube crossbar elements. Such memory cells include a substrate having transistor with a contact that electrically contacts with the transistor. A first support layer is formed over the substrate with an opening that defines a lower chamber above the electrical contact. A nanotube crossbar element is arranged to span the lower chamber. A second support layer is formed with an opening that defines a top chamber above the lower chamber, the top chamber including an extension region that extends beyond an edge of the lower chamber to expose a portion of the top surface of the first support layer. A roof layer covers the top of the top chamber and includes an aperture that exposes a portion of the extension region of the top chamber and includes a plug that extends into the aperture in the roof layer to seal the top and bottom chambers. The memory cell further includes an electrode that overlies the crossbar element such that electrical signals can activate the electrode to attract or repel the crossbar element to set a memory state for the transistor. | 06-17-2010 |
20130203244 | METHODS FOR PFET FABRICATION USING APM SOLUTIONS - A method for fabricating an integrated circuit is disclosed that includes, in accordance with an embodiment, providing an integrated circuit comprising a p-type field effect transistor (pFET), recessing a surface region of the pFET using an ammonia-hydrogen peroxide-water (APM) solution to form a recessed pFET surface region, and depositing a silicon-based material channel on the recessed pFET surface region. | 08-08-2013 |
20130267086 | PASSIVATING POINT DEFECTS IN HIGH-K GATE DIELECTRIC LAYERS DURING GATE STACK FORMATION - Generally, the present disclosure is directed to techniques for improving the reliability of semiconductor devices with high-k gate dielectric layers by passivating point defects during the gate stack formation. One illustrative method disclosed herein includes performing a plurality of material deposition cycles to form a high-k dielectric layer above a semiconductor material layer, and introducing a passivating material into a gaseous precursor that is used for forming the high-k dielectric layer during at least one of the plurality of material deposition cycles. | 10-10-2013 |
Patent application number | Description | Published |
20150021695 | EPITAXIAL BLOCK LAYER FOR A FIN FIELD EFFECT TRANSISTOR DEVICE - Approaches for enabling uniform epitaxial (epi) growth in an epi junction area of a semiconductor device (e.g., a fin field effect transistor device) are provided. Specifically, a semiconductor device is provided including a dummy gate and a set of fin field effect transistors (FinFETs) formed over a substrate; a spacer layer formed over the dummy gate and each of the set of FinFETs; and an epi material formed within a set of recesses in the substrate, the set of recesses formed prior to removal of an epi block layer over the dummy gate. | 01-22-2015 |
20150076653 | OVERLAY PERFORMANCE FOR A FIN FIELD EFFECT TRANSISTOR DEVICE - Approaches for improving overlay performance for an integrated circuit (IC) device are provided. Specifically, the IC device (e.g., a fin field effect transistor (FinFET)) is provided with an oxide layer and a pad layer formed over a substrate, wherein the oxide layer comprises an alignment and overlay mark, an oxide deposited in a set of openings formed through the pad layer and into the substrate, a mandrel layer deposited over the oxide material and the pad layer, and a set of fins patterned in the IC device without etching the alignment and overlay mark. With this approach, the alignment and overlay mark is provided with the fin cut (FC) layer and, therefore, avoids finification. | 03-19-2015 |