Hall, OR
Corinne Hall, Hillsboro, OR US
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20110054714 | MEMORY MODULE THERMAL MANAGEMENT - A method is disclosed for implementing a scheme to configure thermal management control for a memory device resident on a memory module for a computing platform. A method is also disclosed for implementing the configured thermal management control. In a run-time environment for a computing platform a temperature is obtained from a thermal sensor monitoring the memory module. The memory module is in a given memory module with thermal sensor configuration that includes the memory device. An approximation of a temperature for the memory device is made based on thermal information associated with the given configuration of the memory module and the obtained temperature. The configured thermal management control for the memory device is implemented based on the approximated temperature. Other implementations and examples are also described in this disclosure. | 03-03-2011 |
Danielle Renee Hall, Wilsonville, OR US
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20110176150 | METHOD AND APPARATUS FOR CONVERTING LARGER-SIZED DOCUMENTS TO SMALLER-SIZED DOCUMENTS IN AN IMAGE PRODUCTION DEVICE - A method and apparatus for converting larger-sized documents to smaller-sized documents in an image production device is disclosed and may include receiving a request to scan a larger-sized document, determining if the larger-sized document is to be converted to a smaller-sized-document, wherein if it is determined that the larger-sized document is to be converted to a smaller-sized-document, scanning the larger-sized document to obtain image data, combining the image data from each larger-sized document page into one continuous document, measuring a predetermined amount of image data from the one continuous document, positioning the predetermined amount of image data onto a smaller-sized document page, continue positioning the predetermined amount of image data onto a smaller-sized document pages until there is no more image data left from the one continuous document to position onto a smaller-sized document page, and one of storing the smaller-sized document in a memory and printing the smaller-sized document. | 07-21-2011 |
David D. Hall, Corvallis, OR US
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20090109725 | Data storage in circuit elements with changed resistance - A method of storing data in an array of circuit elements, said method comprising injecting a current into selected circuit elements, said current causing a persistent change in a resistance of said selected circuit elements from a first resistance to a second higher resistance indicative of a binary data bit, wherein said current does not break an electrical circuit in which said circuit element is disposed. | 04-30-2009 |
20110084997 | DETERMINING A HEALTHY FLUID EJECTION NOZZLE - A method of determining a healthy fluid ejection nozzle includes measuring changes in impedance across the nozzle as fluid passes through it. A printhead includes a metal probe that intersects an ink nozzle and an integrated circuit to sense a change in impedance across the nozzle through the metal probe. | 04-14-2011 |
Gale Hall, Portland, OR US
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20120036725 | KICKBACK DETECTION METHOD AND APPARATUS - In various embodiments, a cutting tool such as a chainsaw may include a cutting member that is movable by an engine, one or more sensors configured to detect one or more of acceleration in a direction parallel to one or more axes of the cutting tool and rotational velocity about one or more axes of the cutting tool, and a microprocessor configured to cause movement of the cutting member to stop in response to receiving one or more signals from the one or more sensors. In various embodiments, a method may include receiving, by a microprocessor of a chainsaw, a signal from a gyroscope configured to detect rotational velocity about one or more axes of the cutting tool, and actuating, by the microprocessor, a braking system of the chainsaw to stop movement of a cutting chain around a perimeter of a guide bar in response to the signal. | 02-16-2012 |
James C. Hall, Corvallis, OR US
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20130201263 | PRESSURE BAG - A pressure bag for in a fluid cartridge having an opening in open connection with a channel in a wall of the fluid cartridge. | 08-08-2013 |
James W. Hall, Portland, OR US
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20080216622 | SELF FEEDING DRILL PRESS LATHE ATTACHMENT - The present invention provides a self feeding drill press lathe attachment designed for rotating a workpiece along a horizontal axis to remove material from the workpiece to form it into a desired shape. The drill press lathe attachment comprises a base and a power transfer box along with components commonly found on a lathe, but without a motor. The drill press lathe attachment, or “motorless” lathe, may be mounted directly to the bed of an existing drill press thereby providing an alternative means of achieving turning operations without needing a traditional motor driven lathe. | 09-11-2008 |
John J. Hall, Portland, OR US
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20150067811 | CONDUCTING SESSIONS WITH CAPTURED IMAGE DATA OF PHYSICAL ACTIVITY AND UPLOADING USING TOKEN-VERIFIABLE PROXY UPLOADER - A token-verifiable proxy uploader is disclosed. A token request may be transmitted from an end-user communication device for requesting an upload token from a hosted services server that is configured to authorize transmission of a first media file to a hosted proxy server. The upload token may be transmitted to the end-user communication device. Validation of the user of the end-user communication device may be conducted without the end-user device providing any credentials to the media sharing site and in which the end-user device is does not transmit any credentials specific to the media sharing site as part of the validation. The token validation call may be in response to the hosted proxy server receiving the upload token and either: (1) the first media file from the end-user communication device; or (2) a request from the end-user communication device to upload the first media file to the hosted proxy server. | 03-05-2015 |
Jonathan C. Hall, Hillsboro, OR US
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20110153983 | Gathering and Scattering Multiple Data Elements - According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception. | 06-23-2011 |
20120166761 | VECTOR CONFLICT INSTRUCTIONS - A processing core implemented on a semiconductor chip is described having first execution unit logic circuitry that includes first comparison circuitry to compare each element in a first input vector against every element of a second input vector. The processing core also has second execution logic circuitry that includes second comparison circuitry to compare a first input value against every data element of an input vector. | 06-28-2012 |
20140344553 | Gathering and Scattering Multiple Data Elements - According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception. | 11-20-2014 |
Jonathan C. Hall, Portland, OR US
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20120144089 | SCATTER/GATHER ACCESSING MULTIPLE CACHE LINES IN A SINGLE CACHE PORT - Methods and apparatus are disclosed for accessing multiple data cache lines for scatter/gather operations. Embodiment of apparatus may comprise address generation logic to generate an address from an index of a set of indices for each of a set of corresponding mask elements having a first value. Line or bank match ordering logic matches addresses in the same cache line or different banks, and orders an access sequence to permit a group of addresses in multiple cache lines and different banks. Address selection logic directs the group of addresses to corresponding different banks in a cache to access data elements in multiple cache lines corresponding to the group of addresses in a single access cycle. A disassembly/reassembly buffer orders the data elements according to their respective bank/register positions, and a gather/scatter finite state machine changes the values of corresponding mask elements from the first value to a second value. | 06-07-2012 |
20140095779 | PROCESSING MEMORY ACCESS INSTRUCTIONS THAT HAVE DUPLICATE MEMORY INDICES - A method of an aspect includes receiving an instruction indicating a first source packed memory indices, a second source packed data operation mask, and a destination storage location. Memory indices of the packed memory indices are compared with one another. One or more sets of duplicate memory indices are identified. Data corresponding to each set of duplicate memory indices is loaded only once. The loaded data corresponding to each set of duplicate memory indices is replicated for each of the duplicate memory indices in the set. A packed data result in the destination storage location in response to the instruction. The packed data result includes data elements from memory locations that are indicated by corresponding memory indices of the packed memory indices when not blocked by corresponding elements of the packed data operation mask. | 04-03-2014 |
20140181464 | COALESCING ADJACENT GATHER/SCATTER OPERATIONS - According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location. | 06-26-2014 |
20150052333 | Systems, Apparatuses, and Methods for Stride Pattern Gathering of Data Elements and Stride Pattern Scattering of Data Elements - Embodiments of systems, apparatuses, and methods for performing gather and scatter stride instruction in a computer processor are described. In some embodiments, the execution of a gather stride instruction causes a conditionally storage of strided data elements from memory into the destination register according to at least some of bit values of a writemask. | 02-19-2015 |
Jonathan Cannon Hall, Hillsboro, OR US
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20120254591 | SYSTEMS, APPARATUSES, AND METHODS FOR STRIDE PATTERN GATHERING OF DATA ELEMENTS AND STRIDE PATTERN SCATTERING OF DATA ELEMENTS - Embodiments of systems, apparatuses, and methods for performing gather and scatter stride instruction in a computer processor are described. In some embodiments, the execution of a gather stride instruction causes a conditionally storage of strided data elements from memory into the destination register according to at least some of bit values of a writemask. | 10-04-2012 |
20130305020 | VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF - A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams. | 11-14-2013 |
20140149724 | VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF - A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams. | 05-29-2014 |
M. Matthews Hall, Portland, OR US
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20080251746 | Electronically actuated valve system - An electronically actuated valve assembly for an internal combustion engine is disclosed, wherein the valve assembly comprises a valve stem, and a plurality of shape memory alloy segments in operative communication with the valve stem, wherein each shape memory alloy segment is individually actuatable, and wherein actuation of different shape memory alloy segments is configured to cause different valve lifts. | 10-16-2008 |
Robert Hall, Sherwood, OR US
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20100226612 | Optical receptacle and plug with simple structure - An optical receptacle ( | 09-09-2010 |
Ronald W. Hall, Corvallis, OR US
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20100192792 | METHOD OF PREDICTING A DRYING PARAMETER FOR A PRINTING PRESS - A method of predicting at least one drying parameter for a printing press includes estimating an amount and type of an ink to be deposited on a printing surface, determining at least one of: i) a type of the printing surface, ii) a thickness of the printing surface, and iii) a speed of the printing surface moving through the printing press, and calculating, via a controller associated with the dryer, the at least one drying parameter based at least on: i) the amount and the type of the ink to be deposited on the printing surface; ii) the type of the printing surface, iii) the thickness of the printing surface, and iv) the speed of the printing surface moving through the printing press. Also disclosed herein is a method of determining if the ink established on the printing surface is dry. | 08-05-2010 |
Ryan S. Hall, Keizer, OR US
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20140358298 | ALIGNMENT TOOL - In embodiments, one or more targets, each comprising one or more dots, may be permanently or removably affixed to one or more components of a mechanical system such as a bicycle. A computing device may capture a two-dimensional image of the one or more targets. The two-dimensional image may be processed and the location of the targets in three-dimensional space may be determined based at least in part on the processing. Based at least in part on the location of the targets in three-dimensional space, one or more adjustments to one or more of the components of the mechanical system may be identified, and instructions related to those adjustments may be provided to the user. In embodiments, the computing device may be a smartphone. In embodiments, the one or more components may be one or more of a bicycle frame, derailleur, and/or cassette. | 12-04-2014 |
Stephen H. Hall, Hillsboro, OR US
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20080308306 | SHIFTED SEGMENT LAYOUT FOR DIFFERENTIAL SIGNAL TRACES TO MITIGATE BUNDLE WEAVE EFFECT - An article of manufacture includes a circuit board and a pair of traces on or in the circuit board. The pair of traces includes a first trace and a second trace. The first trace includes a first segment and a second segment continuously joined to the first segment. The first segment coincides with a first longitudinal axis. The second trace includes a first segment that runs alongside the first segment of the first trace. The second trace also includes a second segment that runs alongside the second segment of the first trace. The second segment of the second trace is continuously joined to the first segment of the second trace. The second segment of the second trace coincides with the first longitudinal axis. | 12-18-2008 |
20090080832 | Quasi-waveguide printed circuit board structure - In some embodiments a channel is formed in printed circuit board material, the formed channel is plated to form at least two side walls of a quasi-waveguide, and printed circuit board material is laminated to the plated channel using thermoset adhesive. Other embodiments are described and claimed. | 03-26-2009 |
20100202118 | SHIFTED SEGMENT LAYOUT FOR DIFFERENTIAL SIGNAL TRACES TO MITIGATE BUNDLE WEAVE EFFECT - An article of manufacture includes a circuit board and a pair of traces on or in the circuit board. The pair of traces includes a first trace and a second trace. The first trace includes a first segment and a second segment continuously joined to the first segment. The first segment coincides with a first longitudinal axis. The second trace includes a first segment that runs alongside the first segment of the first trace. The second trace also includes a second segment that runs alongside the second segment of the first trace. The second segment of the second trace is continuously joined to the first segment of the second trace. The second segment of the second trace coincides with the first longitudinal axis. | 08-12-2010 |
Stephen H. Hall, Forest Grove, OR US
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20080224936 | Modular waveguide inteconnect - In some embodiments, an electronic device comprises a circuit board, an antenna structure on the circuit board, and a waveguide mounted on the circuit board above the antenna structure. Other embodiments may be described. | 09-18-2008 |
20080240266 | Arrangements for monitoring and controlling a transmission path - In one embodiment of the present disclosure, a method for improving communication between a transmitter and a receiver is disclosed. The method can include receiving a first signal having a first power level over a first path, receiving a second signal having a second power level over a second path wherein the first path is different than the second path. The method can compare the first power level with the second power and determine a difference between the first power level and the second power level. The method can also adjusting a parameter in the system to reduce the difference in power levels between the first and second signals compensating for interference cause by many sources. | 10-02-2008 |
20090002952 | Interference mitigation - In some embodiments, an electronic apparatus comprises a display assembly, a printed circuit board comprising a display driver integrated circuit, and at least one structure to alter a resonance frequency characteristic of at least one of the display assembly or the printed circuit board. Other embodiments may be disclosed. | 01-01-2009 |
20140181348 | CROSSTALK AWARE DECODING FOR A DATA BUS - Techniques for decoding encoded data are described herein. An example of a device in accordance with the present techniques includes a receiving signaling module coupled to a plurality of signal lines. The signaling module includes a receiver to receive a plurality of encoded line voltages or currents on the plurality of signal lines of a bus, wherein each one of the plurality of encoded line voltages corresponds to a weighted sum of data. The signaling module includes a comparator to determine the voltage level of each line at a unit interval and convert the voltage level to a digital value. The signaling module includes a lookup table correlating the digital value with a digital bit stream. | 06-26-2014 |
20140181357 | CROSSTALK AWARE ENCODING FOR A DATA BUS - Techniques for encoding data are described herein. An example of a device in accordance with the present techniques includes a signaling module coupled to a plurality of digital inputs. The signaling module is to encode data received at the plurality of digital inputs to generate encoded data. Based on the encoded data, the signaling module can drive line voltages on a plurality of signal lines of a bus. Each one of the plurality of line voltages corresponds to a weighted sum of the data received at the plurality of digital inputs. | 06-26-2014 |
20140181358 | CROSSTALK AWARE DECODING FOR A DATA BUS - Techniques for decoding encoded data are described herein. An example of a device in accordance with the present techniques includes a signaling module with a receiver, quantizer, and arithmetic circuit. The receiver receives a plurality of encoded line voltages or currents on a plurality of signal lines. The quantizer determines signal levels of each of the plurality of signal lines at a unit interval. The arithmetic circuit provides a plurality of digital output bits of the decoder based on the signal levels. Each one of the digital output bits is a mathematical combination of all of the signal levels. | 06-26-2014 |
Thomas Brett Hall, Portland, OR US
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20100198875 | INCREMENTAL CONCURRENT PROCESSING FOR EFFICIENT COMPUTATION OF HIGH-VOLUME LAYOUT DATA - Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, some embodiments can generate a template database which contains the unique templates in a set of templates. During operation, an embodiment can determine a set of templates for a layout. Next, the system can determine a processing schedule based on a spatially coherent ordering of the set of templates. Next, the system can process the templates according to the spatially coherent processing schedule. Processing templates in a spatially coherent order can ensure that the downstream processes in the concurrent work flow will be able to maximize concurrency, thereby improving overall performance of the system. | 08-05-2010 |
20130086535 | INCREMENTAL CONCURRENT PROCESSING FOR EFFICIENT COMPUTATION OF HIGH-VOLUME LAYOUT DATA - Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, some embodiments can generate a template database which contains the unique templates in a set of templates. During operation, an embodiment can determine a set of templates for a layout. Next, the system can determine a processing schedule based on a spatially coherent ordering of the set of templates. Next, the system can process the templates according to the spatially coherent processing schedule. Processing templates in a spatially coherent order can ensure that the downstream processes in the concurrent work flow will be able to maximize concurrency, thereby improving overall performance of the system. | 04-04-2013 |
20140189616 | INCREMENTAL CONCURRENT PROCESSING FOR EFFICIENT COMPUTATION OF HIGH-VOLUME LAYOUT DATA - Some embodiments of the present invention overcome I/O bottlenecks of an EDA work flow by keeping layout data distributed during handoffs among different processing stages. Specifically, some embodiments leverage a concurrent computation paradigm where data is propagated incrementally between stages, and where data processing among consecutive stages and the I/O between stages are executed concurrently. Specifically, different data processing stages can partition the layout data differently, and portions of the layout data that are not required by a data processing stage can be either passed-through or passed-around the data processing stage. | 07-03-2014 |