Patent application number | Description | Published |
20090193202 | MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE - A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface. | 07-30-2009 |
20110153932 | MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE - A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface. | 06-23-2011 |
20120020178 | MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE - A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface. | 01-26-2012 |
20120170399 | MULTI-COLUMN ADDRESSING MODE MEMORY SYSTEM INCLUDING AN INTEGRATED CIRCUIT MEMORY DEVICE - A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface. | 07-05-2012 |
Patent application number | Description | Published |
20100033306 | METHOD OF CONFIGURING RFID READER - A method of configuring an RFID reader includes (1) collecting information related to an operation environment of an RFID reader, and (2) configuring the RFID reader to operate in a mode that is selected for the operation environment of the RFID reader. | 02-11-2010 |
20100308973 | THERMALLY CONTROLLED DUTY CYCLE REGULATION IN AN RFID MODULE - A system and methods for measuring the temperature of an RFID reader module and inserting a delay in the RFID reader's duty cycle to prevent the RFID reader from initiating a thermal shutdown. The system and methods are self-adaptable, therefore incurring the benefit regardless of the design of the RFID reader host and its associated heat sink. The system and methods also provide for archiving the collected data and analyzing the data providing the ability to improve the design of the RFID reader host. | 12-09-2010 |
20110121075 | METHOD AND APPARATUS FOR AUGMENTING OPTICAL BARCODE SCANNER WITH RFID READER - An apparatus and method for augmenting an optical barcode scanner. The apparatus comprises an accessory module that includes an RFID reader, a body part attachable to the optical barcode scanner, and an interface connector for forming a communication link between the RFID reader and the optical barcode scanner when the interface connector is connected with the expansion port of the optical barcode scanner. | 05-26-2011 |
20110130085 | METHOD AND APPARATUS FOR IDENTIFYING READ ZONE OF RFID READER - An apparatus and method for identifying the read zone of an RFID reader. The apparatus includes a supporting sheet, a reader-position mark on the supporting sheet to indicate a recommended location to position an RFID reader, and a zone-boundary mark on the supporting sheet to indicate a read zone of the RFID reader with a predetermined field strength. | 06-02-2011 |
20120044112 | LOCAL AREA NETWORK ANTENNA FOR A MOBILE COMPUTING DEVICE - An antenna for a mobile device is described. The antenna includes a housing formed from a metal material. The housing functions as a ground plane for the antenna and an RF shield for at least one electronic component of the mobile device. An insulating material covers at least a portion of the housing. The antenna also includes a radiating element disposed on the insulating material. | 02-23-2012 |
20130113669 | ROTATING-POLARIZATION REFLECTOR-BACKED RFID LOOP ANTENNA APPARATUS AND METHOD - The present disclosure provides a rotating-polarization reflector-backed Radio Frequency Identification (RFID) loop antenna apparatus and method. The loop antenna apparatus and method provides high gain (i.e., maximizing read distances at lowest power), directionality (i.e., ability to focus on specific areas), orientation insensitivity (i.e., ability to read RFID tags in any direction or orientation) while occupying minimal volume in overhead configurations. In an exemplary embodiment, the loop antenna apparatus includes a reflector and a loop element with the reflector configured to reflect downward RF energy from the loop element. Antenna polarization is controlled by a feed location on the loop element and antenna pattern is controlled by the reflector. Thus, orientation insensitivity may be achieved without changing the antenna pattern by rotating the feed location and not the reflector. | 05-09-2013 |
20130169414 | METHOD AND APPARATUS FOR RADIO FREQUENCY IDENTIFICATION (RFID) DATA TRANSMISSION - A method and apparatus for obtaining data of a Radio Frequency Identification (RFID) tag in a virtual read zone of a non-RFID enabled device. The method comprises determining a location of the non-RFID enabled device, determining a virtual read zone of the non-RFID enabled device using at least the location of the non-RFID enabled device, identifying at least one fixed reader device having an RFID read zone that at least partially includes the virtual read zone, reading data of the RFID tag using the at least one fixed reader device, and transmitting the data of the RFID tag from the at least one fixed reader device to the non-RFID enabled device. | 07-04-2013 |
20130169415 | PORTABLE DATA TAG READER DEVICE, SYSTEM AND METHOD FOR IDENTIFYING A LOCATION OF A DATA TAG - A portable data tag method, device and system for identifying a location of a data tag. The method comprises reading the data tag by a portable data tag reader device; determining, by a processor in operative communication with the reader device, a location of the portable data tag reader device; determining, by the processor, a read zone of the portable data tag reader device, relative to the location of the portable data tag reader device; and determining, by the processor, the location of the data tag using the location of the portable data tag reader device and the read zone of the portable data tag reader device. | 07-04-2013 |
20130229262 | RADIO FREQUENCY IDENTIFICATION READER ANTENNA ARRANGEMENT WITH MULTIPLE LINEARLY-POLARIZED ELEMENTS - An antenna method and apparatus for a Radio Frequency Identification (RFID) reader includes an RFID reader, a plurality of radio ports of the RFID reader, and a plurality of linearly polarized antenna elements coupled to the radio ports, wherein the RFID reader directs the radio ports to sequentially communicatively connect only one antenna element at a time to the RFID reader such that only one antenna element is operable to transmit/receive at any instant in time. The antenna elements are mounted in an alternating vertically polarized and horizontally polarized configuration. | 09-05-2013 |
20140054378 | CO-LOCATED ANTENNA ARRANGEMENT - An antenna method and arrangement of co-located antennas for wireless communication, includes at least one first antenna having a reflector panel and at least one second antenna utilizing a ground plane, wherein the reflector panel and the ground plane are the same element of the arrangement. The first antenna can be a loop element parallel to the reflector panel and the second antenna can be a monopole element perpendicular to the reflector panel/ground plane. | 02-27-2014 |
20150060543 | PREVENTING PURCHASED MERCHANDISE FROM BEING LEFT AT A CHECKOUT COUNTER - A system and method to prevent merchandise from being left at a checkout counter includes a first step of entering a checkout area with a group of items having identification tags. A next step includes reading the tags of the items in the group. A next step includes associating the tagged items as a group. A next step includes detecting whether any tagged item is separated from the group. A next step includes generating an alert if any tagged item is separated from the group. | 03-05-2015 |
20150116088 | APPARATUS AND METHOD FOR PRODUCING AN APPROPRIATE QUANTITY OF RFID READS - An RFID reader configures each of a plurality of antennas operating in the RFID reader to operate in one of a first state and a second state, configures each of the plurality of antennas to operate in a first session and a second session and to operate in opposite states in the first session and the second session, and configures adjacent antennas or adjacent groups of antennas to operate in opposite states in the first session and the second session. During operation, each of the plurality of antennas is configured to read an RFID tag within a range of the antenna when a state of the RFID tag for the session in which the antenna is configured to operate matches the state in which the antenna is configured to operate and to switch the state of the RFID tag to the opposite state for each session. | 04-30-2015 |
Patent application number | Description | Published |
20110161618 | ASSIGNING EFFICIENTLY REFERENCED GLOBALLY UNIQUE IDENTIFIERS IN A MULTI-CORE ENVIRONMENT - A mechanism is provided in a multi-core environment for assigning a globally unique core identifier. A Power PC® processor unit (PPU) determines an index alias corresponding to a natural index to a location in local storage (LS) memory. A synergistic processor unit (SPU) corresponding to the PPU translates the natural index to a first address in a core's memory, as well as translates the index alias to a second address in the core's memory. Responsive to the second address exceeding a physical memory size, the load store unit of the SPU truncates the second address to a usable range of address space in systems that do not map an address space. The second address and the first address point to the same physical location in the core's memory. In addition, the aliasing using index aliases also preserves the ability to combine persistent indices with relative indices without creating holes in a relative index map. | 06-30-2011 |
20110161935 | METHOD FOR MANAGING HARDWARE RESOURCES WITHIN A SIMULTANEOUS MULTI-THREADED PROCESSING SYSTEM - A method for managing hardware resources and threads within a data processing system is disclosed. Compilation attributes of a function are collected during and after the compilation of the function. The pre-processing attributes of the function are also collected before the execution of the function. The collected attributes of the function are then analyzed, and a runtime configuration is assigned to the function based of the result of the attribute analysis. The runtime configuration may include, for example, the designation of the function to be executed under either a single-threaded mode or a simultaneous multi-threaded mode. During the execution of the function, real-time attributes of the function are being continuously collected. If necessary, the runtime configuration under which the function is being executed can be changed based on the real-time attributes collected during the execution of the function. | 06-30-2011 |
20120198469 | Method for Managing Hardware Resources Within a Simultaneous Multi-Threaded Processing System - A method for managing hardware resources and threads within a data processing system is disclosed. Compilation attributes of a function are collected during and after the compilation of the function. The pre-processing attributes of the function are also collected before the execution of the function. The collected attributes of the function are then analyzed, and a runtime configuration is assigned to the function based of the result of the attribute analysis. The runtime configuration may include, for example, the designation of the function to be executed under either a single-threaded mode or a simultaneous multi-threaded mode. During the execution of the function, real-time attributes of the function are being continuously collected. If necessary, the runtime configuration under which the function is being executed can be changed based on the real-time attributes collected during the execution of the function. | 08-02-2012 |
Patent application number | Description | Published |
20090157913 | Method for Toggling Non-Adjacent Channel Identifiers During DMA Double Buffering Operations - Disclosed are a method, a system and a computer program product for managing direct memory access (DMA) operations in a double buffering system. During direct memory access operations in a computer system, data is transferred from a source memory location to a destination memory location with minimal use of the computer's processing unit. Double buffering utilizes two separate memory buffers to perform simultaneous DMA operations. Prior to processing a DMA request each buffer in a double buffering system is assigned a channel identification (ID), or tag. When reading, writing, or polling status of data in a buffer, the tag identifies the buffer. A toggle factor is utilized to conveniently switch between each buffer in the double buffering system. Utilizing a toggle factor decreases latencies in DMA operations. | 06-18-2009 |
20100159875 | Telephone Handset Contact List Synchronization - A method comprises a first telephone handset selecting a second telephone handset as an approved contact exchange partner. The first telephone handset and the second telephone handset comprise contact information organized in a database. The first telephone handset establishes a telephone call between the first telephone handset and the second telephone handset. The first telephone handset receives contact update information from the second telephone handset in a first protocol. The first telephone handset synchronizes the contact update information with the contact information of the first telephone handset. | 06-24-2010 |
20110055531 | Synchronizing Commands and Dependencies in an Asynchronous Command Queue - Provided are techniques for the managing of command queue dependencies and command queue synchronization. Incoming commands are actively tracked through their dependency relationships. Command dependencies may be tracked across multiple lists, including a submission list and a completion list. Each command on the submission list is prepared for processing and ultimately submitted to command processing logic. Command completion processing is performed on each command on the completion list, including by not limited to removing dependencies from pending commands and possibly queuing pending commands for submission to the command processing logic. Also provided as features of a command queue are a standby barrier, an active barrier and a marker. Standby and active barriers are employed to synchronize and track commands through the command queue. Markers are employed to track commands through the command queue. | 03-03-2011 |
20110055839 | Multi-Core/Thread Work-Group Computation Scheduler - Execution units process commands from one or more command queues. Once a command is available on the queue, each unit participating in the execution of the command atomically decrements the command's work groups remaining counter by the work group reservation size and processes a corresponding number of work groups within a work group range. Once all work groups within a range are processed, an execution unit increments a work group processed counter. The unit that increments the work group processed counter to the value stored in a work groups to be executed counter signals completion of the command. Each execution unit that access a command also marks a work group seen counter. Once the work groups processed counter equals the work groups to be executed counter and the work group seen counter equals the number of execution units, the command may be removed or overwritten on the command queue. | 03-03-2011 |
20110161608 | METHOD TO CUSTOMIZE FUNCTION BEHAVIOR BASED ON CACHE AND SCHEDULING PARAMETERS OF A MEMORY ARGUMENT - Disclosed are a method, a system and a computer program product of operating a data processing system that can include or be coupled to multiple processor cores. In one or more embodiments, each of multiple memory objects can be populated with work items and can be associated with attributes that can include information which can be used to describe data of each memory object and/or which can be used to process data of each memory object. The attributes can be used to indicate one or more of a cache policy, a cache size, and a cache line size, among others. In one or more embodiments, the attributes can be used as a history of how each memory object is used. The attributes can be used to indicate cache history statistics (e.g., a hit rate, a miss rate, etc.). | 06-30-2011 |
20110161734 | PROCESS INTEGRITY IN A MULTIPLE PROCESSOR SYSTEM - Disclosed are a method, a system and a computer program product of operating a data processing system that can include or be coupled to multiple processor cores. In one or more embodiments, an error can be determined while two or more processor cores are processing a first group of two or more work items, and the error can be signaled to an application. The application can determine a state of progress of processing the two or more work items and at least one dependency from the state of progress. In one or more embodiments, a second group of two or more work items that are scheduled for processing can be unscheduled, in response to determining the error. In one or more embodiments, the application can process at least one work item that caused the error, and the second group of two or more work items can be rescheduled for processing. | 06-30-2011 |
20110161943 | METHOD TO DYNAMICALLY DISTRIBUTE A MULTI-DIMENSIONAL WORK SET ACROSS A MULTI-CORE SYSTEM - A method provides efficient dispatch/completion of an N Dimensional (ND) Range command in a data processing system (DPS). The method comprises: a compiler generating one or more commands from received program instructions; ND Range work processing (WP) logic determining when a command generated by the compiler will be implemented over an ND configuration of operands, where N is greater than one (1); automatically decomposing the ND configuration of operands into a one (1) dimension (1D) work element comprising P sequentially ordered work items that each represent one of the operands; placing the 1D work element within a command queue of the DPS; enabling sequential dispatching of 1D work items in ordered sequence from to one or more processing units; and generating an ND Range output by mapping the 1D work output result to an ND position corresponding to an original location of the operand represented by the 1D work item. | 06-30-2011 |
20110161970 | METHOD TO REDUCE QUEUE SYNCHRONIZATION OF MULTIPLE WORK ITEMS IN A SYSTEM WITH HIGH MEMORY LATENCY BETWEEN COMPUTE NODES - Disclosed are a method, a system and a computer program product of operating a data processing system that can include or be coupled to multiple processor cores. The multiple processor cores can be coupled to a memory that can include multiple priority queues associated with multiple respective priorities and store multiple work items. Work items stored in the multiple priority queues can be associated with a bit mask which is associated with a respective priority queue and can be routed to respective groups of one or more processors based on the associated bit mask. In one or more embodiments, at least two groups of processor cores can include at least one processor core that is common to both of the at least two groups of processor cores. | 06-30-2011 |
20110161975 | REDUCING CROSS QUEUE SYNCHRONIZATION ON SYSTEMS WITH LOW MEMORY LATENCY ACROSS DISTRIBUTED PROCESSING NODES - A method for efficient dispatch/completion of a work element within a multi-node data processing system. The method comprises: selecting specific processing units from among the processing nodes to complete execution of a work element that has multiple individual work items that may be independently executed by different ones of the processing units; generating an allocated processor unit (APU) bit mask that identifies at least one of the processing units that has been selected; placing the work element in a first entry of a global command queue (GCQ); associating the APU mask with the work element in the GCQ; and responsive to receipt at the GCQ of work requests from each of the multiple processing nodes or the processing units, enabling only the selected specific ones of the processing nodes or the processing units to be able to retrieve work from the work element in the GCQ. | 06-30-2011 |
20110161976 | METHOD TO REDUCE QUEUE SYNCHRONIZATION OF MULTIPLE WORK ITEMS IN A SYSTEM WITH HIGH MEMORY LATENCY BETWEEN PROCESSING NODES - A method efficiently dispatches/completes a work element within a multi-node, data processing system that has a global command queue (GCQ) and at least one high latency node. The method comprises: at the high latency processor node, work scheduling logic establishing a local command/work queue (LCQ) in which multiple work items for execution by local processing units can be staged prior to execution; a first local processing unit retrieving via a work request a larger chunk size of work than can be completed in a normal work completion/execution cycle by the local processing unit; storing the larger chunk size of work retrieved in a local command/work queue (LCQ); enabling the first local processing unit to locally schedule and complete portions of the work stored within the LCQ; and transmitting a next work request to the GCQ only when all the work within the LCQ has been dispatched by the local processing units. | 06-30-2011 |
20110191785 | Terminating An Accelerator Application Program In A Hybrid Computing Environment - Terminating an accelerator application program in a hybrid computing environment that includes a host computer having a host computer architecture and an accelerator having an accelerator architecture, where the host computer and the accelerator are adapted to one another for data communications by a system level message passing module (‘SLMPM’), and terminating an accelerator application program in a hybrid computing environment includes receiving, by the SLMPM from a host application executing on the host computer, a request to terminate an accelerator application program executing on the accelerator; terminating, by the SLMPM, execution of the accelerator application program; returning, by the SLMPM to the host application, a signal indicating that execution of the accelerator application program was terminated; and performing, by the SLMPM, a cleanup of the execution environment associated with the terminated accelerator application program. | 08-04-2011 |
20120221836 | Synchronizing Commands and Dependencies in an Asynchronous Command Queue - Provided are techniques for the managing of command queue dependencies and command queue synchronization. Incoming commands are actively tracked through their dependency relationships. Command dependencies may be tracked across multiple lists, including a submission list and a completion list. Each command on the submission list is prepared for processing and ultimately submitted to command processing logic. Command completion processing is performed on each command on the completion list, including by not limited to removing dependencies from pending commands and possibly queuing pending commands for submission to the command processing logic. Also provided as features of a command queue are a standby barrier, an active barrier and a marker. Standby and active barriers are employed to synchronize and track commands through the command queue. Markers are employed to track commands through the command queue. | 08-30-2012 |
20130013897 | METHOD TO DYNAMICALLY DISTRIBUTE A MULTI-DIMENSIONAL WORK SET ACROSS A MULTI-CORE SYSTEM - A method provides efficient dispatch/completion of an N Dimensional (ND) Range command in a data processing system (DPS). The method comprises: a compiler generating one or more commands from received program instructions; ND Range work processing (WP) logic determining when a command generated by the compiler will be implemented over an ND configuration of operands, where N is greater than one (1); automatically decomposing the ND configuration of operands into a one (1) dimension (1D) work element comprising P sequentially ordered work items that each represent one of the operands; placing the 1D work element within a command queue of the DPS; enabling sequential dispatching of 1D work items in ordered sequence from to one or more processing units; and generating an ND Range output by mapping the 1D work output result to an ND position corresponding to an original location of the operand represented by the 1D work item. | 01-10-2013 |
20130014124 | REDUCING CROSS QUEUE SYNCHRONIZATION ON SYSTEMS WITH LOW MEMORY LATENCY ACROSS DISTRIBUTED PROCESSING NODES - A method for efficient dispatch/completion of a work element within a multi-node data processing system. The method comprises: selecting specific processing units from among the processing nodes to complete execution of a work element that has multiple individual work items that may be independently executed by different ones of the processing units; generating an allocated processor unit (APU) bit mask that identifies at least one of the processing units that has been selected; placing the work element in a first entry of a global command queue (GCQ); associating the APU mask with the work element in the GCQ; and responsive to receipt at the GCQ of work requests from each of the multiple processing nodes or the processing units, enabling only the selected specific ones of the processing nodes or the processing units to be able to retrieve work from the work element in the GCQ. | 01-10-2013 |
20130254776 | METHOD TO REDUCE QUEUE SYNCHRONIZATION OF MULTIPLE WORK ITEMS IN A SYSTEM WITH HIGH MEMORY LATENCY BETWEEN PROCESSING NODES - A method efficiently dispatches/completes a work element within a multi-node, data processing system that has a global command queue (GCQ) and at least one high latency node. The method comprises: at the high latency processor node, work scheduling logic establishing a local command/work queue (LCQ) in which multiple work items for execution by local processing units can be staged prior to execution; a first local processing unit retrieving via a work request a larger chunk size of work than can be completed in a normal work completion/execution cycle by the local processing unit; storing the larger chunk size of work retrieved in a local command/work queue (LCQ); enabling the first local processing unit to locally schedule and complete portions of the work stored within the LCQ; and transmitting a next work request to the GCQ only when all the work within the LCQ has been dispatched by the local processing units. | 09-26-2013 |
Patent application number | Description | Published |
20080229007 | Enhancements to an XDR Memory Controller to Allow for Conversion to DDR2 - A memory control apparatus includes a data stream format converter and a physical layer converter. The data stream format converter is configured to convert an incoming data stream that has a data stream format corresponding to a first memory type into a format-converted data stream that has a data stream format corresponding to a second memory type. The second memory type is different from the first memory type. The physical layer converter is configured to convert the format-converted data stream into a physical-layer-converted data stream that has at least one physical parameter corresponding to the second memory type. The format-converted data stream has at least one physical parameter corresponding to the first memory type. | 09-18-2008 |
20100180154 | Built In Self-Test of Memory Stressor - A method and system for generating addresses in a memory card built in self-test (MCBIST) for testing memory devices. The method includes receiving a MCBIST command and determining an addressing mode of the MCBIST command. Sequential addresses are generated and modified in response to the addressing mode being a stress test mode. The modifying includes swapping bits in a sequential address with other bits in the sequential address to target selected portions of a memory. The modified sequential addresses are output to the memory to be utilized in a MCBIST stress test of the memory. | 07-15-2010 |
20130179720 | MULTIPLE PROCESSOR DELAYED EXECUTION - A first first-in-first-out (FIFO) memory may receive first processor input from a first processor group that includes a first processor. The first processor group is configured to execute program code based on the first processor input that includes a set of input signals, a clock signal, and corresponding data. The first FIFO may store the first processor input and may output the first processor input to a second FIFO memory and to a second processor according to a first delay. The second FIFO memory may store the first processor input and may output the first processor input to a third processor according to a second delay. The second processor may execute at least a first portion of the program code and the third processor may execute at least a second portion of the program code responsive to the first processor input. | 07-11-2013 |
20140195777 | VARIABLE DEPTH INSTRUCTION FIFOS TO IMPLEMENT SIMD ARCHITECTURE - In a particular embodiment, a method may include creating a plurality of variable depth instruction FIFOs and a plurality of data caches from a plurality of caches corresponding to a plurality of processors, where the plurality of caches and the plurality of processors correspond to MIMD architecture. The method may also include configuring the plurality of variable depth instruction FIFOs to implement SIMD architecture. The method may also include configuring the plurality of variable depth instruction FIFOs for at least one of SIMD operation, SIMD operation with staging, or RC-SIMD operation. | 07-10-2014 |
Patent application number | Description | Published |
20080307184 | MEMORY CONTROLLER OPERATING IN A SYSTEM WITH A VARIABLE SYSTEM CLOCK - The present invention generally relates to memory controllers operating in a system containing a variable system clock. The memory controller may exchange data with a processor operating at a variable processor clock frequency. However the memory controller may perform memory accesses at a constant memory clock frequency. Asynchronous buffers may be provided to transfer data across the variable and constant clock domains. To prevent read buffer overflow while switching to a lower processor clock frequency, the memory controller may quiesce the memory sequencers and pace read data from the sequencers at a slower rate. To prevent write data under runs, the memory controller's data flow logic may perform handshaking to ensure that write data is completely received in the buffer before performing a write access. | 12-11-2008 |
20090119442 | Managing Write-to-Read Turnarounds in an Early Read After Write Memory System - Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank. | 05-07-2009 |
20090327562 | Implementing Bus Interface Calibration for Enhanced Bus Interface Initialization Time - A method and apparatus are provided for implementing bus interface calibration to improve bus interface initialization time in a system. Bus interface calibration is performed and average calibration values are saved. At bus interface initialization time, checking for saved calibration values is performed. The saved calibration values are used and tested. When the saved calibration values pass the test, then the saved calibration values are used for system operation without performing any training steps. | 12-31-2009 |
Patent application number | Description | Published |
20120064746 | METHOD AND APPARATUS FOR TRANSLATING COUPLING FEATURES OF A PLUG-IN UNIT - Embodiments of a plug-in unit for an electrical enclosure are disclosed. The plug-in unit includes at least one stab configured to engage a bus, a stab shaft coupled with a base of the at least one stab, and a stab translation mechanism configured to translate the stab shaft such that the at least one stab translates from a retracted position to an extended position. | 03-15-2012 |
20150129550 | CIRCUIT BREAKER GAS DIRECTING SYSTEM - A gas directing system for a circuit breaker is disclosed. The system includes an insulative housing that fits over vents that convey hot gases upon operation of the circuit breaker. The housing has phase partitions that separate phase sections from one another, and transverse partitions that separate a venting sections for each phase from terminal sections. Gas diverting structures are provided in the venting sections that redirect hot gases towards apertures through which the gases vent. The overall structure may be much lower profile than previous design spacing requirements. | 05-14-2015 |
20150129552 | CIRCUIT BREAKER POSITION ADJUSTMENT SYSTEM - A system for adjusting the position of a circuit breaker is provided. The system allows for translation of the circuit breaker with respect to a support base and interfacing mechanisms, such as those that serve to switch the circuit breaker between its operative states. Adjustment is afforded by an adjustment plate fitted to the support base and that moves with the circuit breaker. Slots through the support base allow for movement of the plate and circuit breaker. A threaded member allows for continuous movement of the plate and circuit breaker for accurate positioning. | 05-14-2015 |
20150129554 | CIRCUIT BREAKER OPERATING SYSTEM - An operating system for a circuit breaker includes a bail and a base that supports the circuit breaker and the bail. The bail extends around the circuit breaker and is pivotally attached to the base, such as by snap engagement. The bail and the base are made of an insulative plastic material such that the circuit breaker may vent hot gases, charged particles, plasma and the like without transferring charge to the operating system components. Additional features may be molded into the parts, such as supports and operators for auxiliary switches. | 05-14-2015 |
Patent application number | Description | Published |
20080217974 | Child Motion Device - A child motion device includes a frame that provides a structural support relative to a reference surface and that includes an arm pivotably coupled to the structural support. A child supporting device is coupled to the arm and spaced from the reference surface by the frame. A drive system is configured to move the arm such that the child supporting device reciprocates along a motion path at a frequency within a range from about 0.37 Hz to about 0.62 Hz. In some cases, a further drive system is configured to oscillate the child supporting device generally along the axis of rotation at a frequency in a range from about 2.85 Hz to about 3.15 Hz. | 09-11-2008 |
20080238163 | Seat Support Structure for a Child Motion Device - A child motion device has a frame assembly configured to rest on a floor surface, a drive system defining a generally vertical axis of rotation, and a support arm supported above the floor surface by the frame assembly. The support arm is cantilevered from near the axis of rotation and has a driven end coupled to the drive system, which pivotally reciprocates the support arm through a partial orbit around the axis of rotation, A seat holder is carried by the support arm spaced from the driven end and a seat is supported by the seat holder. The seat and seat holder are constructed to permit the seat to be removed from the seat holder. The seat is usable as a seat when removed from the seat holder and can be positioned on the seat holder in more than one optional seat facing orientation. | 10-02-2008 |
20090170618 | Child Motion Device - A child motion device has a frame assembly configured to rest on a floor surface. The device also has a drive system that defines a generally vertical axis of rotation. An arm extends from part of the device and is cantilevered from the axis of rotation. The arm is supported above the floor surface and has a driven end coupled to and movable by the drive system and a distal end opposite the driven end. The drive system is configured to pivotally reciprocate the arm through a partial orbit around the axis of rotation. A child seat is supported on the distal end of the support arm. | 07-02-2009 |
20100127539 | Seat Support Structure for a Child Motion Device - A child motion device has a frame assembly configured to rest on a floor surface, a drive system defining a generally vertical axis of rotation, and a support arm supported above the floor surface by the frame assembly. The support arm is cantilevered from near the axis of rotation and has a driven end coupled to the drive system, which pivotally reciprocates the support arm through a partial orbit around the axis of rotation. A seat holder is carried by the support arm spaced from the driven end and a seat is supported by the seat holder. The seat and seat holder are constructed to permit the seat to be removed from the seat holder. The seat is usable as a seat when removed from the seat holder and can be positioned on the seat holder in more than one optional seat facing orientation. | 05-27-2010 |
20130318709 | Infant Supporting Apparatus - An infant supporting apparatus includes a base frame, a support frame and a resting support. The base frame includes a first and a second leg frame portion pivotally connected with each other about a first pivot axis, wherein the first and second leg frame portions have foot portions. The support frame is assembled with the base frame, and includes a first and a second support frame portion pivotally connected with each other about a second pivot axis spaced apart from the first pivot axis, the first and second pivot axes being vertically aligned with each other. The resting support is suspended from the first and second support frames for receiving the placement of a child. | 12-05-2013 |
20130326808 | Infant Playpen Apparatus Provided with Utility Accessories - An infant playpen apparatus includes a playpen frame having two opposite side frame portions, two rail structures respectively affixed with the two side frame portions, a support platform operable to detachably assemble with the rail structures, and two coupling structures connected with the support platform and operable to respectively assemble with the rail structures. At least one of the coupling structures includes a latch that can lock an assembly of the support platform with the rail structure, and unlock the assembly of the support platform with the rail structure for removing the support assembly from the rail structure. The playpen apparatus can further include a m bassinet held with the playpen frame. The support platform can slide along the rail structures between a first position where the support platform substantially uncovers the bassinet, and a second position where the support platform lies above and substantially overlaps with the bassinet. | 12-12-2013 |
20140191173 | Accessories Suitable for Use with an Infant Playpen and Mount Assembly for Installing the Same - A mount assembly includes a playpen frame, a support frame that can provide support for a bassinet in the playpen frame, and multiple bar segments to provide support for a utility accessory positioned side-by-side relative to the bassinet. The playpen frame includes two first upper side rail assemblies each having a fixed wall, and a second upper side rail assembly connected with the two first upper side rail assemblies. The support frame includes two connectors operable to respectively attach to and detach from the fixed walls. Each connector is formed to include a socket. The two connectors can attach to the fixed walls respectively near a middle of the two first upper side rail assemblies. The bar segments are mountable to the playpen frame, one of the bar segments once mounted to the playpen frame having an end portion resting in contact with the socket of one connector. | 07-10-2014 |
20150047122 | INFANT PLAYPEN CAPABLE OF RECEIVING THE INSTALLATION OF MULTIPLE REMOVABLE ACCESSORIES - An infant playpen includes a plurality of upright legs, and a first and a second upper side rail assembly supported by the upright legs. Each of the first and a second upper side rail assembly includes at least one elongated segment having an outer surface, and a plurality of positioning regions are defined on the outer surfaces of the elongated segments, each of the positioning regions being configured to locate a connection of a removable accessory on the infant playpen. An infant care system is also disclosed, which includes the infant playpen and a removable accessory installed thereon. One selected positioning region of the first upper side rail assembly can be received in a housing of the removable accessory, and a locking part of the removable accessory is displaced to a locked position that retains the selected positioning region in the housing. | 02-19-2015 |
20150173523 | INFANT CARE APPARATUS - An infant care apparatus includes a standing frame, and an infant resting support connected with the support frame and having a plurality of bearing surfaces. The infant resting support is rotatable relative to the standing frame to position any of the bearing surfaces facing upward for receiving a child thereon, and the infant resting support is further slidable vertically relative to the standing frame to adjust a height of the infant resting support. | 06-25-2015 |
20150216321 | Infant Supporting Apparatus - An infant supporting apparatus includes a leg frame defining a clearance and having foot portions configured to stand on a ground surface, a support frame assembled with the leg frame above the foot portions, and an infant resting support for receiving the placement of a child, the infant resting support being suspended from the support frame above the clearance. The infant supporting apparatus has a configuration of use in which the infant supporting apparatus has the leg frame standing on a ground adjacent to a play yard that is received at least partially through the clearance, the infant resting support being suspended from above the play yard and the infant supporting apparatus being attached with the play yard. Moreover, the infant supporting apparatus can be independently used as a standalone device separate from the play yard. | 08-06-2015 |
20150250330 | Child Motion Apparatus - A child motion apparatus includes a base, a seat arranged above the base, and an upright column disposed below the seat. The seat includes a bottom frame segment and a seatback frame segment, the bottom frame segment having a front and a rear end, the seatback frame segment being pivotally connected with the rear end of the bottom frame segment. The upright column pivotally supports the seat above the base, and is connected with the bottom frame segment at a location between the front end and the rear end thereof. | 09-10-2015 |