Patent application number | Description | Published |
20140064485 | METHOD FOR REAL-TIME COMPOSITING OF ENCRYPTED VIDEO STREAMS WITHOUT DECRYPTION - A system, method and device for real-time compositing of encrypted video streams without having to decrypt each video stream is disclosed herein. A shared encryption key is derived to encrypt multiple incoming video streams to an encrypted master video stream, while retaining full interoperability with popular incumbent video encryption standards. Compositing video is then possible without having to decrypt the master video stream, thereby preserving the security of the copyrighted material. The invention preferably genlocks a digital video source to a master video stream. | 03-06-2014 |
20140082506 | SYSTEMS AND METHODS FOR WIDGET RENDERING AND SHARING ON A PERSONAL ELECTRONIC DEVICE - Systems and methods for providing, sharing, storing and playing widgets and associated media content on a personal audiovisual device, such as a digital photo frame, are described. In one implementation, widgets may be selected by a user for rendering based on capabilities of a user's device, with the widgets then provided to the device for playback. Digital content such as audio files, images, and/or video may be rendered in conjunction with playback of the widget. Widgets may be shared between users so as to facilitate sharing of media content. | 03-20-2014 |
20140136847 | SECURITY AND AUTHENTICATION SYSTEMS AND METHODS FOR PERSONALIZED PORTABLE DEVICES AND ASSOCIATED SYSTEMS - Systems and methods for client authentication and verification in a distributed client-server system are described. An authentication and verification system may include a plurality of client devices containing private keys, a first server configured to interface with the plurality of client devices, and a second, secure server configured to interface with the first server and store public keys associated with the private keys on the client devices. A method is further described for verifying client devices in conjunction with the first and second servers. The first server may contain secure tokens that can be decrypted in conjunction with the authentication and verification method. | 05-15-2014 |
20140294244 | SYSTEMS AND METHODS FOR GESTURE RECOGNITION FOR INPUT DEVICE APPLICATIONS - Systems and methods for gesture recognition for input device applications are described. In one embodiment, a system for gesture recognition includes a pair of IR LED emitters, an imaging module such as a camera or other imaging device, an LED emitter control module and a processing module. The IR LEDs generate IR light to highlight a target from one or more angles, and the received images are processed to identify target position and/or motion to provide output data based on the determined target position and/or motion. | 10-02-2014 |
20140347292 | TOUCHSCREEN WITH A LIGHT MODULATOR - A device with a touchscreen with a light modulator is disclosed herein. The device transitions from a netbook mode to a touchscreen mode. The device comprises a main unit and a touchscreen unit with a transparent display. The touchscreen unit is preferably separated from the main unit when in a netbook mode, and the touchscreen unit communicates wirelessly with the main unit. The touchscreen unit preferably has an outer screen display surface and an inner screen display surface on each side of a light modulating unit. The main unit preferably has a main unit display. | 11-27-2014 |
20150040118 | SYSTEM AND METHOD FOR AUTOMATICALLY UPDATING THE SOFTWARE OF A NETWORKED PERSONAL AUDIOVISUAL DEVICE - A method for automatically updating software executed by an electronic device is disclosed herein. The method includes receiving, at the electronic device, an update indication from a server that updated software is available for the electronic device. The method further includes modifying, in response to the update indication, a boot state of the electronic device and initiating operation of the electronic device in an update mode. The updated software is received, at the electronic device, during operation in the update mode. The method further includes initiating, upon determining the updated software has been correctly received, operation of the electronic device in a normal mode. | 02-05-2015 |
Patent application number | Description | Published |
20130275213 | SOCIAL MARKETPLACE APPARATUS AND METHOD - A system, method, and computer-readable storage medium configured to enable consumers to associate with retail merchants. Product information is received from a user computing device. The product information is matched with promotions and friends that want the product in their wish lists. The user is informed of the promotions and friends, and offered a myriad of options to facilitate product-related transactions with merchants. | 10-17-2013 |
20140358788 | Method for Receiving an Electronic Receipt of an Electronic Payment Transaction Into a Mobile Device - According to one embodiment of the present disclosure, there is provided a method for receiving an electronic receipt of an electronic payment transaction into a mobile device, the method comprising: storing, into an installed application in the mobile device used to perform the electronic payment transaction, a unique transaction identity issued on the electronic payment transaction; generating, in a server, an electronic receipt issued on the electronic payment transaction; verifying that the electronic receipt matches against the unique transaction identity stored in the installed application; and receiving the electronic receipt into the mobile device in response to the verifying step determining that the electronic receipt matches against the unique transaction identity stored in the installed application. Also provided is a mobile device for receiving an electronic receipt of an electronic payment transaction and a system for receiving an electronic receipt of an electronic payment transaction into a mobile device. | 12-04-2014 |
20140365370 | SYSTEM AND METHOD OF CONDUCTING AN AUTHENTICATION TRANSACTION - A system and method of conducting an authentication transaction; and a near field communication (NFC) enabled mobile device for conducting the authentication transaction. The method includes the steps of: storing data associated with one or more authentication certificates in a secure element of the NFC enabled mobile device; sending the data associated with the one or more authentication certificates from the NFC enabled mobile device to a server via a NFC enabled transceiver; verifying the authenticity of the one or more authentication certificates at the server; and upon successful authentication, sending transaction data from the server to the NFC enabled mobile device via the NFC enabled transceiver. | 12-11-2014 |
20150073990 | ELECTRONIC TRANSACTION METHOD - Disclosed herein is a method of transferring information in an electronic transaction between a first entity and a second entity. The method comprises: sending, by a first system | 03-12-2015 |
20150073999 | METHOD AND SYSTEM FOR CONDUCTING A PAYMENT TRANSACTION AND CORRESPONDING DEVICES - A method includes generating a token at a server device and transmitting the token from the server device to a payer device, the token corresponding to a payment account; receiving the token at the payer device and transmitting the token from the payer device to a payee device via a short-range wireless communication protocol; receiving the token at the payee device and transmitting the token with transaction data from the payee device to the server device, the transaction data corresponding to the payment transaction; and receiving the token with the transaction data at the server device and conducting the payment transaction at the server device using the transaction data and the payment account corresponding to the token. | 03-12-2015 |
20150213419 | METHOD AND SYSTEM FOR FACILITATING MICROPAYMENTS IN A FINANCIAL TRANSACTION SYSTEM - A system for processing accounts includes a database configured to store a plurality of accounts, the accounts including a consumer account associated with a consumer and a plurality of merchant accounts including a transacting merchant account associated with a merchant, wherein at least one account includes an amount of a virtual currency associated with the account. The system further includes a processor configured to process a financial transaction, wherein the transaction includes the consumer and the merchant, is for a specified amount of virtual currency, and processing the transaction includes transferring the specified amount of virtual currency from the consumer account to the transacting merchant account. The processor is further configured to process the at least one account, wherein processing the at least one account includes converting the associated amount of virtual currency to or from a real currency when the at least one account meets a predetermined criteria. | 07-30-2015 |
20160005009 | METHOD FOR CONDUCTING A TRANSACTION - A method for conducting a transaction between a merchant and a customer, a merchant device, and a computer storage medium for instructing a computing device to execute a method for conducting a transaction between a merchant and a customer are disclosed. The method includes establishing a secure wireless connection between a merchant device and a customer device, real-time synchronizing, via the secure connection, a shopping cart of the customer between the merchant and the customer devices, determining, via the secure connection, at least one payment option for checking out the shopping cart, and processing, at a transaction processing device, the payment based on a selected payment option out of the at least one payment option. | 01-07-2016 |
Patent application number | Description | Published |
20110224565 | METHOD OF PREDICTING ACUTE CARDIOPULMONARY EVENTS AND SURVIVABILITY OF A PATIENT - According to embodiments of the invention, there is provided a method of producing an artificial neural network capable of predicting the survivability of a patient, the method including: storing in an electronic database patient health data, the patient health data comprising a plurality of sets of data, each set having at least one of a first parameter relating to heart rate variability data and a second parameter relating to vital sign data, each set further having a third parameter relating to patient survivability; providing a network of nodes interconnected to form an artificial neural network, the nodes comprising a plurality of artificial neurons, each artificial neuron having at least one input with an associated weight; and training the artificial neural network using the patient health data such that the associated weight of the at least one input of each artificial neuron of the plurality of artificial neurons is adjusted in response to respective first, second and third parameters of different sets of data from the patient health data, such that the artificial neural network is trained to produce a prediction on the survivability of a patient. | 09-15-2011 |
20130237776 | METHOD OF PREDICTING ACUTE CARDIOPULMONARY EVENTS AND SURVIVABILITY OF A PATIENT - A method of producing an artificial neural network capable of predicting the survivability of a patient, including: storing in an electronic database patient health data comprising a plurality of sets of data, each set having at least one of a first parameter relating to heart rate variability data and a second parameter relating to vital sign data, each set further having a third parameter relating to patient survivability; providing a network of nodes interconnected to form an artificial neural network, the nodes comprising a plurality of artificial neurons, each artificial neuron having at least one input with an associated weight; and training the artificial neural network using the patient health data such that the associated weight of the at least one input of each artificial neuron is adjusted in response to respective first, second and third parameters of different sets of data from the patient health data. | 09-12-2013 |
20140187988 | METHOD OF PREDICTING ACUTE CARDIOPULMONARY EVENTS AND SURVIVABILITY OF A PATIENT - A method of producing an artificial neural network capable of predicting the survivability of a patient, including: storing in an electronic database patient health data comprising a plurality of sets of data, each set having at least one of a first parameter relating to heart rate variability data and a second parameter relating to vital sign data, each set further having a third parameter relating to patient survivability; providing a network of nodes interconnected to form an artificial neural network, the nodes comprising a plurality of artificial neurons, each artificial neuron having at least one input with an associated weight; and training the artificial neural network using the patient health data such that the associated weight of the at least one input of each artificial neuron is adjusted in response to respective first, second and third parameters of different sets of data from the patient health data. | 07-03-2014 |
20140257063 | METHOD OF PREDICTING ACUTE CARDIOPULMONARY EVENTS AND SURVIVABILITY OF A PATIENT - A method of producing an artificial neural network capable of predicting the survivability of a patient, including: storing in an electronic database patient health data comprising a plurality of sets of data, each set having at least one of a first parameter relating to heart rate variability data and a second parameter relating to vital sign data, each set further having a third parameter relating to patient survivability; providing a network of nodes interconnected to form an artificial neural network, the nodes comprising a plurality of artificial neurons, each artificial neuron having at least one input with an associated weight; and training the artificial neural network using the patient health data such that the associated weight of the at least one input of each artificial neuron is adjusted in response to respective first, second and third parameters of different sets of data from the patient health data. | 09-11-2014 |
20150150468 | SYSTEM AND METHOD FOR PREDICTING ACUTE CARDIOPULMONARY EVENTS AND SURVIVABILITY OF A PATIENT - A method of producing an artificial neural network capable of predicting the survivability of a patient, including: storing in an electronic database patient health data comprising a plurality of sets of data, each set having at least one of a first parameter relating to heart rate variability data and a second parameter relating to vital sign data, each set further having a third parameter relating to patient survivability; providing a network of nodes interconnected to form an artificial neural network, the nodes comprising a plurality of artificial neurons, each artificial neuron having at least one input with an associated weight; and training the artificial neural network using the patient health data such that the associated weight of the at least one input of each artificial neuron is adjusted in response to respective first, second and third parameters of different sets of data from the patient health data. | 06-04-2015 |
20150223759 | PREDICTING ACUTE CARDIOPULMONARY EVENTS AND SURVIVABILITY OF A PATIENT - A method of predicting survivability of a patient. The method includes storing in an electronic database patient health data comprising a plurality of sets of data, each set having a first parameter relating to heart rate variability data including at least one of ST segment elevation and depression, a second parameter relating to vital sign data, and a third parameter relating to patient survivability; providing a network of nodes interconnected to form an artificial neural network, the nodes comprising a plurality of neurons, each having at least one input with an associated weight; and training the neural network using the patient health data such that the associated weight of the at least one input of each neuron is adjusted in response to respective first, second and third parameters of different sets of data from the patient health data, such that the neural network is trained to produce a prediction on the survivability of a patient within the next 72 hours. | 08-13-2015 |
Patent application number | Description | Published |
20090028240 | Encoder, Decoder, Method for Encoding/Decoding, Computer Readable Media and Computer Program Elements - An encoder for encoding a first digital signal representative for a first channel and a second digital signal representative for a second channel is described. The encoder comprises cascaded intra-channel prediction elements for compressing the first digital signal and the second digital signal based on intra-channel correlation and an inter-channel prediction element for compressing the first digital signal and the second digital signal based on inter-channel correlation. | 01-29-2009 |
20100023575 | PREDICTOR - A Predictor is described which is based on a modified RLS (recursive least squares) algorithm. The modifications prevent divergence and accuracy problems when fixed point implementation is used. | 01-28-2010 |
20110046945 | METHOD AND DEVICE OF BITRATE DISTRIBUTION/TRUNCATION FOR SCALABLE AUDIO CODING - Embodiments of the invention provides a method and device for assigning bitrates to a plurality of channels in a scalable audio encoding/truncation process. Different bitrates are assigned to different channels in the scalable audio encoding/truncation process. | 02-24-2011 |
20120102035 | Data Embedding Methods, Embedded Data Extraction Methods, Truncation Methods, Data Embedding Devices, Embedded Data Extraction Devices And Truncation Devices - In an embodiment, a data embedding method may be provided. The data embedding method may include inputting data to be encoded and data to be embedded; grouping the data to be encoded into a first set and a second set, based on an entropy of the data to be encoded; and embedding the data to be embedded into the data to be encoded by replacing a pre-determined part of the second set with the data to be encoded so that the first set remains free of data to be embedded. | 04-26-2012 |
Patent application number | Description | Published |
20120300531 | Current Writing Circuit for a Resistive Memory Cell Arrangement - A current writing circuit for a resistive memory cell arrangement is provided. The current writing circuit comprises a first current source; a first reference potential terminal; a first switch configured to switch between the first current source and the first reference potential terminal during a write operation; a second current source; a second reference potential terminal; and a second switch configured to switch between the second reference potential terminal when the first switch is switched to the first current source, and the second current source when the first switch is switched to the first reference potential terminal, during the write operation, wherein the first current source and the second current source are of the same polarity. Further embodiments relate to a memory cell arrangement and a method of writing into a target resistive memory cell of a resistive memory cell arrangement. | 11-29-2012 |
20130077383 | Writing Circuit for a Resistive Memory Cell Arrangement and a Memory Cell Arrangement - A writing circuit for a resistive memory cell arrangement is provided, the resistive memory cell arrangement including a plurality of resistive memory cells. The writing circuit includes a controlled voltage source including a plurality of pass transistors, wherein each pass transistor includes a first source/drain terminal, a second source/drain terminal and a gate terminal, and wherein the first source/drain terminal is configured to be electrically coupled to a power supply line and the second source/drain terminal is configured to be electrically coupled to a bit line associated with a resistive memory cell of the plurality of resistive memory cells, and a plurality of switches, wherein each switch is configured to control the gate terminal of the pass transistor, wherein the controlled voltage source is configured to supply a voltage to the resistive memory cell for a write operation. Further embodiments provide a resistive memory cell arrangement. | 03-28-2013 |
20130170279 | Current Writing Circuit for a Resistive Memory Cell Arrangement - A current writing circuit for a resistive memory cell arrangement is provided. The current writing circuit comprises a first current source; a first reference potential terminal; a first switch configured to switch between the first current source and the first reference potential terminal during a write operation; a second current source; a second reference potential terminal; and a second switch configured to switch between the second reference potential terminal when the first switch is switched to the first current source, and the second current source when the first switch is switched to the first reference potential terminal, during the write operation, wherein the first current source and the second current source are of the same polarity. Further embodiments relate to a memory cell arrangement and a method of writing into a target resistive memory cell of a resistive memory cell arrangement. | 07-04-2013 |
20130279237 | READING CIRCUIT FOR A RESISTIVE MEMORY CELL - A reading circuit for a resistive memory cell is provided, the circuit including a current source, a precharge switch, a comparator circuit including a first input node (in-node), and a second in-node, the precharge switch configured to couple the current source to the first in-node to apply a precharge voltage during a first reading time period, and to decouple the current source during a second reading time period, the comparator circuit configured to operate during a third reading time period, a memory cell access switch to enable a current flow at least partially during the second and the third reading time periods through a memory cell, the comparator circuit configured to compare a voltage at the first in-node with a reference voltage at the second in-node and to determine a programming state of the memory cell based on the voltage at the first in-node during the third reading time period. | 10-24-2013 |
20130343116 | WRITING CIRCUIT FOR A MAGNETORESISTIVE MEMORY CELL, MEMORY CELL ARRANGEMENT AND METHOD OF WRITING INTO A MAGNETORESISTIVE MEMORY CELL OF A MEMORY CELL ARRANGEMENT - A writing circuit for a magnetoresistive memory cell is provided. The writing circuit includes a first electrical connecting terminal, a second electrical connecting terminal, a third electrical connecting terminal, a fourth electrical connecting terminal, a first reference potential terminal, a second reference potential terminal, a first switch configured to couple one of the first electrical connecting terminal, the second electrical connecting terminal, the third electrical connecting terminal and the fourth electrical connecting terminal to the magnetoresistive memory cell, and a second switch configured to couple the first reference potential terminal to the magnetoresistive memory cell if the first electrical connecting terminal or the second electrical connecting terminal is coupled to the magnetoresistive memory cell, and to couple the second reference potential terminal to the magnetoresistive memory cell if the third electrical connecting terminal or the fourth electrical connecting terminal is coupled to the magnetoresistive memory cell. | 12-26-2013 |
20140003126 | CIRCUIT ARRANGMENT AND A METHOD OF WRITING STATES TO A MEMORY CELL | 01-02-2014 |
20140149773 | LATCH CIRCUIT AND DATA PROCESSING SYSTEM - A latch circuit is described comprising a switchable resistive element and a switching circuit configured to set the switchable resistive element to a first resistive state in response to receiving a set signal and to set the switchable resistive element to a second resistive state in response to receiving a reset signal. | 05-29-2014 |
20140233331 | WRITE CONTROL CIRCUITS AND WIRE CONTROL METHODS - According to various embodiments, a write control circuit configured to control writing to a memory cell by applying a writing current to the memory cell may be provided. The write control circuit may include: a current application circuit configured to apply the writing current to the memory cell; a determination circuit configured to determine whether writing to the memory cell is finished; and a stop writing circuit configured to cut off the writing current from the memory cell if it is determined that writing to the memory cell is finished. | 08-21-2014 |
Patent application number | Description | Published |
20120267788 | Hybrid TSV and Method for Forming the Same - Generally, the subject matter disclosed herein relates to conductive via elements, such as through-silicon vias (TSV's), and methods for forming the same. One illustrative method of forming a conductive via element disclosed herein includes forming a via opening in a substrate, the via opening extending through an interlayer dielectric layer formed above the substrate and a device layer formed below the interlayer dielectric layer, and extending into the substrate. The method also includes forming a first portion of the conductive via element comprising a first conductive contact material in a bottom portion of the via opening, and forming a second portion of the conductive via element comprising a second conductive contact material different from the first conductive contact material in an upper portion of the via opening and above the first portion. | 10-25-2012 |
20120270391 | SCHEME FOR PLANARIZING THROUGH-SILICON VIAS - Generally, the subject matter disclosed herein relates to conductive via elements, such as through-silicon vias (TSV's), and methods for forming the same. One illustrative method disclosed herein includes forming a layer of isolation material above a via opening formed in a semiconductor device, the via opening extending into a substrate of the semiconductor device. The method also includes performing a first planarization process to remove at least an upper portion of the layer of isolation material formed outside of the via opening, and forming a conductive via element inside of the via opening after performing the first planarization process. | 10-25-2012 |
20150179547 | HYBRID TSV AND METHOD FOR FORMING THE SAME - A semiconductor chip includes a substrate and a semiconductor layer positioned above the substrate. A hybrid through-silicon via (“TSV”) extends continuously through at least the semiconductor layer and the substrate and includes a first TSV portion and a second TSV portion. A bottom plug portion of the first TSV portion is positioned in the substrate and has a lower surface adjacent to a back side of the substrate and an upper surface below the semiconductor layer. Upper sidewall portions of the first TSV portion extend from the upper surface through at least the semiconductor layer. A depth of the bottom plug portion is greater than a thickness of the upper sidewall portions. The second TSV portion is conductively coupled to the first TSV portion, is laterally surrounded by the upper sidewall portions, and extends continuously from the upper surface through at least the semiconductor layer. | 06-25-2015 |
Patent application number | Description | Published |
20090261466 | Semiconductor Device and Method of Forming Vertical Interconnect Structure Using Stud Bumps - A semiconductor device is made by forming a conductive layer over a temporary carrier. The conductive layer includes a wettable pad. A stud bump is formed over the wettable pad. The stud bump can be a stud bump or stacked bumps. A semiconductor die is mounted to the carrier. An encapsulant is deposited over the semiconductor die and around the stud bump. A first interconnect structure is formed over a first surface of the encapsulant. The first interconnect structure includes a first IPD and is electrically connected to the stud bump. The carrier is removed. A second interconnect structure is formed over a second surface of encapsulant opposite the first interconnect structure. The second interconnect structure includes a second IPD. The first or second IPD includes a capacitor, resistor, or inductor. The semiconductor devices are stackable and electrically connected through the stud bump. | 10-22-2009 |
20100140752 | Semiconductor Device and Method of Forming Compliant Polymer Layer Between UBM and Conformal Dielectric Layer/RDL for Stress Relief - A semiconductor device has a first conductive layer formed over a top surface of a substrate. A first insulating layer is formed over the substrate. A first dielectric layer is formed over the first insulating layer. A second conductive layer is formed over the first conductive layer and first dielectric layer. A second dielectric layer is formed over the second conductive layer. A polymer material is deposited over the second dielectric layer and second conductive layer. A third conductive layer is formed over the polymer material and second conductive layer. The third conductive layer is electrically connected to the second conductive layer. A first solder bump is formed over the third conductive layer. A conductive via is formed through a back surface of the substrate. The conductive via is electrically connected to the first conductive layer. The polymer material has a low coefficient of thermal expansion. | 06-10-2010 |
20100230822 | Semiconductor Die and Method of Forming Noise Absorbing Regions Between THVS in Peripheral Region of the Die - A semiconductor wafer has a plurality of semiconductor die. A peripheral region is formed around the die. An insulating material is formed in the peripheral region. A portion of the insulating material is removed to form a through hole via (THV). A conductive material is deposited in the THV to form a conductive THV. A conductive layer is formed between the conductive THV and contact pads of the semiconductor die. A noise absorbing material is deposited in the peripheral region between the conductive THV to isolate the semiconductor die from intra-device interference. The noise absorbing material extends through the peripheral region from a first side of the semiconductor die to a second side of the semiconductor die. The noise absorbing material has an angular, semi-circular, or rectangular shape. The noise absorbing material can be dispersed in the peripheral region between the conductive THV. | 09-16-2010 |
20100237471 | Semiconductor Die and Method of Forming Through Organic Vias Having Varying Width in Peripheral Region of the Die - A plurality of semiconductor die is mounted to a carrier separated by a peripheral region. An insulating material is deposited in the peripheral region. A first opening is formed in the insulating material of the peripheral region to a first depth. A second opening is formed in the insulating material of the peripheral region centered over the first opening to a second depth less than the first depth. The first and second openings constitute a composite through organic via (TOV) having a first width in a vertical region of the first opening and a second width in a vertical region of the second opening. The second width is different than the first width. A conductive material is deposited in the composite TOV to form a conductive TOV. An organic solderability preservative (OSP) coating is formed over a contact surface of the conductive TOV. | 09-23-2010 |
20100237495 | Semiconductor Device and Method of Providing Z-Interconnect Conductive Pillars with Inner Polymer Core - A semiconductor device is made by providing a sacrificial substrate and depositing an adhesive layer over the sacrificial substrate. A first conductive layer is formed over the adhesive layer. A polymer pillar is formed over the first conductive layer. A second conductive layer is formed over the polymer pillar to create a conductive pillar with inner polymer core. A semiconductor die or component is mounted over the substrate. An encapsulant is deposited over the semiconductor die or component and around the conductive pillar. A first interconnect structure is formed over a first side of the encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The sacrificial substrate and adhesive layers are removed. A second interconnect structure is formed over a second side of the encapsulant opposite the first interconnect structure. The second interconnect structure is electrically connected to the conductive pillar. | 09-23-2010 |
20100244241 | Semiconductor Device and Method of Forming a Thin Wafer Without a Carrier - A semiconductor device has a conductive via in a first surface of a substrate. A first interconnect structure is formed over the first surface of the substrate. A first bump is formed over the first interconnect structure. The first bump is formed over or offset from the conductive via. An encapsulant is deposited over the first bump and first interconnect structure. A portion of the encapsulant is removed to expose the first bump. A portion of a second surface of the substrate is removed to expose the conductive via. The encapsulant provides structural support and eliminates the need for a separate carrier wafer when thinning the substrate. A second interconnect structure is formed over the second surface of the substrate. A second bump is formed over the first bump. A plurality of semiconductor devices can be stacked and electrically connected through the conductive via. | 09-30-2010 |
20110140247 | INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SHIELDED PACKAGE AND METHOD OF MANUFACTURE THEREOF - A method of manufacture of an integrated circuit packaging system includes: providing a substrate assembly having a connection path; mounting a base device over the substrate assembly with a mount layer; mounting a stack device over the base device and having a stack die and a stack-organic-material; forming a stack-through-via in the stack-organic-material of the stack device and connected to the stack die and the substrate assembly; and applying a shield layer directly on a planarized surface of the stack-through-via partially exposed from the stack-organic-material. | 06-16-2011 |
20120091567 | Semiconductor Die and Method of Forming Noise Absorbing Regions Between THVs in Peripheral Region of the Die - A semiconductor wafer has a plurality of semiconductor die. A peripheral region is formed around the die. An insulating material is formed in the peripheral region. A portion of the insulating material is removed to form a through hole via (THV). A conductive material is deposited in the THV to form a conductive THV. A conductive layer is formed between the conductive THV and contact pads of the semiconductor die. A noise absorbing material is deposited in the peripheral region between the conductive THV to isolate the semiconductor die from intra-device interference. The noise absorbing material extends through the peripheral region from a first side of the semiconductor die to a second side of the semiconductor die. The noise absorbing material has an angular, semi-circular, or rectangular shape. The noise absorbing material can be dispersed in the peripheral region between the conductive THV. | 04-19-2012 |
20120153472 | Semiconductor Device and Method of Providing Z-Interconnect Conductive Pillars with Inner Polymer Core - A semiconductor device is made by providing a sacrificial substrate and depositing an adhesive layer over the sacrificial substrate. A first conductive layer is formed over the adhesive layer. A polymer pillar is formed over the first conductive layer. A second conductive layer is formed over the polymer pillar to create a conductive pillar with inner polymer core. A semiconductor die or component is mounted over the substrate. An encapsulant is deposited over the semiconductor die or component and around the conductive pillar. A first interconnect structure is formed over a first side of the encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The sacrificial substrate and adhesive layers are removed. A second interconnect structure is formed over a second side of the encapsulant opposite the first interconnect structure. The second interconnect structure is electrically connected to the conductive pillar. | 06-21-2012 |
20120199972 | Semiconductor Device and Method of Forming Vertical Interconnect Structure Using Stud Bumps - A semiconductor device is made by forming a conductive layer over a temporary carrier. The conductive layer includes a wettable pad. A stud bump is formed over the wettable pad. The stud bump can be a stud bump or stacked bumps. A semiconductor die is mounted to the carrier. An encapsulant is deposited over the semiconductor die and around the stud bump. A first interconnect structure is formed over a first surface of the encapsulant. The first interconnect structure includes a first IPD and is electrically connected to the stud bump. The carrier is removed. A second interconnect structure is formed over a second surface of encapsulant opposite the first interconnect structure. The second interconnect structure includes a second IPD. The first or second IPD includes a capacitor, resistor, or inductor. The semiconductor devices are stackable and electrically connected through the stud bump. | 08-09-2012 |
20120280402 | Semiconductor Die and Method of Forming through Organic Vias having Varying Width in Peripheral Region of the Die - A plurality of semiconductor die is mounted to a carrier separated by a peripheral region. An insulating material is deposited in the peripheral region. A first opening is formed in the insulating material of the peripheral region to a first depth. A second opening is formed in the insulating material of the peripheral region centered over the first opening to a second depth less than the first depth. The first and second openings constitute a composite through organic via (TOV) having a first width in a vertical region of the first opening and a second width in a vertical region of the second opening. The second width is different than the first width. A conductive material is deposited in the composite TOV to form a conductive TOV. An organic solderability preservative (OSP) coating is formed over a contact surface of the conductive TOV. | 11-08-2012 |
20120280403 | Semiconductor Die and Method of Forming through Organic Vias having Varying Width in Peripheral Region of the Die - A plurality of semiconductor die is mounted to a carrier separated by a peripheral region. An insulating material is deposited in the peripheral region. A first opening is formed in the insulating material of the peripheral region to a first depth. A second opening is formed in the insulating material of the peripheral region centered over the first opening to a second depth less than the first depth. The first and second openings constitute a composite through organic via (TOV) having a first width in a vertical region of the first opening and a second width in a vertical region of the second opening. The second width is different than the first width. A conductive material is deposited in the composite TOV to form a conductive TOV. An organic solderability preservative (OSP) coating is formed over a contact surface of the conductive TOV. | 11-08-2012 |
20130285236 | Semiconductor Device and Method of Forming a Thin Wafer Without a Carrier - A semiconductor device has a conductive via in a first surface of a substrate. A first interconnect structure is formed over the first surface of the substrate. A first bump is formed over the first interconnect structure. The first bump is formed over or offset from the conductive via. An encapsulant is deposited over the first bump and first interconnect structure. A portion of the encapsulant is removed to expose the first bump. A portion of a second surface of the substrate is removed to expose the conductive via. The encapsulant provides structural support and eliminates the need for a separate carrier wafer when thinning the substrate. A second interconnect structure is formed over the second surface of the substrate. A second bump is formed over the first bump. A plurality of semiconductor devices can be stacked and electrically connected through the conductive via. | 10-31-2013 |
20140203443 | Semiconductor Device and Method of Providing Z-Interconnect Conductive Pillars with Inner Polymer Core - A semiconductor device is made by providing a sacrificial substrate and depositing an adhesive layer over the sacrificial substrate. A first conductive layer is formed over the adhesive layer. A polymer pillar is formed over the first conductive layer. A second conductive layer is formed over the polymer pillar to create a conductive pillar with inner polymer core. A semiconductor die or component is mounted over the substrate. An encapsulant is deposited over the semiconductor die or component and around the conductive pillar. A first interconnect structure is formed over a first side of the encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The sacrificial substrate and adhesive layers are removed. A second interconnect structure is formed over a second side of the encapsulant opposite the first interconnect structure. The second interconnect structure is electrically connected to the conductive pillar. | 07-24-2014 |
Patent application number | Description | Published |
20120161319 | BALL GRID ARRAY METHOD AND STRUCTURE - A process for making an integrated circuit, a wafer level integrated circuit package or an embedded wafer level package includes forming copper contact pads on a substrate or substructure. The substructure may include devices and the contact pads may be used for forming electrical couplings to the devices. For example, copper plating may be applied to a substructure and the copper plating etched to form copper contact pads on the substructure. An etching process may be applied to remove barrier layer material on the substructure, such as adjacent to the copper pads. For example, a hydrogen peroxide etch may be applied to remove titanium-tungsten from a surface of the substructure. The pads are again etched to remove barrier layer etchant, byproducts and/or oxide from the pads. Contamination control steps may be performed, such as quick-dump-and-rinse (QDR) and spin-rinse-and-dry (SRD) processing. | 06-28-2012 |
20120168942 | THROUGH HOLE VIA FILLING USING ELECTROLESS PLATING - An embedded wafer level ball grid array (eWLB) is formed by embedding a semiconductor die in a molding compound. A trench is formed in the molding compound with a laser drill. A first layer of copper is deposited on the sidewall of the trench by physical vapor deposition. A second layer of copper is then formed on the first layer of copper by an electroless process. A third layer of copper is then formed on the second layer by electroplating. | 07-05-2012 |
20120168944 | THROUGH HOLE VIA FILLING USING ELECTROLESS PLATING - An embedded wafer level ball grid array (eWLB) is formed by embedding a semiconductor die in a molding compound. A trench is formed in the molding compound with a laser drill. A first layer of copper is deposited on the sidewall of the trench by physical vapor deposition. A second layer of copper is then formed on the first layer of copper by an electroless process. A third layer of copper is then formed on the second layer by electroplating. | 07-05-2012 |
20120282767 | METHOD FOR PRODUCING A TWO-SIDED FAN-OUT WAFER LEVEL PACKAGE WITH ELECTRICALLY CONDUCTIVE INTERCONNECTS, AND A CORRESPONDING SEMICONDUCTOR PACKAGE - A semiconductor packaging process includes drilling apertures in a reconstituted wafer, then filling the apertures with conductive paste by wiping a quantity of the paste across a back surface of the wafer so that paste is forced into the apertures. The paste is cured to form conductive posts. The wafer is thinned, and redistribution layers are formed on front and back surfaces of the wafer, with the posts acting as interconnections between the redistribution layers. In an alternative process, blind apertures are drilled. A dry film resist is applied to the front surface of the wafer, and patterned to expose the apertures. Conductive paste is applied from the front. To prevent paste from trapping air pockets in the apertures, the wiping process is performed under vacuum. After curing the paste, the wafer is thinned to expose the cured paste in the apertures, and redistribution layers are formed. | 11-08-2012 |
20130105973 | EMBEDDED WAFER LEVEL PACKAGE FOR 3D AND PACKAGE-ON-PACKAGE APPLICATIONS, AND METHOD OF MANUFACTURE | 05-02-2013 |
20130105991 | EMBEDDED WAFER LEVEL PACKAGE FOR 3D AND PACKAGE-ON-PACKAGE APPLICATIONS, AND METHOD OF MANUFACTURE | 05-02-2013 |
20130170169 | CIRCUIT MODULE WITH MULTIPLE SUBMODULES - An embodiment of a circuit module includes module nodes, a first submodule, a second submodule, and a conductive structure. The first submodule has a first submodule node, and the second submodule is disposed over the first submodule and has a second submodule node. The conductive structure couples the first submodule node to one of the module nodes and couples the second submodule node to one of the module nodes. Another embodiment of a circuit module includes module nodes, a first submodule, a second submodule, and a conductive structure. The first submodule has first submodule nodes, and the second submodule is disposed over the first submodule and has second submodule nodes. The conductive structure couples one of the first and second submodule nodes to one of the module nodes and couples one of the first submodule nodes to one of the second submodule nodes. | 07-04-2013 |
20140113410 | SYSTEM IN PACKAGE MANUFACTURING METHOD USING WAFER-TO-WAFER BONDING - Embodiments of the present disclosure are related to manufacturing system-in-packages at wafer-level. In particular, various embodiments are directed to adhering a first wafer to a second wafer and adhering solder balls to contact pads of the first wafer. In one embodiment, a first wafer having first and second surfaces is provided. The first wafer includes bond pads located on the first surface that are coupled to a respective semiconductor device located in the first wafer. A second wafer having an electrical component located therein is provided. A conductive adhesive is provided on at least one of the first wafer and the second wafer. Conductive balls are provided on the bond pads on the first surface of the first wafer. The conductive balls and the conductive adhesive are heated to cause the conductive balls to adhere to the bond pad and the conductive adhesive to adhere the first wafer to the second wafer. | 04-24-2014 |
20140175649 | ELECTRONIC DEVICE INCLUDING ELECTRICALLY CONDUCTIVE VIAS HAVING DIFFERENT CROSS-SECTIONAL AREAS AND RELATED METHODS - An electronic device may include a bottom interconnect layer having a first electrically conductive via therein. The electronic device may also include an integrated circuit (IC) carried by said bottom interconnect layer, and an encapsulation material on the bottom interconnect layer and surrounding the IC. The encapsulation layer may have a second electrically conductive via therein aligned with the first electrically conductive via. The second electrically conductive via may have a cross-sectional area larger than a cross-sectional area of the first electrically conductive via. | 06-26-2014 |
Patent application number | Description | Published |
20080221457 | Multimodal Detection of Tissue Abnormalities Based on Raman and Background Fluorescence Spectroscopy - Methods and apparatus for classifying tissue use features of Raman spectra and background fluorescent spectra. The spectra may be acquired in the near-infrared wavelengths. Principal component analysis and linear discriminant analysis of reference spectra may be used to obtain a classification function that accepts features of the Raman and background fluorescence spectra for test tissue and yields an indication as to the likelihood that the test tissue is abnormal. The methods and apparatus may be applied to screening for skin cancers or other diseases. | 09-11-2008 |
20150216417 | DIAGNOSTIC INSTRUMENT AND METHODS RELATING TO RAMAN SPECTROSCOPY - A probe head for a diagnostic instrument, the probe head comprising;
| 08-06-2015 |
20150335248 | METHODS RELATED TO REAL-TIME CANCER DIAGNOSTICS AT ENDOSCOPY UTILIZING FIBER-OPTIC RAMAN SPECTROSCOPY - A method of achieving instrument independent measurements for quantitative analysis of fiber-optic Raman spectroscope system, the system comprising a laser source, a spectroscope and a fiber optic probe to transmit light from the laser source to a target and return scattered light to the spectroscope, the method comprising transmitting light from the laser source to a standard target having a known spectrum, recording a calibration spectrum of the scattered light from the standard target, comparing the known spectrum and the calibration system and generating a probe and/or probe-system transfer function, and storing the transfer function. Further provided is a method of performing real-time diagnostic Raman spectroscopy optionally in combination with the other disclosed methods. | 11-26-2015 |
20160000330 | Diagnostic Instrument and Method - A diagnostic instrument comprises a monochromatic light source, transmission means to transmit light from the light source to a test site, collection means to transmit scattered light from the test site, and spectral analysis apparatus to receive light from the collection means, the spectral analysis apparatus comprising a diffraction grating having a first grating element and a second grating element, wherein the first grating element diffracts light within a first wavelength range and the second grating element diffracts light within a second wavelength range, the spectral analysis apparatus further comprising a light-sensing apparatus, the first grating element arranged to diffract light onto a first area of the light-sensing apparatus and the second grating element arranged to diffract light onto a second area of the light-sensing apparatus. | 01-07-2016 |
Patent application number | Description | Published |
20100151782 | METHOD AND APPARATUS FOR BROADCAST CONTENT RELATED NOTIFICATION - The present invention is a system and method for broadcast content related notification. In embodiments, a Notification Generation unit (NTG) generates a notification message, the notification message including notification event description and related broadcast content identifiers. A broadcast content identifier references to a broadcast service, content or program which the notification event is related with. A Notification Channel Selection unit (NTCS) selects a notification channel to be used for delivery of the notification message. A Notification Distribution unit (NTD) uses the selected notification channel for the delivery of notification messages to one or multiple terminals. A Notification Reception unit (NTR) in a terminal receives the notification message from the notification channel. Notification Process unit (NTP) in the terminal processes the notification message and process the notification messages according to the notification event description, the related broadcast content identifiers and other information. | 06-17-2010 |
20110137177 | OPTICAL-COMBINED IMAGING METHOD, OPTICAL-COMBINED IMAGING APPARATUS, PROGRAM, AND INTEGRATED CIRCUIT - An optical-combined imaging method which improves image quality and shortens the time for imaging includes: a structure identification step (S | 06-09-2011 |
20110268362 | PROBE AND IMAGE RECONSTRUCTION METHOD USING PROBE - Provided is a probe capable of effectively performing NIR imaging by optimally arranging input channels and detection channels, and an image reconstruction method using the probe. The probe ( | 11-03-2011 |
20120230546 | GENERIC OBJECT-BASED IMAGE RECOGNITION APPARATUS WITH EXCLUSIVE CLASSIFIER, AND METHOD FOR THE SAME - The present invention provides an image recognition apparatus with enhanced performance and robustness. | 09-13-2012 |
20130071031 | IMAGE PROCESSING DEVICE, IMAGE PROCESSING METHOD, IMAGE PROCESSING PROGRAM, AND INTEGRATED CIRCUIT - The present invention provides an image processing device capable of combining a plurality of contents (e.g. videos) with a story line retained as much as possible, while reducing view's discomfort. The image processing device compares one of the contents, which contains a first partial content and a second partial content subsequent to the first partial content, with another one of the contents, which contains a plurality of consecutive partial contents, so as to detect, as a third partial content, a partial content with the highest similarity value from among the plurality of partial contents, and generates relational information by using the highest similarity value obtained by the first processing unit, the relational information being used for merging the first partial content, the second partial content and the third partial content. | 03-21-2013 |
20140193074 | IMAGE RECOGNITION DEVICE, IMAGE RECOGNITION METHOD, AND INTEGRATED CIRCUIT - An image recognition device that improves the accuracy of generic object recognition compared with conventional technologies by reducing the influence of the position, size, background clutter and the like of an object that is targeted to be recognized in the input image by the generic object recognition. The image recognition device performs a generic object recognition and includes: a segmenting unit configured to segment an input image into a plurality of regions in accordance with meanings extracted from content of the input image; a generating unit configured to compute feature data for each of the plurality of regions and generate feature data of the input image reflecting the computed feature data; and a checking unit configured to check whether or not a recognition-target object is present in the input image in accordance with the feature data of the input image. | 07-10-2014 |