Patent application number | Description | Published |
20120124402 | DETERMINING A POWER SAVING MODE BASED ON A HARDWARE RESOURCE UTILIZATION TREND - Techniques are disclosed for managing the amount of power consumed by server components of a computer system, each server component having multiple power modes. The utilization of each server component is monitored. Based on the monitored utilization, a time period is determined in which to apply a selected power mode to the respective server component. The respective server component is configured to operate in the selected power mode for at least the determined time period. | 05-17-2012 |
20130091947 | DETERMINING A POWER SAVING MODE BASED ON A HARDWARE RESOURCE UTILIZATION TREND - Techniques are disclosed for managing the amount of power consumed by server components of a computer system, each server component having multiple power modes. The utilization of each server component is monitored. Based on the monitored utilization, a time period is determined in which to apply a selected power mode to the respective server component. The respective server component is configured to operate in the selected power mode for at least the determined time period. | 04-18-2013 |
20150082055 | Changing Output Power to be Within a Range Based on a Power Use Efficiency Peak - If a total output power provided to a computer is less than a minimum of a power capacity range around a power use efficiency peak, and the occurrence of the total output power being less than the minimum value occurs more than a first threshold number of times within a time period, a first action is performed that causes the total output power provided to the computer to change to exceed the minimum of the power capacity range. If the total output power provided to the computer is greater than a maximum of the power capacity range, and the occurrence of the total output power being greater than the maximum occurs more than a second threshold number of times within the time period, a second action is performed that causes the total output power provided to the computer to change to be less than the maximum of the power capacity range. | 03-19-2015 |
Patent application number | Description | Published |
20100185819 | INTELLIGENT CACHE INJECTION - A first cache simultaneously broadcasts, in a single message, a request for a cache line and a request to accept a future related evicted cache line to multiple other caches. Each of the multiple other caches evaluate their occupancy to derive an occupancy value that reflects their ability to accept the future related evicted cache line. In response to receiving a requested cache line, the first cache evicts the related evicted cache line to the cache with the highest occupancy value. | 07-22-2010 |
20110119322 | On-Chip Networks for Flexible Three-Dimensional Chip Integration - Mechanisms for providing an interconnect layer of a three-dimensional integrated circuit device having multiple independent and cooperative on-chip networks are provided. With regard to an apparatus implementing the interconnect layer, such an apparatus comprises a first integrated circuit layer comprising one or more first functional units and an interconnect layer coupled to the first integrated circuit layer. The first integrated circuit layer and interconnect layer are integrated with one another into a single three-dimensional integrated circuit. The interconnect layer comprises a plurality of independent on-chip communication networks that are independently operable and independently able to be powered on and off, each on-chip communication network comprising a plurality of point-to-point communication links coupled together by a plurality of connection points. The one or more first functional units are coupled to a first independent on-chip communication network of the interconnect layer. | 05-19-2011 |
20120038057 | THERMAL ENHANCEMENT FOR MULTI-LAYER SEMICONDUCTOR STACKS - A circuit arrangement and method in one aspect utilize thermal-only through vias, extending between the opposing faces of stacked semiconductor dies, to increase the thermal conductivity of a multi-layer semiconductor stack. The thermal vias are provided in addition to data-carrying through vias, which communicate data signals between circuit layers, and power-carrying through vias, which are coupled to a power distribution network for the circuit layers, such that the thermal conductivity is increased above that which may be provided by the data-carrying and power-carrying through vias in the stack. A circuit arrangement and method in another aspect organize the circuit layers in a multi-layer semiconductor stack based upon current density so as to reduce power distribution losses in the stack. | 02-16-2012 |
Patent application number | Description | Published |
20100271071 | Universal Inter-Layer Interconnect for Multi-Layer Semiconductor Stacks - A circuit arrangement and method utilize a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers. Based upon a standardized placement of the inter-layer interface region in each circuit layer, and a standardized arrangement of electrical conductors associated with the inter-layer bus, each circuit layer may designed using a standardized template upon which the design features necessary to implement the inter-layer bus are already provided, thereby simplifying circuit layer design and the interconnection of functional units to the inter-layer bus. In addition, vertically-oriented supernodes may be defined within a semiconductor stack to provide multiple independently-operating nodes having functional units disposed in multiple circuit layers of the stack. | 10-28-2010 |
20120098140 | HYBRID BONDING TECHNIQUES FOR MULTI-LAYER SEMICONDUCTOR STACKS - A circuit arrangement and method utilize hybrid bonding techniques that combine wafer-wafer bonding processes with chip-chip and/or chip-wafer bonding processes to form a multi-layer semiconductor stack, e.g., by bonding together one or more sub-assemblies formed by wafer-wafer bonding together with other sub-assemblies and/or chips using chip-chip and/or chip-wafer bonding processes. By doing so, the advantages of wafer-wafer bonding techniques, such as higher interconnect densities, may be leveraged with the advantages of chip-chip and chip-wafer bonding techniques, such as mixing and matching chips with different sizes, aspect ratios, and functions. | 04-26-2012 |
20120124291 | Secondary Cache Memory With A Counter For Determining Whether to Replace Cached Data - A selective cache includes a set configured to receive data evicted from a number of primary sets of a primary cache. The selective cache also includes a counter associated with the set. The counter is configured to indicate a frequency of access to data within the set. A decision whether to replace data in the set with data from one of the primary sets is based on a value of the counter. | 05-17-2012 |
20120187570 | HYBRID BONDING TECHNIQUES FOR MULTI-LAYER SEMICONDUCTOR STACKS - A circuit arrangement and method utilize hybrid bonding techniques that combine wafer-wafer bonding processes with chip-chip and/or chip-wafer bonding processes to form a multi-layer semiconductor stack, e.g., by bonding together one or more sub-assemblies formed by wafer-wafer bonding together with other sub-assemblies and/or chips using chip-chip and/or chip-wafer bonding processes. By doing so, the advantages of wafer-wafer bonding techniques, such as higher interconnect densities, may be leveraged with the advantages of chip-chip and chip-wafer bonding techniques, such as mixing and matching chips with different sizes, aspect ratios, and functions. | 07-26-2012 |
20120198406 | UNIVERSAL INTER-LAYER INTERCONNECT FOR MULTI-LAYER SEMICONDUCTOR STACKS - An apparatus, program product and method facilitate the design of a multi-layer circuit arrangement incorporating a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers. | 08-02-2012 |
20130009324 | UNIVERSAL INTER-LAYER INTERCONNECT FOR MULTI-LAYER SEMICONDUCTOR STACKS - An apparatus, program product and method facilitate the design of a multi-layer circuit arrangement incorporating a universal, standardized inter-layer interconnect in a multi-layer semiconductor stack to facilitate interconnection and communication between functional units disposed on a stack of semiconductor dies. Each circuit layer in the multi-layer semiconductor stack is required to include an inter-layer interface region that is disposed at substantially the same topographic location such that when the semiconductor dies upon which such circuit layers are disposed are arranged together in a stack, electrical conductors disposed within each semiconductor die are aligned with one another to provide an inter-layer bus that is oriented vertically, or transversely, with respect to the individual circuit layers. | 01-10-2013 |
20130011968 | HYBRID BONDING TECHNIQUES FOR MULTI-LAYER SEMICONDUCTOR STACKS - A circuit arrangement and method utilize hybrid bonding techniques that combine wafer-wafer bonding processes with chip-chip and/or chip-wafer bonding processes to form a multi-layer semiconductor stack, e.g., by bonding together one or more sub-assemblies formed by wafer-wafer bonding together with other sub-assemblies and/or chips using chip-chip and/or chip-wafer bonding processes. By doing so, the advantages of wafer-wafer bonding techniques, such as higher interconnect densities, may be leveraged with the advantages of chip-chip and chip-wafer bonding techniques, such as mixing and matching chips with different sizes, aspect ratios, and functions. | 01-10-2013 |