Patent application number | Description | Published |
20080305655 | PIN GRID ARRAY PACKAGE SUBSTRATE INCLUDING PINS HAVING ANCHORING ELEMENTS - A microelectronic package substrate and an electrically conductive pin. The substrates includes: a die-side surface adapted to receive a die thereon; a PCB-side surface adapted to be mechanically and electrically bonded to a PCB; an array of land pads on the PCB-side surface, the land pads defining anchoring recesses therein; an array of electrically conductive pins electrically and mechanically bonded to respective ones of the land pads, the pins having anchoring elements thereon mated with corresponding ones of the anchoring recesses of the land pads, the anchoring elements and anchoring recesses being configured such that a mating thereof inhibits a tilting of the pins on the land pads; and a plurality of pin-attach solder joints mechanically and electrically bonding the pins to corresponding ones of the land pads. | 12-11-2008 |
20090001550 | Method of Forming a Multilayer Substrate Core Structure Using Sequential Microvia Laser Drilling And Substrate Core Structure Formed According to the Method - A method of fabricating a substrate core structure, and a substrate core structure formed according to the method. The method includes: laser drilling a first set of via openings through a starting insulating layer; filling the first set of via openings with a conductive material to provide a first set of conductive vias; providing first and second patterned conductive layers on opposite sides of the starting insulating layer; providing a supplemental insulating layer onto the first patterned conductive layer; laser drilling a second set of via openings through the supplemental insulating layer; filling the second set of via openings with a conductive material to provide a second set of conductive vias; and providing a supplemental patterned conductive layer onto an exposed side of the supplemental insulating layer, the second set of conductive vias contacting the first patterned conductive layer and the supplemental patterned conductive layer at opposite sides thereof. | 01-01-2009 |
20090002958 | Method of Forming a Substrate Core Structure Using Microvia Laser Drilling and Conductive Layer Pre-Patterning And Substrate Core Structure Formed According to the Method - A method of fabricating a substrate core structure comprises, providing first and second patterned conductive layers defining openings therein on each side of a starting insulating layer; providing a first and a second supplemental insulating layers onto respective ones of a first and a second patterned conductive layer; laser drilling a set of via openings extending through at least some of the conductive layer openings of the first and second patterned conductive layers; filling the set of via openings with a conductive material to provide a set of conductive vias; and providing a first and a second supplemental patterned conductive layer onto respective ones of the first and the second supplemental insulating layers, the set of conductive vias contacting the first supplemental patterned conductive layer at one side thereof and the second supplemental patterned conductive layer at another side thereof. | 01-01-2009 |
20090004403 | Method of Providing Patterned Embedded Conducive Layer Using Laser Aided Etching of Dielectric Build-Up Layer - A method of providing a patterned conductive layer. The method includes: providing a build-up layer comprising an insulating material; laser irradiating selected portions of the build-up layer according to a predetermined pattern of the patterned conductive layer to be provided, laser irradiating comprising using a laser beam having a photon energy higher than a bonding energy of at least some of the chemical bonds of the insulating material to yield predetermined laser-weakened portions of the build-up layer according to the predetermined pattern; removing the laser-weakened portions of the build-up layer to yield recesses according to the predetermined pattern; and filling the recesses with a conductive material to yield the patterned conductive layer. | 01-01-2009 |
20090047783 | METHOD OF REMOVING UNWANTED PLATED OR CONDUCTIVE MATERIAL FROM A SUBSTRATE, AND METHOD OF ENABLING METALLIZATION OF A SUBSTRATE USING SAME - A method of removing unwanted material from a substrate includes providing a system ( | 02-19-2009 |
20090081381 | METHOD OF ENABLING SELECTIVE AREA PLATING ON A SUBSTRATE - A method of enabling selective area plating on a substrate includes forming a first electrically conductive layer ( | 03-26-2009 |
20090084755 | METHOD FOR FORMING MICRO-VIAS ON A SUBSTRATE - A method for forming at least one micro-via on a substrate is disclosed. The method comprises drilling at least one hole in a substrate by using a first laser beam. The first laser beam has an energy distribution, which is more at edges of the first laser beam than at the center of the first laser beam. The method further comprises forming at least one blank pattern on a top surface of the substrate and around an outer periphery of the at least one hole by removing at least a portion of the substrate by using a second laser beam. At least one blank pattern of the plurality of blank pattern corresponds to pad of the at least one micro-via. Thereafter, the method comprises filling the plurality of blank patterns and the at least one micro-via with a conductive material to form at least micro-via. | 04-02-2009 |
20090152743 | ROUTING LAYER FOR A MICROELECTRONIC DEVICE, MICROELECTRONIC PACKAGE CONTAINING SAME, AND METHOD OF FORMING A MULTI-THICKNESS CONDUCTOR IN SAME FOR A MICROELECTRONIC DEVICE - A routing layer for a microelectronic device includes a first region ( | 06-18-2009 |
20090170239 | UTILIZING APERTURE WITH PHASE SHIFT FEATURE IN FORMING MICROVIAS - A method, comprises drilling a set of one or more microvias in a semiconductor package with an aperture, wherein drilling the set of microvias comprises to use an aperture that has a phase shift region to reduce a spot size of a drilling beam that is used to form the set of microvias. | 07-02-2009 |
20090238516 | SUBSTRATES FOR OPTICAL DIE STRUCTURES - Package substrates for optical die structures are generally described. In one example, an apparatus includes a package substrate having one or more plated through hole (PTH) structures, an optical waveguide coupled with the package substrate, the optical waveguide having one or more input/output (I/O) optical signal pathways to route I/O signals to and from the package substrate, and one or more optical fibers coupled with the optical waveguide, the one or more optical fibers being disposed in the PTH structures to route I/O signals to and from a motherboard. | 09-24-2009 |
20100078805 | METHOD AND CORE MATERIALS FOR SEMICONDUCTOR PACKAGING - A semiconductor package comprises a semiconductor substrate that may comprise a core. The core may comprise one or more materials selected from a group comprising ceramics and glass dielectrics. The package further comprises a set of one or more inner conductive elements that is provided on the core, a set of one or more outer conductive elements that is provided on an outer side of the substrate, and a semiconductor die to couple to the substrate via one or more of the outer conductive elements. Example materials for the core may comprise one or more from alumina, zirconia, carbides, nitrides, fused silica, quartz, sapphire, and Pyrex. A laser may be used to drill one or more plated through holes to couple an inner conductive element to an outer conductive element. A dielectric layer may be formed in the substrate to insulate an outer conductive element from the core or an inner conductive element. | 04-01-2010 |
20100101084 | SAME LAYER MICROELECTRONIC CIRCUIT PATTERNING USING HYBRID LASER PROJECTION PATTERNING (LPP) AND SEMI-ADDITIVE PATTERNING(SAP) - In some embodiments, same layer microelectronic circuit patterning using hybrid laser projection patterning (LPP) and semi-additive patterning (SAP) is presented. In this regard, a method is introduced including patterning a first density region of a laminated substrate surface using LPP, patterning a second density region of the laminated substrate surface using SAP, and plating the first and second density regions of the laminated substrate surface, wherein features spanning the first and second density regions are directly coupled. Other embodiments are also disclosed and claimed. | 04-29-2010 |
20100126009 | Method of enabling selective area plating on a substrate - A method of enabling selective area plating on a substrate ( | 05-27-2010 |
20100163295 | COAXIAL PLATED THROUGH HOLES (PTH) FOR ROBUST ELECTRICAL PERFORMANCE - In some embodiments, coaxial plated through holes (PTH) for robust electrical performance are presented. In this regard, an apparatus is introduced comprising an integrated circuit device and a substrate coupled with the integrated circuit device, wherein the substrate includes: a plated through hole, the plated through hole filled with dielectric material and a coaxial copper wire, and conductive traces to separately route the plated through hole and the coaxial copper wire. Other embodiments are also disclosed and claimed. | 07-01-2010 |
20100163535 | Method of forming a pattern on a work piece, method of shaping a beam of electromagnetic radiation for use in said method, and aperture for shaping a beam of electromagnetic radiation - A method of forming a pattern ( | 07-01-2010 |
20100289154 | METHOD AND CORE MATERIALS FOR SEMICONDUCTOR PACKAGING - A semiconductor package comprises a semiconductor substrate that may comprise a core. The core may comprise one or more materials selected from a group comprising ceramics and glass dielectrics. The package further comprises a set of one or more inner conductive elements that is provided on the core, a set of one or more outer conductive elements that is provided on an outer side of the substrate, and a semiconductor die to couple to the substrate via one or more of the outer conductive elements. Example materials for the core may comprise one or more from alumina, zirconia, carbides, nitrides, fused silica, quartz, sapphire, and Pyrex. A laser may be used to drill one or more plated through holes to couple an inner conductive element to an outer conductive element. A dielectric layer may be formed in the substrate to insulate an outer conductive element from the core or an inner conductive element. | 11-18-2010 |
20110058340 | METHOD OF FORMING A MULTILAYER SUBSTRATE CORE STRUCTURE USING SEQUENTIAL MICROVIA LASER DRILLING AND SUBSTRATE CORE STRUCTURE FORMED ACCORDING TO THE METHOD - A method of fabricating a substrate core structure, and a substrate core structure formed according to the method. The method includes: laser drilling a first set of via openings through a starting insulating layer; filling the first set of via openings with a conductive material to provide a first set of conductive vias; providing first and second patterned conductive layers on opposite sides of the starting insulating layer; providing a supplemental insulating layer onto the first patterned conductive layer; laser drilling a second set of via openings through the supplemental insulating layer; filling the second set of via openings with a conductive material to provide a second set of conductive vias; and providing a supplemental patterned conductive layer onto an exposed side of the supplemental insulating layer, the second set of conductive vias contacting the first patterned conductive layer and the supplemental patterned conductive layer at opposite sides thereof. | 03-10-2011 |
20110123725 | METHOD OF ENABLING SELECTIVE AREA PLATING ON A SUBSTRATE - A method of enabling selective area plating on a substrate includes forming a first electrically conductive layer ( | 05-26-2011 |
20120146180 | HYBRID-CORE THROUGH HOLES AND VIAS - A semiconductor device substrate includes a front section and back section that are laminated cores disposed on a front- and back surfaces of a first core. The first core has a cylindrical plated through hole that has been metal plated and filled with air-core material. The front- and back sections have laser-drilled tapered vias that are filled with conductive material and that are coupled to the plated through hole. The back section includes an integral inductor coil that communicates to the front section. The first core and the laminated-cores form a hybrid-core semiconductor device substrate with an integral inductor coil. | 06-14-2012 |
20130189812 | COAXIAL PLATED THROUGH HOLES (PTH) FOR ROBUST ELECTRICAL PERFORMANCE - In some embodiments, coaxial plated through holes (PTH) for robust electrical performance are presented. in this regard, an apparatus is introduced comprising an integrated circuit device and a substrate coupled with the integrated circuit device, wherein the substrate includes: a plated through hole, the plated through hole filled with dielectric material and a coaxial copper wire, and conductive traces to separately route the plated through hole and the coaxial copper wire. Other embodiments are also disclosed. | 07-25-2013 |
20130242498 | METHOD OF FORMING A SUBSTRATE CORE STRUCTURE USING MICROVIA LASER DRILLING AND CONDUCTIVE LAYER PRE-PATTERNING AND SUBSTRATE CORE STRUCTURE FORMED ACCORDING TO THE METHOD - A method of fabricating a substrate core structure comprises: providing first and second patterned conductive layers defining openings therein on each side of a starting insulating layer; providing a first and a second supplemental insulating layers onto respective ones of a first and a second patterned conductive layer; laser drilling a set of via openings extending through at least some of the conductive layer openings of the first and second patterned conductive layers; filling the set of via openings with a conductive material to provide a set of conductive vias; and providing a first and a second supplemental patterned conductive layer onto respective ones of the first and the second supplemental insulating layers, the set of conductive vias contacting the first supplemental patterned conductive layer at one side thereof, and the second supplemental patterned conductive layer at another side thereof. | 09-19-2013 |
20140204454 | CONFIGURATION OF ACOUSTO-OPTIC DEFLECTORS FOR LASER BEAM SCANNING - A first acousto-optic deflector receives a laser beam. The first acousto-optic deflector diffracts the received laser beam along a first axis. A second acousto-optic deflector receives the diffracted laser beam. The second acousto-optic deflector diffracts the received diffracted laser beam along a second axis. | 07-24-2014 |
20140332975 | MULTICHIP INTEGRATION WITH THROUGH SILICON VIA (TSV) DIE EMBEDDED IN PACKAGE - Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with three-dimensional (3D) integration of multiple dies, as well as corresponding fabrication methods and systems incorporating such 3D IC package assemblies. A bumpless build-up layer (BBUL) package substrate may be formed on a first die, such as a microprocessor die. Laser radiation may be used to form an opening in a die backside film to expose TSV pads on the back side of the first die. A second die, such as a memory die stack, may be coupled to the first die by die interconnects formed between corresponding TSVs of the first and second dies. Underfill material may be applied to fill some or all of any remaining gap between the first and second dies, and/or an encapsulant may be applied over the second die and/or package substrate. Other embodiments may be described and/or claimed. | 11-13-2014 |