Patent application number | Description | Published |
20110014776 | METHOD FOR PRODUCING SOI SUBSTRATE - A method for easily manufacturing a transparent SOI substrate having: a main surface with a silicon film formed thereon; and a rough main surface located on a side opposite to a side where the silicon film is formed. A method for manufacturing transparent SOI substrate, having a silicon film formed on a first main surface of the transparent insulating substrate, while a second main surface of the transparent insulating substrate, an opposite to the first main surface, is roughened. The method includes at least the steps of: roughening the first main surface with an RMS surface roughness lower than 0.7 nm and the second main surface with an RMS surface roughness higher than the surface roughness of the first main surface to prepare the transparent insulating substrate; and forming the silicon film on the first main surface of the transparent insulating substrate. | 01-20-2011 |
20120228730 | MICROCHIP AND SOI SUBSTRATE FOR MANUFACTURING MICROCHIP - A plasma treatment or an ozone treatment is applied to the respective bonding surfaces of the single-crystal Si substrate in which the ion-implanted layer has been formed and the quartz substrate, and the substrates are bonded together. Then, a force of impact is applied to the bonded substrate to peel off a silicon thin film from the bulk portion of single-crystal silicon along the hydrogen ion-implanted layer, thereby obtaining an SOI substrate having an SOI layer on the quartz substrate. A concave portion, such as a hole or a micro-flow passage, is formed on a surface of the quartz substrate of the SOI substrate thus obtained, so that processes required for a DNA chip or a microfluidic chip are applied. A silicon semiconductor element for the analysis/evaluation of a sample attached/held to this concave portion is formed in the SOI layer. | 09-13-2012 |
20130288453 | METHOD OF MANUFACTURING LAMINATED WAFER BY HIGH TEMPERATURE LAMINATING METHOD - A method of manufacturing a laminated wafer is provided by forming a silicon film layer on a surface of an insulating substrate comprising the steps in the following order of: applying a surface activation treatment to both a surface of a silicon wafer or a silicon wafer to which an oxide film is layered and a surface of the insulating substrate followed by laminating in an atmosphere of temperature exceeding 50° C. and lower than 300° C., applying a heat treatment to a laminated wafer at a temperature of 200° C. to 350° C., and thinning the silicon wafer by a combination of grinding, etching and polishing to form a silicon film layer. | 10-31-2013 |
20140120794 | THERMAL INSULATION LAMINATE - Provided is a thermal insulation laminate having both of an excellent thermal insulation property and high visible light transmittance, and further having a provided antifouling property and an excellent scratch resistance. A thermal insulation laminate includes a photocatalytic layer ( | 05-01-2014 |
20140327116 | COMPOSITE SUBSTRATE - Disclosed is a composite substrate, which is provided with an inorganic insulating sintered substrate, which has a heat conductivity of 5 W/m·K or more, and a volume resistivity of 1×10 | 11-06-2014 |
Patent application number | Description | Published |
20090221131 | Method for preparing substrate having monocrystalline film - Provided is a method for easily preparing a substrate comprising a monocrystalline film thereon or thereabove with almost no crystal defects without using a special substrate. More specifically, provided is a method for preparing a substrate comprising a monocrystalline film formed on or above a handle substrate, the method comprising: a step A of providing a donor substrate and the handle substrate; a step B of growing a monocrystalline layer on the donor substrate; a step C of implanting ions into the monocrystalline layer on the donor substrate so as to form an ion-implanted layer; a step D of bonding a surface of the monocrystalline layer of the ion-implanted donor substrate to a surface of the handle substrate; and a step E of peeling the bonded donor substrate at the ion-implanted layer existing in the monocrystalline layer so as to form the monocrystalline film on or above the handle substrate; wherein at least the steps A to E are repeated by using the handle substrate having the monocrystalline film formed thereon or thereabove as a donor substrate. | 09-03-2009 |
20090246935 | Method for producing soi substrate - Provided is a method for producing an SOI substrate comprising a transparent insulating substrate and a silicon film formed on a first major surface of the insulating substrate wherein a second major surface of the insulating substrate which is opposite to the major surface is roughened, the method suppressing the generation of metal impurities and particles in a simple and easy way. More specifically, provided is a method for producing an SOI substrate comprising a transparent insulating substrate, a silicon film formed on a first major surface of the transparent insulating substrate, and a roughened second major surface, which is opposite to the first major surface, the method comprising steps of: providing the transparent insulating substrate, mirror surface-processing at least the first major surface of the transparent insulating substrate, forming a silicon film on the first major surface of the transparent insulating substrate, and laser-processing the second major surface of the transparent insulating substrate so as to roughen the second major surface by using a laser. | 10-01-2009 |
20100244182 | METHOD OF MANUFACTURING LAMINATED WAFER BY HIGH TEMPERATURE LAMINATING METHOD - To provide a method of manufacturing a laminated wafer by which a strong coupling is achieved between wafers made of different materials having a large difference in thermal expansion coefficient without lowering a maximum heat treatment temperature as well as in which cracks or chips of the wafer does not occur. A method of manufacturing a laminated wafer | 09-30-2010 |
Patent application number | Description | Published |
20080299376 | SILICON ON INSULATOR (SOI) WAFER AND PROCESS FOR PRODUCING SAME - Ion injection is performed to a single crystal silicon wafer to form an ion injection layer, with the ion injection surface of the single crystal silicon wafer and/or the surface of the transparent insulation substrate are/is processed using plasma and/or ozone. The ion injection surface of the single crystal silicon wafer and the surface of the transparent insulation substrate are bonded to each other by bringing them into close contact with each other at room temperature. A silicon on insulator (SOI) wafer is obtained by mechanically peeling the single crystal silicon wafer by giving an impact to the ion injection layer, to form an SOI layer on the transparent insulation substrate, and thermal processing for flattening the SOI layer surface is performed to the SOI wafer, under an atmosphere of an inert gas, a hydrogen gas, and a mixture gas of them. | 12-04-2008 |
20080305317 | SILICON ON INSULATOR (SOI) WAFER AND PROCESS FOR PRODUCING SAME - In a manufacturing method for manufacturing a silicon on insulator (SOI) wafer, an ion injection layer is formed within the wafer, by injecting a hydrogen ion or a rare gas ion from a surface of the single crystal silicon wafer, the ion injection surface of the single crystal silicon wafer and/or a surface of the transparent insulation substrate is processed using plasma and/or ozone, the ion injection surface of the single crystal silicon wafer is bonded to the surface of the transparent insulation substrate, by bringing them into close contact with each other at room temperature, with the processed surface(s) as bonding surface(s), and an SOI layer is formed on the transparent insulation substrate, by mechanically peeling the single crystal silicon wafer by giving an impact to the ion injection layer. | 12-11-2008 |
20080305318 | SILICON ON INSULATOR (SOI) WAFER AND PROCESS FOR PRODUCING SAME - In a manufacturing method of manufacturing a silicon on insulator (SOI) wafer, a single crystal silicon whose surface is an N region on an outer side of an OSF region, is grown and sliced to fabricate an N region single crystal silicon. An ion injection layer is formed within the N region single crystal silicon wafer by injecting a hydrogen ion or a rare gas ion from a surface of the N region single crystal silicon wafer; the ion injection surface of the N region single crystal silicon wafer and/or a surface of the transparent insulation substrate is processed using plasma and/or ozone. The ion injection surface is bonded to the surface of the transparent insulation substrate by bringing them into close contact with each other at room temperature. An SOI layer is formed by mechanically peeling the single crystal silicon wafer. | 12-11-2008 |
20140065051 | METHOD FOR MANUFACTURING SILICON CARBIDE POWDER - A method for revitalizing worn and fatigued silicon carbide powder thermally reacted it continuously with a mixture of silicon oxide powder and/or carbon powder and a boron and carbon-containing additive in a non-oxidizing atmosphere at a temperature higher than 1850 degrees C. but lower than 2400 degrees C. | 03-06-2014 |
Patent application number | Description | Published |
20110316131 | SEMICONDUCTOR DEVICE WITH HEAT SPREADER - A BGA type semiconductor device includes: a substrate having wirings and electrodes; a semiconductor element disposed on the substrate, having a rectangular plan shape, and a plurality of electrodes disposed along each side of the semiconductor element; a plurality of wires connecting the electrodes on the semiconductor element with the electrodes on the substrate; a heat dissipation member disposed on the substrate, covering the semiconductor element, and having openings formed in areas facing apex portions of the plurality of wires connected to the electrodes formed along each side of the semiconductor element; and a sealing resin member for covering and sealing the semiconductor element and heat dissipation member. | 12-29-2011 |
20120319264 | SEMICONDUCTOR DEVICE WITH HEAT SPREADER - A BGA type semiconductor device includes: a substrate having wirings and electrodes; a semiconductor element disposed on the substrate, having a rectangular plan shape, and a plurality of electrodes disposed along each side of the semiconductor element; a plurality of wires connecting the electrodes on the semiconductor element with the electrodes on the substrate; a heat dissipation member disposed on the substrate, covering the semiconductor element, and having openings formed in areas facing apex portions of the plurality of wires connected to the electrodes formed along each side of the semiconductor element; and a sealing resin member for covering and sealing the semiconductor element and heat dissipation member. | 12-20-2012 |
20120319275 | SEMICONDUCTOR DEVICE WITH HEAT SPREADER - A BGA type semiconductor device includes: a substrate having wirings and electrodes; a semiconductor element disposed on the substrate, having a rectangular plan shape, and a plurality of electrodes disposed along each side of the semiconductor element; a plurality of wires connecting the electrodes on the semiconductor element with the electrodes on the substrate; a heat dissipation member disposed on the substrate, covering the semiconductor element, and having openings formed in areas facing apex portions of the plurality of wires connected to the electrodes formed along each side of the semiconductor element; and a sealing resin member for covering and sealing the semiconductor element and heat dissipation member. | 12-20-2012 |
20120322209 | SEMICONDUCTOR DEVICE WITH HEAT SPREADER - A BGA type semiconductor device includes: a substrate having wirings and electrodes; a semiconductor element disposed on the substrate, having a rectangular plan shape, and a plurality of electrodes disposed along each side of the semiconductor element; a plurality of wires connecting the electrodes on the semiconductor element with the electrodes on the substrate; a heat dissipation member disposed on the substrate, covering the semiconductor element, and having openings formed in areas facing apex portions of the plurality of wires connected to the electrodes formed along each side of the semiconductor element; and a sealing resin member for covering and sealing the semiconductor element and heat dissipation member. | 12-20-2012 |