Patent application number | Description | Published |
20080212290 | ROTATABLE COMPONENT SUPPORT ASSEMBLY FOR AN ELECTRONICS ENCLOSURE - An electronics component support assembly and an electronics system assembly employing the component support assembly are provided. The component support assembly includes a rotatable base support and a component connector assembly. The rotatable base support is sized to reside within an electronics enclosure and to operatively support multiple electronics components thereon. The component connector assembly is associated with the rotatable base support, and at least some electronics components of the multiple electronics components couple thereto when operatively supported by the rotatable base support. Rotation of the rotatable base support facilitates access to the multiple electronics components, and the component connector assembly allows for rotation of the rotatable base support with the multiple electronics components operatively supported on the rotatable base support. | 09-04-2008 |
20080267060 | METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR PROVIDING HIGH SPEED FAULT TRACING WITHIN A BLADE CENTER SYSTEM - Providing high speed fault tracing within a blade center system by using a high speed transmitter port of a switch to implement a first snoop port and using a high speed receiver port of the switch to implement a second snoop port, thus permitting snooping of the blade center system from a single blade slot. | 10-30-2008 |
20080267192 | SYSTEMS AND METHODS FOR MONITORING HIGH SPEED NETWORK TRAFFIC VIA SEQUENTIALLY MULTIPLEXED DATA STREAMS - Systems and methods for monitoring high-speed network traffic via sequentially multiplexed data streams. Exemplary embodiments include a switch module system, including a first switch module configured to be coupled to a first, server chassis, a first data port disposed on the first switch module and a set of first port data links configured to be coupled to a set of data port data links, each data link configurable to channel at least one of a normal data stream and a monitored data stream. | 10-30-2008 |
20080270638 | SYSTEMS AND METHODS FOR MONITORING HIGH SPEED NETWORK TRAFFIC VIA SIMULTANEOUSLY MULTIPLEXED DATA STREAMS - Systems and methods for monitoring high-speed network traffic via simultaneously multiplexed data streams. Exemplary embodiments include a switch module system, including a first switch module coupled to a first server chassis, a first data port disposed on the first switch module and a set of data links disposed on the first data port, each data link configurable to receive a normal data stream and a monitored data stream. | 10-30-2008 |
20080304489 | APPARATUS AND METHOD TO SET THE SIGNALING RATE OF A NETWORK DISPOSED WITHIN AN INFORMATION STORAGE AND RETRIEVAL SYSTEM - A method is disclosed to set the speed of a network. The method supplies a network interconnected with a system controller and a plurality of switch domains, where each of those plurality of switch domains comprises one or more information storage devices and a switch domain controller, and sets by each of the plurality of switch domains a signaling rate for that switch domain. The method queries in-band by the system controller each of the plurality of switch domains for that switch domain's signaling rate, and provides in-band by each of the plurality of switch domains the signaling rate for that switch domain. The method provides in-band by the system controller to each of the plurality of switch domains a first speed selection command specifying a first network speed, and resets by each of the plurality of switch domains the signaling rate for that switch domain to the first network speed. | 12-11-2008 |
20080307185 | APPARATUS AND METHOD TO SET SIGNAL COMPENSATION SETTINGS FOR A DATA STORAGE DEVICE - A method is disclosed to set signal compensation settings for a data storage device comprising a first port and a second port, where that first port is interconnected to a first switch via a first communication pathway having a predetermined first length. The method determines first signal compensation settings based upon the first length. | 12-11-2008 |
20090006889 | I2C Failure Detection, Correction, and Masking - A method of operation of a computer system having a master and slave Inter-IC (I2C) bus network includes detecting and isolating an I2C bus failure, configuring a failed I2C bus as offline, reconfiguring a remaining I2C bus as a multi-mastered bus, and masking the failed I2C bus from operation until the failed I2C bus can be repaired. A first test request is sent to a remote device from a local device. If the remote device receives the first test request, a remote bus mode is switched to a failure position, a local bus mode is switched to a multi-master position, and a second request is sent to the remote device to indicate position changes. | 01-01-2009 |
20090102423 | APPARATUS AND METHOD TO PROVIDE POWER TO BATTERY-BACKUP ASSEMBLIES DISPOSED IN AN INFORMATION STORAGE AND RETRIEVAL SYSTEM - A method to supply power to one or more battery-backup assemblies, wherein the method supplies a first controller, a second controller, a first battery-backup assembly, and a second battery-backup assembly. The method further supplies a power bus interconnected to the first controller, the second controller, the first battery-backup assembly, and the second battery-backup assembly, and a first power supply and a second power supply interconnected with the power bus. The method provides power to the first controller and to the second controller and to the first battery-backup assembly over a first period of time, and provides power to the first controller and to the second controller and to the second battery-backup assembly over a second period of time, where the first period of time differs from the second period of time. | 04-23-2009 |
20090147646 | APPARATUS AND METHOD TO VISUALLY INDICATE THE STATUS OF A DATA STORAGE DEVICE - A data storage and retrieval system that comprises a data storage device is disclosed. The data storage and retrieval system further comprises a first LED, a second LED, a third LED, and a fourth LED, interconnected with the data storage device. The data storage device causes the first LED and the second LED to emit first light comprising a first color if the data storage device detects an internal failure. Alternatively, the storage device causes the third LED and the fourth LED to emit second light comprising a second color if the data storage device remains operative. | 06-11-2009 |
20090187707 | System and method of maximization of storage capacity in a configuration limited system - A method, system and computer-usable medium are disclosed for providing management of serial attached small computer system interface (SAS) storage devices. A host computer comprises a storage controller connected to a SAS port expander comprising a plurality of ports that are logically assigned to target storage devices. The device ports of all storage devices physically attached to the SAS port expander are bypassed to remove their logical SAS expander port assignments. The storage controller unbypasses the device ports, allowing it to recognize the presence of all physically attached storage devices. The recognized storage devices are inventoried and storage devices that are not logically assigned a SAS expander port are designated as being spare storage devices. SAS expander ports are logically assigned to the non-spare storage devices and SAS storage operations are performed. | 07-23-2009 |
20090235130 | TEST PATTERN CUSTOMIZATION OF HIGH SPEED SAS NETWORKS IN A MANUFACTURING TEST SYSTEM - A method for testing a high-speed serial interface, comprising: generating a customized stress test pattern configured to violate an 8bit/10bit-encoding scheme into an expander, the customized stress test pattern is configured to stress the high-speed serial interface beyond marginal limits resulting in less testing to force errors within the high-speed serial interface; transmitting the customized stress test pattern from a transmit port of a first serializer/deserializer device of the high-speed serial interface; and monitoring a receive port of a second serializer/deserializer device to detect errors within the high-speed serial interface. | 09-17-2009 |
20090254772 | Extending and Scavenging Super-Capacitor Capacity - A memory system has mechanisms for scavenging capacity of a super capacitor by removing, or reducing, system load from the super capacitor when the super capacitor voltage decays below a low threshold. The mechanisms then restore the system load to the super capacitor when the super capacitor voltage ramps back above a high threshold. A controller may reduce system load by placing a volatile memory system in a standby state and disabling a field effect transistor to remove power from a non-volatile memory system. A controller may adjust the high threshold and/or a low threshold by setting a digitally controlled potentiometer in a threshold detect circuit via an I | 10-08-2009 |
20090279439 | SYSTEMS, METHODS AND COMPUTER PROGRAM PRODUCTS FOR CONTROLLING HIGH SPEED NETWORK TRAFFIC IN SERVER BLADE ENVIRONMENTS - Systems, methods and computer program products for controlling high-speed network traffic in server blade environments. Exemplary embodiments include a method for controlling high-speed network traffic in a server blade network, the method including identifying a port under test, identifying a debug port, identifying a code state of interest from the port under test and generating a modified IDLE word in response to an identification of a code state of interest from the port under test. | 11-12-2009 |
20090307563 | REPLACING BAD HARD DRIVE SECTORS USING MRAM - A method of a method of replacing bad sectors in a Hard Disk Drive comprises detecting bad sectors on the Hard Disk Drive; remapping the bad sectors to an auxiliary data storage device comprising an Magnetoresistive Random Access Memory connected to the Hard Disk Drive; and storing data on the auxiliary storage device. | 12-10-2009 |
20090323452 | Dual Mode Memory System for Reducing Power Requirements During Memory Backup Transition - A controller of a memory system is configured to reduce power requirements during memory backup transition. When transitioning to backup mode, the memory system controller performs a number of power saving techniques. The controller may change a number of configuration settings in the volatile memory system, such as reducing output driver strength, increasing differential impedance, increasing on-die termination, disabling receiver input circuitry, and disconnecting the termination voltage network. The controller may also assert a hard reset to the storage controller system to significantly reduce the load and allow the voltage regulator to continue to provide power to the memory system for a longer period of time. | 12-31-2009 |
20090327578 | Flash Sector Seeding to Reduce Program Times - A non-volatile flash memory comprises a plurality of non-volatile memories where a first non-volatile memory is pre-programmed (erased) with all ones, and at least a second non-volatile memory is pre-programmed with a seed value that takes advantage of the reduced programming time for less than six zeros. When writing (programming) a data byte, the memory system looks up the data byte in one or more seed tables to determine a portion of non-volatile memory to which the memory system may write the data byte with a reduced programming time. The memory system then records the location of the data byte in an address translation table so the data byte may be accessed. | 12-31-2009 |
20100008409 | METHOD FOR CLOCK JITTER STRESS MARGINING OF HIGH SPEED INTERFACES - A method for clock jitter stress margining of high speed interfaces including generating a jittered clock signal via a clock signal generator of a high speed interface controller card, inputting the jittered clock signal to a control input of a looped-back port of the high speed interface controller card, inputting a test pattern signal to the looped-back port generated from a logic circuitry of the high speed interface controller card, receiving the test pattern signal to the logic circuitry from the looped-back port via the transmitter to the receiver, monitoring a bit error rate of the looped-back port by comparing the received test pattern signal to the inputted test pattern signal, and outputting a fail indication signal if the bit error rate is within a fail threshold. | 01-14-2010 |
20100011261 | Verifying Data Integrity of a Non-Volatile Memory System during Data Caching Process - To ensure integrity of non-volatile flash, the controller programs the non-volatile memories with background test patterns and verifies the non-volatile memories during power on self test (POST) operation. In conjunction with verifying the non-volatile memories, the controller may routinely run diagnostics and report status to the storage controller. As part of the storage controller power up routines, the storage controller issues a POST command to the controller via an I | 01-14-2010 |
20100046590 | EXTENDING TRANSMISSION DISTANCE IN A HIGH-SPEED SERIAL NETWORK - A data transmission system for transmitting data from a first location to a second location includes a transmitting device configured to transmit the data and located at the first location. The transmitting device includes a serial attached SCSI (SAS) enabled controller. The system also includes an I/O port coupled to the transmitting device and having multiple lanes and a repeater powered by one of the lanes. The system also includes a receiving device coupled to the second end of the cable. | 02-25-2010 |
20100052625 | In Situ Verification of Capacitive Power Support - A mechanism for in situ verification of capacitive power support is provided. A memory system uses a super capacitor to support a voltage rail when input power is lost or interrupted. The voltage discharge curve is a function of load and capacitance of the component. By stepping the regulated power supply to a lower output within the voltage range and recording voltage and current draw at the super capacitor as it discharges to the new regulator output voltage, the super capacitor holdup capability can be tested. | 03-04-2010 |
20100064164 | Autonomic Component Service State Management for a Multiple Function Component - A mechanism is provided for autonomic component service state management for a multiple function component. The mechanism determines whether independent functions within a multiple function service boundary can be serviced. When a single function experiences a failure that requires service, repair, or replacement, the surviving functions notify the service management software of the state of the independent functions. The service management software then determines the state of the overall component and implements the appropriate service method. | 03-11-2010 |
20100088533 | Single Shared Power Domain Dynamic Load Based Power Loss Detection and Notification - The advanced management module services in a data processing system are configured to determine the system load and provide an input to the early power off warning detection logic that evaluates the power system state to detect a condition when power resources are insufficient to maintain the write caching storage system power within defined acceptable limits. The early power off warning detection logic generates a notification based on the system load and the available power supply resources to maintain maximum availability and reliability characteristics. | 04-08-2010 |
20100180162 | Freeing A Serial Bus Hang Condition by Utilizing Distributed Hang Timers - A method for automatically detecting and correcting one or more hang conditions within one or more of a master device and target device of a serial bus interface when one or more signals are held in an invalid state. A hang timer monitors one or more operations of the serial bus when the serial bus is participating in a serial bus transfer. If the transfer does not end before the bus timeout value has been exceeded, the hang timer will issue a reset to the state machine forcing the state machine back to an idle state. The hang timer will also disable the serial bus drivers of the state machine, whereby the hang condition is corrected. | 07-15-2010 |
20100199021 | Firehose Dump of SRAM Write Cache Data to Non-Volatile Memory Using a Supercap - A mechanism is provided for firehose dumping modified data in a static random access memory of a hard disk drive to non-volatile memory of the hard disk drive during a power event. Responsive an indication of a power event in the hard disk drive, hard disk drive command processing is suspended. A token is set in the non-volatile storage indicating that flash memory in the non-volatile memory contains modified data. A portion of a static random access memory cache table containing information on the modified data in the static random access memory is copied to the flash memory. The modified data from the static random access memory is then copied to the flash memory. Responsive to a determination that the power event that initiated the copy of the modified data in the static random access memory to the flash memory is still present, the hard disk drive is shut down. | 08-05-2010 |
20100318820 | STORAGE SYSTEM POWER MANAGEMENT - A method for managing power consumed by storage systems and other devices is disclosed herein. In certain embodiments, such a method may include initially monitoring conditions (such as data traffic conditions) on a communication link between a first device and a second device. The method may further include determining whether the conditions on the communication link warrant powering down or powering up the second device. In the event the conditions warrant powering down the second device, a power-down command may be generated and transmitted from the first device to the second device. In the event the conditions warrant powering up the second device, a power-up command may be generated and transmitted from the first device to the second device. In selected embodiments, the power-up and power-down commands are one of SCSI commands and FICON commands. A corresponding apparatus, system, and computer-usable medium are also disclosed and claimed herein. | 12-16-2010 |
20110038639 | POWER-UP OF DEVICE VIA OPTICAL SERIAL INTERFACE - An optical communication serial interface is employed to power up a device from a powered down state to a powered on state. An optical receiver element receives serial optical signals transmitted by at least one optical fiber and converts the received serial optical signals to electrical signals. A low level reception converter detects and decodes the electrical signals to provide data and control words from detected and decoded normal electrical signals for a high level command processor. A power supply maintains low level power to at least the optical receiver element and the low level reception converter of the optical communication serial interface while the device is in the powered down state. The low level reception converter detects a particular abnormal sequence of electrical signals; and in response to detecting the particular abnormal sequence of electrical signals, asserts a control signal to power up the device controllable power supply. | 02-17-2011 |
20110099320 | Solid State Drive with Adjustable Drive Life and Capacity - A method for adjusting a drive life and a capacity of a solid state drive (SSD), the SSD comprising a plurality of memory devices includes determining a desired drive life for the SSD; determining a utilization for the SSD; and allocating a portion of the plurality of memory devices as available memory and a portion of the plurality of memory devices as spare memory based on the desired drive life and the utilization. An SSD with an adjustable drive life and capacity includes a plurality of memory devices; and a memory allocation module configured to: determine a desired drive life for the SSD; determine a utilization for the SSD; and allocate a portion of the plurality of memory devices as available memory and a portion of the plurality of memory devices as spare memory based on the desired drive life and the utilization. | 04-28-2011 |
20110099419 | SOLID STATE DRIVE WITH FLASH SPARING - A method for flash sparing on a solid state drive (SSD) includes detecting a failure from a primary memory device; determining if a failure threshold for the primary memory device has been reached; and, in the event the failure threshold for the primary memory device has been reached: quiescing the SSD; and updating an entry in a sparing map table to replace the primary memory device with a spare memory device. | 04-28-2011 |
20110113279 | Method Apparatus and System for a Redundant and Fault Tolerant Solid State Disk - A redundant and fault tolerant solid state disk (SSDC) includes a determination module configured to identify a first SSDC configured to connect to a flash array and a second SSDC configured to connect to the flash array. A capture module is configured to capture a copy of an I/O request received by the first SSDC from a port of a dual port connector, and/or capture a copy of an I/O request received by the second SSDC from a port of the dual port connector, and identify a write I/O request from the I/O request. A detection module is configured to detect a failure in the first SSDC. A management module is configured to manage access to a flash array by the first SSDC and the second SSDC. An error recovery and failover module is configured to automatically reassign work from the first SSDC to the second SSDC. | 05-12-2011 |
20120198249 | Shared Power Domain Dynamic Load Based Power Loss Detection and Notification - The advanced management module services in a data processing system are configured to determine the system load and provide an input to the early power off warning detection logic that evaluates the power system state to detect a condition when power resources are insufficient to maintain the write caching storage system power within defined acceptable limits. The early power off warning detection logic generates a notification based on the system load and the available power supply resources to maintain maximum availability and reliability characteristics. | 08-02-2012 |
20120207468 | POWER-UP OF DEVICE VIA OPTICAL SERIAL INTERFACE - An optical communication serial interface is employed to power up a device from a powered down state to a powered on state. An optical receiver element receives serial optical signals transmitted by at least one optical fiber and converts the received serial optical signals to electrical signals. A low level reception converter detects and decodes the electrical signals to provide data and control words from detected and decoded normal electrical signals for a high level command processor. A power supply maintains low level power to at least the optical receiver element and the low level reception converter of the optical communication serial interface while the device is in the powered down state. The low level reception converter detects a particular abnormal sequence of electrical signals; and in response to detecting the particular abnormal sequence of electrical signals, asserts a control signal to power up the device controllable power supply. | 08-16-2012 |
20120215971 | Firehose Dump of SRAM Write Cache Data to Non-Volatile Memory Using a Supercap - A mechanism is provided for firehose dumping modified data in a static random access memory of a hard disk drive to non-volatile memory of the hard disk drive during a power event. Responsive an indication of a power event in the hard disk drive, hard disk drive command processing is suspended. A token is set in the non-volatile storage indicating that flash memory in the non-volatile memory contains modified data. A portion of a static random access memory cache table containing information on the modified data in the static random access memory is copied to the flash memory. The modified data from the static random access memory is then copied to the flash memory. Responsive to a determination that the power event that initiated the copy of the modified data in the static random access memory to the flash memory is still present, the hard disk drive is shut down. | 08-23-2012 |
20120215973 | Method Apparatus and System for a Redundant and Fault Tolerant Solid State Disk - A solid state drive includes a first solid state disc controller (SSDC), a second SSDC and a flash array. The flash array includes a first flash port and a second flash port. The first SSDC is configured to connect to the flash array through the first flash port and the second flash array is configured to connect to the flash array through the second flash port. The first SSDC and the second SSDC are both configured to connect to all memory within the flash array and the first SSDC, second SSDC, and flash array are within a common solid state drive. | 08-23-2012 |
20120239867 | Flash Sector Seeding to Reduce Program Times - A non-volatile flash memory comprises a plurality of non-volatile memories where a first non-volatile memory is pre-programmed (erased) with all ones, and at least a second non-volatile memory is pre-programmed with a seed value that takes advantage of the reduced programming time for less than six zeros. When writing (programming) a data byte, the memory system looks up the data byte in one or more seed tables to determine a portion of non-volatile memory to which the memory system may write the data byte with a reduced programming time. The memory system then records the location,of the data byte in an address translation table so the data byte may be accessed. | 09-20-2012 |
20130246841 | METHOD, APPARATUS, AND SYSTEM FOR A REDUNDANT AND FAULT TOLERANT SOLID STATE DISK - A solid state drive includes a first solid state disc controller (SSDC), a second SSDC and a flash array. The flash array includes a first flash port and a second flash port. The first SSDC is configured to connect to the flash array through the first flash port and the second flash array is configured to connect to the flash array through the second flash port. | 09-19-2013 |
20140365791 | REMOTE POWER DOWN CONTROL OF A DEVICE - In remote power down control of a device configured for externally initiated remote power down, such as over a network, activity of all externally connected sources of valid power down requests for the device is monitored; and the device is powered down in response to a combination of one of a received power down request and an inactivity time out with respect to each of the sources of valid power down requests for the device. | 12-11-2014 |