Patent application number | Description | Published |
20100054045 | Memory and Reading Method Thereof - A memory includes many memory regions each including a target memory cell, a source line, a bit line and a reading control circuit. The source line is coupled to a first terminal of the target memory cell. The bit line is coupled to a second terminal of the target memory cell. The reading control circuit is for selectively applying a working voltage to the source line. | 03-04-2010 |
20100322018 | Temperature Compensation Circuit and Method for Sensing Memory - A compensation circuit includes a comparator and an emulation circuit. The comparator has a first terminal, and a second terminal for receiving a reference voltage. The emulation circuit is coupled to the first terminal of the comparator. The emulation circuit responses to the temperature, so that the comparator outputs a read timing control signal at a first time spot, or outputs the read timing control signal at a second time spot, the first time spot is later than the second time spot. | 12-23-2010 |
20110085380 | Method of Programming a Memory - A method of programming a memory, wherein the memory includes many memory regions having multiple multi-level cells. Each memory region includes a first bit line, a second bit line, a data buffer and a protecting unit. The protecting unit, coupled to the first and second bit lines, and the data buffer, prevents a programming error from occurring. In an embodiment of the programming method, corresponding data are inputted to the data buffers respectively. The data corresponding to an n | 04-14-2011 |
20110161750 | Pre-Code Device, and Pre-Code System and Pre-Coding Method Thereof - A pre-code device includes firstly memory circuit, an address decoder, and an alternative logic circuit. The first memory circuit includes a number of memory blocks and at east a replacing block. The memory blocks are pointed by a number of respective physical addresses. The replacing block is pointed by a replacing address. The address decoder decodes an input address to provide a pre-code address. The alternative logic circuit looks up an address mapping table, which maps defect physical address among the physical addresses to the replacing address, to map the pre-code address to the replacing address when the pre-code address corresponds to the defect physical address. The alternative logic circuit correspondingly pre-codes the pre-code data to the replacing block. | 06-30-2011 |
20120300562 | METHOD AND CIRCUIT FOR TESTING A MULTI-CHIP PACKAGE - A method and circuit for testing a multi-chip package is provided. The multi-chip package includes at least a memory chip, and the memory chip includes a number of memory cells. The method includes performing a normal read operation on the memory cells to check if data read from the memory cells is the same with preset data in the memory cells; and performing a special read operation on the memory cells to check if data read from the memory cells is the same with an expected value, wherein the expected value is independent from data stored in the memory cells. | 11-29-2012 |
Patent application number | Description | Published |
20080304337 | METHOD FOR ACCESSING MEMORY - A method for accessing memory is provided. The memory includes many multi-level cells each having at least a storage capable of storing 2 | 12-11-2008 |
20080307163 | METHOD FOR ACCESSING MEMORY - A method for accessing memory is provided. The memory includes many multi-level cells each having at least a storage capable of storing 2 | 12-11-2008 |
20090021994 | MEMORY AND METHOD FOR PROGRAMMING THE SAME - A method for programming a memory, which includes multiple multi-level cells each having a left half cell and a right half cell, includes the following steps. First, a target address corresponding to 2n-group data to be stored is provided, wherein n is a positive integer. Next, the 2n-group data is sequentially programmed into the multi-level cells based upon the target address in a programming loop so that the data stored in the left half cells and the data stored in the right half cells are from different groups of the 2n-group data. | 01-22-2009 |
20100027339 | PAGE BUFFER AND METHOD OF PROGRAMMING AND READING A MEMORY - A page buffer and method of programming and reading a memory are provided. The page buffer includes a first latch, a second latch, a data change unit and a program control unit. The first latch includes a first terminal for loading data of the lower page and the upper page. The second latch includes a first terminal for storing the data of the lower page and the upper page from the first latch. The data change unit is coupled to a second terminal of the first latch for changing a voltage of the second terminal of the first latch to a low level. The program control unit is coupled to the first terminal of the second latch and the cells, and controlled by the voltage of the first terminal of the first latch for respectively programming the data of the lower page and the upper page to a target cell. | 02-04-2010 |
20100124136 | TEMPERATURE COMPENSATION CIRCUIT AND METHOD FOR SENSING MEMORY - A temperature compensation circuit includes a voltage generator, a comparator and an emulation cell array. The voltage generator provides a predetermined voltage and a reference voltage. The comparator has a first terminal for receiving the predetermined voltage, and a second terminal for receiving the reference voltage. The emulation cell array is coupled to the first terminal of the comparator. When a voltage of the first terminal of the comparator is discharged, via the emulation cell array, to be lower than the reference voltage, the comparator outputs a read timing control signal to control a sense amplifier to perform a sensing operation. | 05-20-2010 |