Huffman, TX
Chad B. Huffman, Houston, TX US
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20080210370 | MACROSCOPIC ORDERED ASSEMBLY OF CARBON NANOTUBES - The present invention is directed to the creation of macroscopic materials and objects comprising aligned nanotube segments. The invention entails aligning single-wall carbon nanotube (SWNT) segments that are suspended in a fluid medium and then removing the aligned segments from suspension in a way that macroscopic, ordered assemblies of SWNT are formed. The invention is further directed to controlling the natural proclivity or nanotube segments to self assemble into or ordered structures by modifying the environment of the nanotubes and the history of that environment prior to and during the process. The materials and objects are “macroscopic” in that they are large enough to be seen without the aid of a microscope or of the dimensions of such objects. These macroscopic ordered SWNT materials and objects have the remarkable physical, electrical, and chemical properties that SWNT exhibit on the microscopic scale because they are comprised of nanotubes, each of which is aligned in the same direction and in contact with its nearest neighbors. An ordered assembly of closest SWNT also serves as a template for growth of more and larger ordered assemblies. An ordered assembly further serves as a foundation for post processing treatments that modify the assembly internally to specifically enhance selected material properties such as shear strength, tensile strength, compressive strength, toughness, electrical conductivity, and thermal conductivity. | 09-04-2008 |
Craig Huffman, Krugerville, TX US
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20080206988 | Formation of fully silicided gate with oxide barrier on the source/drain silicide regions - A simple and cost effective method of forming a fully silicided (FUSI) gate of a MOS transistor is disclosed. In one example, the method comprises forming a nitride hardmask overlying a polysilicon gate, forming an S/D silicide in source/drain regions of the transistor, oxidizing a portion of the S/D silicide to form an oxide barrier overlying the S/D silicide in the source/drain regions, removing the nitride hardmask from the polysilicon gate, and forming a gate silicide such as by deposition of a gate silicide metal over the polysilicon gate and the oxide barrier in the source/drain regions to form a fully silicided (FUSI) gate in the transistor. Thus, the oxide barrier protects the source/drain regions from additional silicide formation by the gate silicide metal formed thereafter. The method may further comprise selectively removing the oxide barrier in the source/drain regions after forming the fully silicided (FUSI) gate. | 08-28-2008 |
20080230815 | Mitigation of gate to contact capacitance in CMOS flow - Sidewall spacers that are primarily oxide, instead of nitride, are formed adjacent to a gate stack of a CMOS transistor. Individual sidewall spacers are situated between a conductive gate electrode of the gate stack and a conductive contact of the transistor. As such, a capacitance can develop between the gate electrode and the contact, depending on the dielectric constant of the interposed sidewall spacer. Accordingly, forming sidewall spacers out of oxide, which has a lower dielectric constant than nitride, mitigates capacitance that can otherwise develop between these features. Such capacitance is undesirable, at least, because it can inhibit transistor switching speeds. Accordingly, fashioning sidewall spacers as described herein can mitigate yield loss by reducing the number of devices that have unsatisfactory switching speeds and/or other undesirable performance characteristics. | 09-25-2008 |
20090294867 | DUAL METAL GATES USING ONE METAL TO ALTER WORK FUNCTION OF ANOTHER METAL - Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to the damage from the metal etch process. | 12-03-2009 |
20120256270 | DUAL METAL GATES USING ONE METAL TO ALTER WORK FUNCTION OF ANOTHER METAL - Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to the damage from the metal etch process. | 10-11-2012 |
Craig H. Huffman, Krugerville, TX US
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20090057776 | METHOD OF FORMING FULLY SILICIDED NMOS AND PMOS SEMICONDUCTOR DEVICES HAVING INDEPENDENT POLYSILICON GATE THICKNESSES, AND RELATED DEVICE - A method of forming fully silicided NMOS and PMOS semiconductor devices having independent polysilicon gate thicknesses, and related device. At least some of the illustrative embodiments are methods comprising forming an N-type gate over a semiconductor substrate (the N-type gate having a first thickness), forming a P-type gate over the semiconductor substrate (the P-type gate having a second thickness different than the first thickness), and performing a simultaneous silicidation of the N-type gate and the P-type gate. | 03-05-2009 |
20090321846 | Method of Forming Fully Silicided NMOS and PMOS Semiconductor Devices Having Independent Polysilicon Gate Thicknesses, and Related Device - A method of forming fully silicided NMOS and PMOS semiconductor devices having independent polysilicon gate thicknesses, and related device. At least some of the illustrative embodiments are methods comprising forming an N-type gate over a semiconductor substrate (the N-type gate having a first thickness), forming a P-type gate over the semiconductor substrate (the P-type gate having a second thickness different than the first thickness), and performing a simultaneous silicidation of the N-type gate and the P-type gate. | 12-31-2009 |
Craig Henry Huffman, Krugerville, TX US
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20080233697 | Multiple-gate MOSFET device and associated manufacturing methods - One embodiment of the present invention relates to a method of fabricating a multi-gate transistor. During the method a second gate electrode material is selectively removed from a semiconductor structure from which the multi-gate transistor is formed, thereby exposing at least one surface of a first gate electrode material. The exposed surface of the first gate electrode material is deglazed. Subsequently, the first gate electrode material is removed. Other methods and devices are also disclosed. | 09-25-2008 |
20080268589 | SHALLOW TRENCH DIVOT CONTROL POST - The disclosure provides a method of manufacturing a semiconductor device. The method comprises forming a shallow trench isolation structure, including performing a wet etch process to remove a patterned pad oxide layer located on a semiconductor substrate. The wet etch thereby produces a divot on upper lateral edges of a insulator-filled trench in the semiconductor substrate. Forming the shallow trench isolation structure also includes forming a nitride post on a vertical wall of the divot. Forming the nitride post includes depositing a nitride layer on the insulator, and dry etching the nitride layer. The dry etch is selective towards the nitride located adjacent the vertical wall such that a portion of the nitride layer remains on the vertical wall subsequent to the dry etching. | 10-30-2008 |
Dana D. Huffman, Richardson, TX US
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20110030259 | Magazine and firearm with improved ammunition loading feature - A firearm magazine housing contains a spring to forcibly urge a follower with ammunition rounds stacked thereon toward an open end of the housing, thereby to facilitate delivery of the ammunition rounds into the firing chamber of a firearm. A follower support apparatus disposed within the housing supports the follower for movement in the housing, and permits the ammunition rounds to be stacked onto the follower independently of the spring. | 02-10-2011 |
20140283427 | Magazine and firearm with positional adjustment of magazine spring - A firearm magazine housing contains a spring to forcibly urge a follower with ammunition rounds stacked thereon toward an open end of the housing, thereby to facilitate delivery of the ammunition rounds into the firing chamber of a firearm. By a positional adjustment of the spring, the urging force that the spring applies to the follower during loading of ammunition rounds is reduced. | 09-25-2014 |
20160097608 | MAGAZINE AND FIREARM WITH POSITIONAL ADJUSTMENT OF MAGAZINE SPRING - Positional adjustment of a firearm magazine spring is supported by various instrumentalities. A magazine housing has therein a locking assembly carried on the magazine spring and cooperable with a sidewall of the housing to releasably lock the spring to the housing. Contact portions that engage the spring and permit application of compressive force to the spring are provided variously as part of: an apparatus separate from a firearm; a magazine well of a firearm; and a magazine insertion opening in a firearm that is separate from a magazine well of the firearm. | 04-07-2016 |
James D. Huffman, Plano, TX US
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20080304314 | Semiconductor Device and Method Comprising a High Voltage Reset Driver and an Isolated Memory Array - A method of operating a semiconductor device, a semiconductor device and a digital micromirror system are presented. In an embodiment, the semiconductor device comprises a grounded substrate, a memory array, and a reset driver. The memory array may be isolated from the grounded substrate with a buried layer. The set of voltages of the memory array may be shifted with respect to a reset voltage. The reset driver may drive the reset voltage and the reset driver may have at least one extended drain transistor in the grounded substrate. | 12-11-2008 |
20100202037 | System for On-Chip Actuation - In accordance with particular embodiments, a system for displaying modulated light includes a spatial light modulator comprising a plurality of micromirrors having a pixel pitch less than 17 micrometers. The system also includes an intermediate voltage generator operable to generate a negative voltage and a positive voltage. The system further includes at least two level shifters coupled to the intermediate voltage generator. The system additionally includes a reset driver coupled to the at least two level shifters and to at least a subset of the plurality of micromirrors. The reset driver is operable to drive the subset of the micromirrors. The spatial light modulator, the intermediate voltage generator, the at least two level shifters, and the reset driver are all incorporated on a common substrate. | 08-12-2010 |
James Douglas Huffman, Plano, TX US
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20160065058 | TWO-STATE CHARGE-PUMP CONTROL-LOOP FOR MEMS DVC CONTROL - The present invention generally relates to a DVC having a charge-pump coupled to a MEMS device. The charge-pump is designed to control the output voltage delivered to the electrodes, such as the pull-in electrode or the pull-off electrode, that move the switching element within the MEMS device between locations spaced far from and disposed closely to the RF electrode. | 03-03-2016 |
20160072408 | METHOD AND TECHNIQUE TO CONTROL MEMS DVC CONTROL WAVEFORM FOR LIFETIME ENHANCEMENT - The present invention generally relates to a method of operating a MEMS DVC while minimizing impact of the MEMS device on contact surfaces. By reducing the drive voltage upon the pull-in movement of the MEMS device, the acceleration of the MEMS device towards the contact surface is reduced and thus, the impact velocity is reduced and less damage of the MEMS DVC device occurs. | 03-10-2016 |
James Earl Huffman, Keller, TX US
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20090085524 | BATTERY CHARGING CIRCUIT - A circuit charges and maintains a battery. The circuit includes a microprocessor for receiving a current sense signal and a voltage sense signal. The microprocessor generates control signals for selectively operating the circuit in a charging mode and in a maintenance mode. The circuit includes a current sense circuit for measuring the battery's current consumption and generating the current sense signal responsive to the measured current consumption. The circuit includes a voltage sense circuit for measuring the battery's voltage and generating the voltage sense signal responsive to the measured battery voltage. The circuit includes a waveform generator circuit for receiving the control signals, and operating in response thereto to apply a charging signal to the battery when in the charging mode and to deactivate the charging signal when in the maintenance mode. The charging signal has an oscillating triangular waveform superimposed on a DC bias signal. | 04-02-2009 |
20090085525 | METHOD FOR CHARGING BATTERY - A method for charging a battery includes measuring the battery's voltage and comparing the battery voltage to a first threshold voltage. The method includes operating the battery in a charging mode if the measured battery voltage is less than the first threshold voltage, wherein operating in the charging mode comprises applying a charging signal to the battery. The charging signal has an oscillating triangular waveform superimposed on a DC bias signal. The method includes measuring the battery's current consumption and comparing the current consumption to a first threshold current. The method includes operating in a maintenance mode if the battery's current consumption is less than the first threshold current, wherein operating in the maintenance mode comprises terminating application of the charging signal to the battery. The method includes measuring, during operation in the maintenance mode, the battery's voltage and comparing the measured voltage to a second threshold voltage. The method includes applying the oscillating triangular waveform superimposed on the DC bias signal until the battery's voltage is equal to or greater than the second threshold voltage. | 04-02-2009 |
20090085526 | CIRCUIT FOR GENERATING TRIANGULAR WAVEFORM HAVING RELATIVELY SHORT LINEAR RISE TIME AND SUBSTANTIALLY LONG LINEAR FALL TIME - A circuit includes a pulse transformer having primary and secondary windings. An oscillating waveform is applied to the primary winding to induce an oscillating waveform at the secondary winding. A transistor in series with a first resistor is coupled between the secondary winding and the ground. An R-C network formed by a second and a third resistor and a capacitor is coupled to a base junction of the transistor. The R-C network causes a slow, tapered linear pinch off of the transistor's conductance to enable the circuit to output a triangular waveform, which is characterized by a relatively short linear rise time followed by a substantially long linear fall time. The R-C network is coupled to the secondary winding via a first and a second diode, respectively. | 04-02-2009 |
20120299533 | CIRCUIT AND METHOD ENABLING THE SHARING OF A BATTERY CHARGER WITH MULTIPLE BATTERIES - A circuit includes a first port configured for connection to a battery charger and a plurality of second ports each configured for connection to a battery to be charged. The circuit includes a corresponding switchable circuit path provided between the first port and each of the second ports. A control circuit is configured to selectively activate the switchable circuit paths so as to connect the first port to selected ones of the second ports for charging of the connected battery by the connected battery charger. | 11-29-2012 |
Jeremy K. Huffman, Amarillo, TX US
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20130244160 | LOW STRUCTURE CARBON BLACK AND METHOD OF MAKING SAME - A carbon black having an I | 09-19-2013 |
Joann Huffman, Austin, TX US
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20090051490 | METHODS AND SYSTEMS TO IMPROVE RFID INVENTORY POLLING ACCURACY - Methods, systems, and media to improve polling accuracy in RFID systems are disclosed. Embodiments comprise receiving information from one or more tags by a tag reader, comparing the information from the tags to other information, and adding the tag to an inventory if the tag does not exist in the other information. While some embodiments compare the tag information from the tags to baseline inventories for other areas, some embodiments compare it to current inventories for the other areas or compare it to a combination of both inventories. Some embodiments involve polling RFID tags in storage containers. Other embodiments involve machine-accessible mediums with instructions to receive information from the tag reader, analyze the information with baseline and current inventories of other areas, and store identification information for the tag in a current inventory database if the information is absent from the baseline and current inventories. | 02-26-2009 |
20090315677 | Container Manifest Integrity Maintenance System and Method - A system, method, and medium for tracking the contents of a container in which the items stored in the container are provided with radio frequency identification (“RFID”) tags, and a tracker affixed to the container periodically polls the items in the container to collect identification information. An electronic manifest, also attached to the container, is updated periodically to reflect items which have been added to the container or removed from the container since the last polling. The tracker emulates an RFID tag when polled by an external reader, responding by uploading the entire electronic manifest to the external reader. The external reader and the affixed reader preferably utilize distinct RFID protocols so as to produce a hierarchical manifest data structure with high integrity. | 12-24-2009 |
Robert Kenneth Huffman, Bandera, TX US
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20160026895 | Alerting system for automatically detecting, categorizing, and locating animals using computer aided image comparisons - Described are systems for (a) monitoring real-time animal activity in an area of interest using computer aided image comparison of a real-time image of the area and reference images of animals of interest and (b) providing informed alerts to a user. | 01-28-2016 |