Yutaka Akiyama
Yutaka Akiyama, Tokyo JP
Patent application number | Description | Published |
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20080310521 | Signal transmission circuit and signal transmission system - A signal transmission circuit includes a transmitting circuit for outputting a transmitting signal to a transmission line, a parallel circuit including a capacitor and a first resistance connected between an output terminal of the transmitting circuit and the transmission line, and a series circuit including an inductor and a second resistance connected between an output side of the parallel circuit and a ground. | 12-18-2008 |
20080316136 | Antenna apparatus utilizing aperture of transmission line - An antenna apparatus utilizing an aperture of transmission line, which is connected to a first transmission line having a predetermined characteristic impedance, includes a tapered line portion, and an aperture portion. The tapered line portion is connected to one end of the transmission line, and the tapered line portion includes a second transmission line including a pair of line conductors. The tapered line portion keeps a predetermined characteristic impedance constant and expands at least one of a width of the transmission line and an interval in a tapered shape at a predetermined taper angle. The aperture portion has a radiation aperture connected to one end of the tapered line portion. A size of one side of the aperture end plane of the aperture portion is set to be equal to or higher than a quarter wavelength of the minimum operating frequency of the antenna apparatus. | 12-25-2008 |
20090072358 | Semiconductor Integrated Circuit Package, Printed Circuit Board, Semiconductor Apparatus, and Power Supply Wiring Structure - A semiconductor integrated circuit package, a printed circuit board, a semiconductor apparatus, and a power supply wiring structure that allow attainment of stable power source and ground wiring without causing resonance even in a high-frequency bandwidth are provided. In an interior portion of the package, a power source wiring and a ground wiring constitute a pair wiring structure in which the power source wiring and the ground wiring are juxtaposed at a predetermined interval so as to establish electromagnetic coupling therebetween. A plurality of pair wiring structures are combined in such a manner that, when viewed in a section perpendicular to a wiring extending direction, the pair wiring assembly assumes a staggered (checkered) configuration. It is preferable that, each of the silicon chip and the printed circuit board, like the package, has pair wiring structures disposed inside. | 03-19-2009 |
20100013318 | PRINTED CIRCUIT BOARD - A printed circuit board includes a ground layer, a power source layer, a signal wiring layer, an insulating layer and an electromagnetic radiation suppressing member. The power source layer is provided to be opposed to the ground layer. The signal wiring layer transmits a signal in a predetermined frequency domain. The insulating layer insulates the ground layer, the power source layer and the signal wiring layer from one another. The electromagnetic radiation suppressing member is provided to cover a circumferential edge of the insulating layer. The electromagnetic radiation suppressing member has a negative dielectric constant and a positive magnetic permeability in a frequency domain including the predetermined frequency domain. | 01-21-2010 |
20100289156 | SEMICONDUCTOR DEVICE - According to an aspect of the invention, a semiconductor device includes a substrate having an opening area, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip has a first electrode for high-speed communication and that is disposed around the opening area on the substrate. The second semiconductor chip has a second electrode and third electrode for power and low-speed communication and that is disposed on the first semiconductor chip so that the first electrode is coupled with the second electrode by electrostatic coupling and dielectric coupling, the third electrode facing the opening area. | 11-18-2010 |
20110042120 | WIRING AND COMPOSITE WIRING - A wire (a twisted pair cable) that transmits a gigahertz band signal and that is provided with a pair of core wires that are twisted with each other, a first insulation coating material, a second insulation coating material, and a shield material that shields evanescent waves emitted from the pair of core wires. The pair of core wires have a twisting pitch, a diameter, and a spacing so that the wire has a characteristic impedance of 100 to 200Ω and the phases of the TEM (Transverse Electro-Magnetic) wave and the evanescent wave that are emitted from the pair of core wires are matched. | 02-24-2011 |
20110073352 | PAIRED LOW-CHARACTERISTIC IMPEDANCE POWER LINE AND GROUND LINE STRUCTURE - Disclosed is a paired low-characteristic impedance power line and ground line structure in which loop inductance is substantially 0. The paired low-characteristic impedance power line and ground line structure includes a laminated sheet in which a metal wiring layer having a power line and a ground line is provided on the surface of an insulating sheet, an insulating thin-film layer provided so as to cover the power line and the ground line, and a resistive layer provided on the surface of the insulating thin-film layer. | 03-31-2011 |
20150070957 | SEMICONDUCTOR DEVICE AND METHOD OF WRITING/READING ENTRY ADDRESS INTO/FROM SEMICONDUCTOR DEVICE - The semiconductor device of the present invention includes a search memory mat having a configuration in which a location with which an entry address is registered is allocated in a y-axis direction, and key data is allocated in an x-axis direction and a control circuit connected to the search memory mat. In the search memory mat, a plurality of separate memories is formed such that a region to which the key data is allocated is separated into a plurality of regions along the y-axis direction. The control circuit includes an input unit to which the key data is input, a division unit which divides the key data input to the input unit into a plurality of pieces of key data, and a writing unit which allocates each piece of divided key data by the division unit into the separate memory using the divided key data as an address. | 03-12-2015 |
Yutaka Akiyama, Kawasaki JP
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20080303914 | IMAGE SENSOR ARRAY ARCHITECTURE FOR IMPROVED RESOLUTION SWITCHING - An image sensor array is provided with: a first CCD image sensor configured to output a plurality of first signal voltages from a first output terminal; a second CCD image sensor configured to output a plurality of second signal voltages from a second output terminal; a switch circuit selectively connecting one of the first and second output terminals to a signal voltage output terminal; and a timing generator circuit responsive to a basic clock for generating first and second control signals and switch control signals. The first and second control signals are used for controlling generation of the plurality of first and second signal voltages, respectively. The switch control signals are used for controlling the switch circuit. The timing generator circuit controls the first and second CCD image sensors so that the first and second CCD image sensors output the plurality of first signal voltages and the plurality of second signal voltages, alternately. The timing generator circuit controls the switch circuit so that switch circuit outputs from the signal voltage output terminal one of the plurality of first signal voltages and one of the plurality of second signal voltages, alternately. | 12-11-2008 |
20100102420 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - To provide a semiconductor device in which an interval between first wells can be shortened by improving a separation breakdown voltage between the first wells and a method for manufacturing the same. A semiconductor device includes a first conductivity type semiconductor substrate | 04-29-2010 |
Yutaka Akiyama, Hachioji JP
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20090108955 | Semiconductor Device and Method for Adjusting Characteristics Thereof - The object of the invention is to provide a semiconductor device including signal-transmission interconnections preferable for transmitting high frequency signal and capability to adjust characteristics of the above signal-transmission interconnections. A semiconductor device according to the present invention consists of a signal-transmission interconnection | 04-30-2009 |
Yutaka Akiyama, Hachioji-Shi JP
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20110255323 | MEMORY/LOGIC CONJUGATE SYSTEM - There is a problem that a bandwidth bottleneck occurs because a crossbar switch is used to cope with an increase in scale. In an example of a memory/logic conjugate system according to the present invention, a plurality of cluster memory chips each including a plurality of cluster memories | 10-20-2011 |
20130061004 | MEMORY/LOGIC CONJUGATE SYSTEM - In a memory/logic conjugate system, a plurality of cluster memory chips each including a plurality of cluster memories ( | 03-07-2013 |
Yutaka Akiyama, Kanagawa JP
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20140264722 | SEMICONDUCTOR DEVICE - A semiconductor chip includes a first circuit and a second circuit having different reference potentials. A first potential which is a reference potential of the first circuit is applied to the semiconductor chip through any of plural lead terminals, and a second potential which is a reference potential of the second circuit is applied to the semiconductor chip through any of plural lead terminals. A substrate of the semiconductor chip has a structure in which a buried insulating layer and a semiconductor layer of a first conductivity type are laminated on a semiconductor substrate such as a SOI substrate. A fixed potential is applied to the semiconductor substrate through a die pad and a lead terminal for a substrate potential. The fixed potential is applied to the semiconductor chip through a different route from the reference potential of the first circuit and the reference potential of the second circuit. | 09-18-2014 |
20150060948 | SEMICONDUCTOR DEVICE - A field plate causes excessive gate capacitance that interferes with high-speed transistor switching. To suppress the excessive gate capacitance, an aperture includes a first side wall positioned on the side of a drain electrode, and a second side wall positioned on the side of a source electrode. A gate electrode at the same time includes a first side surface facing opposite the drain electrode as seen from a plan view. The first side surface of the gate electrode is positioned on the inner side of the first side wall and the second side wall as seen from a flat view. Moreover, a portion of a first field plate is embedded between the first side surface and the first side wall. The gate electrode and the first field plate are electrically insulated by a first insulation member. | 03-05-2015 |
Yutaka Akiyama, Kawasaki-Shi JP
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20140284709 | SEMICONDUCTOR DEVICE - A buried layer of a second conductivity type and a lower layer of a second conductivity type are formed in a drift layer. A boundary insulating film is formed in the boundary between the lateral portion of the buried layer of a second conductivity type and the drift layer. The lower layer of a second conductivity type is in contact with the lower end of the buried layer of a second conductivity type and the lower end of the boundary insulating film. The buried layer of a second conductivity type is electrically connected to a source electrode. A high-concentration layer of a second conductivity type is formed in the surface layer of the buried layer of a second conductivity type. | 09-25-2014 |
20140312440 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - An object of the present invention is to suppress an error in the value detected by a pressure sensor, which may be caused when environmental temperature varies. A semiconductor substrate has a first conductivity type. A semiconductor layer is formed over a first surface of the semiconductor substrate. Each of resistance parts has a second conductivity type, and is formed in the semiconductor layer. The resistance parts are spaced apart from each other. A separation region is a region of the first conductivity type formed in the semiconductor layer, and electrically separates the resistance parts from each other. A depressed portion is formed in a second surface of the semiconductor substrate, and overlaps the resistance parts, when viewed planarly. The semiconductor layer is an epitaxial layer. | 10-23-2014 |