Patent application number | Description | Published |
20110017971 | INTEGRATED CIRCUIT DEVICES INCLUDING LOW-RESISTIVITY CONDUCTIVE PATTERNS IN RECESSED REGIONS - An integrated circuit device includes a device isolation pattern on a semiconductor substrate to define an active area therein. The active area includes a doped region therein. A conductive pattern extends on the active area and electrically contacts the doped region. The conductive pattern has a lower resistivity than the doped region. The conductive pattern may be disposed in a recessed region having a bottom surface lower than a top surface of the active area. A channel pillar electrically contacts to the doped region and extends therefrom in a direction away from the substrate. A conductive gate electrode is disposed on a sidewall of the channel pillar, and a gate dielectric layer is disposed between the gate electrode and the sidewall of the channel pillar. | 01-27-2011 |
20110101445 | SUBSTRATE STRUCTURES INCLUDING BURIED WIRING, SEMICONDUCTOR DEVICES INCLUDING SUBSTRATE STRUCTURES, AND METHOD OF FABRICATING THE SAME - A semiconductor device includes a substrate structure including a first substrate and a second substrate, and a buried wiring interposed between the first substrate and the second structure, where the buried wiring is in direct contact with the second substrate. The semiconductor device further includes a vertical transistor located in the second substrate of the substrate structure. The vertical transistor includes a gate electrode and a semiconductor pillar, and the buried wiring is one of source electrode or a drain electrode of the vertical transistor | 05-05-2011 |
20110111568 | METHODS OF FABRICATING VERTICAL CHANNEL TRANSISTORS - Methods of fabricating vertical channel transistors may include forming an active region on a substrate, patterning the active region to form vertical channels at sides of the active region, forming a buried bit line in the active region between the vertical channels, and forming a word line facing a side of the vertical channel. | 05-12-2011 |
20110143508 | METHOD OF FABRICATING VERTICAL CHANNEL TRANSISTOR - A method of fabricating a vertical channel transistor includes: forming a line type active pattern on a substrate so as to extend in a first horizontal direction; forming a vertical channel isolating the active pattern in a second horizontal direction intersecting the first horizontal direction and extending vertically on the substrate; | 06-16-2011 |
20110156119 | SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FORMING THE SAME - Semiconductor memory devices and methods of forming the same are provided, the semiconductor memory devices include a first and a second buried gate respectively disposed on both inner sidewalls of a groove formed in an active portion and a device isolation pattern. The first and second buried gates are controlled independently from each other. | 06-30-2011 |
20110220977 | SEMICONDUCTOR DEVICES WITH BURIED BIT LINES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES - A semiconductor device, comprising: a vertical pillar transistor (VPT) formed on a silicon-on-insulator (SOI) substrate, the VPT including a body that has a lower portion and an upper portion, a source/drain node disposed at an upper end portion of the upper portion of the body and a drain/source node disposed at the lower portion of the body; a buried bit line (BBL) formed continuously on sidewalls and an upper surface of the lower portion, the BBL includes metal sificide; and a word line that partially enclosing the upper portion of the body of the VPT, wherein the BBL extends along a first direction and the word line extends in a second direction substantially perpendicular to the first direction. An offset region is disposed immediately beneath the word line. | 09-15-2011 |
20110223731 | Vertical Channel Transistors And Methods For Fabricating Vertical Channel Transistors - Provided are a vertical channel transistor and a method for fabricating a vertical channel transistor. The method includes forming an active layer on a substrate, forming a plurality of vertical channels on the active layer, forming a plurality of isolated gate electrodes to surround sidewalls of the plurality of vertical channels, forming a buried bitline to extend along the active layer between the plurality of vertical channels, forming a plug-in between the plurality of vertical channels to connect the plurality of isolated gate electrodes and forming a wordline on a location where the plug-in and the plurality of isolated gate electrodes are connected. | 09-15-2011 |
20110303974 | INTEGRATED CIRCUIT DEVICES INCLUDING VERTICAL CHANNEL TRANSISTORS WITH SHIELD LINES INTERPOSED BETWEEN BIT LINES AND METHODS OF FABRICATING THE SAME - An integrated circuit device includes a plurality of pillars protruding from a substrate in a first direction. Each of the pillars includes source/drain regions in opposite ends thereof and a channel region extending between the source/drain regions. A plurality of conductive bit lines extends on the substrate adjacent the pillars in a second direction substantially perpendicular to the first direction. A plurality of conductive shield lines extends on the substrate in the second direction such that each of the shield lines extends between adjacent ones of the bit lines. Related fabrication methods are also discussed. | 12-15-2011 |
20120007208 | Semiconductor Devices and Methods of Manufacturing the Same - Semiconductor devices and methods of manufacturing the same are provided. The semiconductor devices may include first and second active patterns. The second active patterns may protrude from the first active patterns. The semiconductor devices may also include a device isolation pattern between each of the first active patterns. The semiconductor devices may further include a sidewall mask on the first active patterns and the second active patterns. The semiconductor devices may additionally include a buried conductive pattern on the device isolation pattern. | 01-12-2012 |
20120153379 | SEMICONDUCTOR DEVICES WITH VERTICAL CHANNEL TRANSISTORS - Semiconductor devices with vertical channel transistors, the devices including semiconductor patterns disposed on a substrate, first gate patterns disposed between the semiconductor patterns on the substrate, a second gate pattern spaced apart from the first gate patterns by the semiconductor patterns, and conductive lines crossing the first gate patterns. The second gate pattern includes a first portion extending parallel to the first gate patterns and a second portion extending parallel to the conductive lines. | 06-21-2012 |