Patent application number | Description | Published |
20080303557 | CIRCUITS FOR FORMING THE INPUTS OF A LATCH - Circuits for forming the inputs of a latch are provided. In some embodiments, circuits for forming inputs of a latch comprise: a first transistor having a first gate terminal, a first drain terminal, a first source terminal, a first gate length, and a first common mode level at the first gate terminal, wherein the first gate terminal provides a data input to the latch; and a second transistor having a second gate terminal, a second drain terminal, a second source terminal, a second gate length, and a second common mode level at the second gate terminal, wherein the second gate terminal provides a clock input to the latch, the second drain terminal is coupled to the first source terminal, and the first gate length and the second gate length are sized so that the first common model level and the second common mode level are substantially equal. | 12-11-2008 |
20100259107 | Systems and Methods for Providing Power to a Device Under Test - Systems and methods for providing power to a device under test are prcn ided. In some embodiments, systems for providing power to a device under test are provided, the systems comprising a power source for providing an alternating current, a probe having a probe inductor coupled to the power source; and a device under test having a device inductor magnetically coupled to the probe inductor, and having a circuit to be tested that receives power produced in the device inductor, In some embodiments, devices that receive power from a probe having an inductor that is coupled to an alternating current power source are provided, the devices comprising: a device inductor magnetically coupled to the probe inductor; and a circuit to be tested that receives power produced in the device inductor. | 10-14-2010 |
20110076961 | Systems and Methods for Controlling the Second Order Intercept Point of Receivers - In accordance with some embodiments, methods for controlling the second order intercept point in a receiver are provided, the methods comprising: generating an amplitude modulated test tone; causing the test tone to be received by a receiver; determining a characteristic of a second order intercept point of the receiver based on the received test tone; and based on the characteristic, adjusting a parameter of the receiver. In accordance with some embodiments, systems for controlling the second order intercept point in a receiver are provided, the systems comprising: a test tone generator that generates an amplitude modulated test tone; a receiver that receives the test tone; a correlator that determines a characteristic of a second order intercept point of the receiver based on the received test tone; and digital logic that, based on the characteristic, adjusts a parameter of the receiver. | 03-31-2011 |
20110124307 | Systems and Methods for Cancelling Interferers in a Receiver - In some embodiments, systems and methods for cancelling interferers in a receiver, comprise: a first mixer in a main path that downconverts a first RF signal to form a main baseband or intermediate-frequency signal; and a second mixer in an alternate path that downconverts a second RF signal to form an alternate baseband or intermediate-frequency signal, wherein the first RF signal and the second RF signal are both based on a third RF signal, and wherein the main baseband or intermediate-frequency signal and the alternate baseband or intermediate-frequency signal, when combined, cancel out an interferer in the third RF signal. | 05-26-2011 |
20120275549 | Systems and Methods for Wirelessly Receiving Data - In accordance with some embodiments, receivers for receiving a wireless data transmission are provided, the receivers comprising at least one amplifier that receives an RF input signal and produces at least one amplified signal; a mixer that mixes the at least one signal to produce a mixed signal; a filter that filters the mixed signal to produce a filtered signal, a comparator that compares the filtered signal to a threshold voltage and produces a digital signal, a first pulse generate i that generates a first pulse in response to a transition in the digital signal, a second pulse generator that generates a second pulse that is longer than the first pulse in response to a transition in the digital signal; and digital logic that generates a clock output and that generates a data output based on a state of the first pulse when the second pulse expires. | 11-01-2012 |
20140132438 | Circuits and Methods for Implementing a Residue Amplifier - Circuits and methods for implementing a residue amplifier are provided. In some embodiments, circuits for implementing a residue amplifier are provided, the circuits comprising: a first capacitor configured to be charged to an input voltage level and that discharges from the input voltage level to a reference voltage level; a comparator having a first input coupled to the first capacitor, a second input coupled to a reference voltage source, and an output that indicates when the charge on the first capacitor is above the reference voltage level; and a second capacitor configured to be charged to an output voltage based on the output of the comparator. | 05-15-2014 |
20140197971 | SYSTEMS AND METHODS FOR PROVIDING A PIPELINED ANALOG-TO-DIGITAL CONVERTER - Systems comprising: a first MDAC stage comprising: a sub-ADC that outputs a value based on an input signal; at least two reference capacitors that are charged to a Vref; at least two sampling capacitors that are charged to a Vin; and a plurality of switches that couple the at least two reference capacitors so that they are charged during a sampling phase, that couple the at least two sampling capacitors so that they are charged during the sampling phase, that couple at least one of the reference capacitors so that it is parallel to one of the at least two sampling capacitors during a hold phase, and that couple the other of the at least two sampling capacitors so that it couples the at least one of the reference capacitors and the one of the at least two sampling capacitors to a reference capacitor of a second MDAC stage. | 07-17-2014 |
20150056937 | SYSTEMS AND METHODS FOR CONTROLLING THE SECOND ORDER INTERCEPT POINT OF RECEIVERS - In accordance with some embodiments, methods for controlling the second order intercept point in a receiver are provided, the methods comprising: generating an amplitude modulated test tone; causing the test tone to be received by a receiver; determining a characteristic of a second order intercept point of the receiver based on the received test tone; and based on the characteristic, adjusting a parameter of the receiver. In accordance with some embodiments, systems for controlling the second order intercept point in as receiver are provided, the systems comprising: a test tone generator that generates an amplitude modulated test tone; a receiver that receives the test tone; a correlator that determines a characteristic of a second order intercept point of the receiver based on the received test tone; and digital logic that, based on the characteristic, adjusts a parameter of the receiver. | 02-26-2015 |