Patent application number | Description | Published |
20080303509 | PHASE MEASUREMENT APPARATUS, SKEW MEASUREMENT APPARATUS, PHASE MEASUREMENT METHOD, AND SKEW MEASUREMENT METHOD - There is provided a phase measurement apparatus for measuring a phase of a signal under measurement. The phase measurement apparatus includes a sampling section that samples the signal under measurement at timings indicated by a sampling clock supplied thereto, a jitter injecting section that injects jitter to at least one of the signal under measurement which is to be input into the sampling section and the sampling clock, and a phase calculating section that calculates the phase of the signal under measurement based on a result of the sampling performed by the sampling section. | 12-11-2008 |
20080304608 | TEST APPARATUS, AND DEVICE FOR CALIBRATION - The test apparatus includes a first comparator and a second comparator that measure a measured signal output from the device under test at a given sampling clock timing, a deciding section that decides a quality of the device under test on the basis of a measurement result in the first comparator and the second comparator, a control section that causes the first comparator and the second comparator to input an adjustment signal having a previously injected jitter and respectively sample the input signal, a skew computing section that computes a skew between the first comparator and the second comparator on the basis of sampling results, and a phase adjusting section that adjusts a phase of at least any one of the measured signal and the sampling clock in at least any one of the first comparator and the second comparator on the basis of the skew. | 12-11-2008 |
20080310489 | COMMUNICATION SYSTEM, RECEIVER UNIT, AND ADAPTIVE EQUALIZER - A communication system in which a signal is transferred includes a transmitter that transmits a signal, a receiver that receives a signal transmitted thereto, and an adaptive equalizer that generates a compensated signal by compensating degradation of the signal to be received by the receiver. The adaptive equalizer includes a signal compensating section that generates the compensated signal by passing therethrough the signal to be received by the receiver, a jitter measuring section that measures jitter of the compensated signal output from the signal compensating section, and an adjusting section that adjusts a characteristic of the signal compensating section so as to reduce the jitter of the compensated signal which is measured by the jitter measuring section. | 12-18-2008 |
20090103672 | TRANSMISSION SYSTEM, TRANSMITTER, RECEIVER, AND TRANSMISSION METHOD - There is provided a circuit constituted by small-sized and simple logical gates which reduces the bit errors generated in a data sequence received by a receiver. A transmission system, in which a data sequence is transferred, includes a transmitter that transmits a first transfer signal including an edge-present data waveform which has (i) a first timing edge indicating a timing to obtain data included in the data sequence and (ii) a level signal indicating a signal level corresponding to a value of the data, and a receiver that outputs the value of the data in accordance with the signal level which is detected at the timing indicated by the first timing edge of the edge-present data waveform. | 04-23-2009 |
20090132884 | TIMING GENERATOR AND SEMICONDUCTOR TESTING APPARATUS - A timing generator that needs no analog circuit for adding jitters and allows the circuit scale and power consumption to be reduced. There are included a counter for performing a counting operation synchronized with a reference clock signal: a timing memory for outputting respective data corresponding to the quotient and remainder resulting from dividing the time from the front of a basic period until a generation of a timing edge by the period of the reference clock signal: a coincidence detecting circuit for outputting a signal that exhibits a high level when the count value of the counter coincides with the quotient: a jitter generating circuit for outputting as a jitter amplitude value: adders for adding a time corresponding to the remainder and a time represented by the jitter amplitude value outputted from the jitter generating circuit: and a variable delay circuit for delaying the output signal from the coincidence detecting circuit by the time represented by the addition result of the adders and outputting the delayed output signal. | 05-21-2009 |
20090189666 | JITTER INJECTION CIRCUIT, PATTERN GENERATOR, TEST APPARATUS, AND ELECTRONIC DEVICE - Provided is a jitter injection circuit that generates a jittery signal including jitter, including a plurality of delay circuits that receive a supplied reference signal in parallel and that each delay the received reference signal by a preset delay amount and a signal generating section that generates each edge of the jittery signal according to a timing of the signal output by each delay circuit. In the jitter injection circuit the delay amount of at least one delay circuit is set to be a value different from an integer multiple of an average period of the jittery signal. | 07-30-2009 |
20090189667 | JITTER INJECTION CIRCUIT, PATTERN GENERATOR, TEST APPARATUS, AND ELECTRONIC DEVICE - Provided is a jitter injection circuit that generates a jittery signal including jitter, including a plurality of delay circuits that are connected in a cascading manner and that each sequentially delay a supplied reference signal by a preset delay amount and a signal generating section that generates each edge of the jittery signal according to a timing of the signal output by each delay circuit. In the jitter injection circuit the delay amount of at least one delay circuit is set to be a value different from an integer multiple of an average period of the jittery signal. | 07-30-2009 |
20090207897 | MEASURING APPARATUS, TEST APPARATUS, RECORDING MEDIUM, PROGRAM AND ELECTRONIC DEVICE - There is provided a measuring apparatus for measuring a signal-to-noise ratio of a discrete waveform which is output from an AD converter in response to an input signal, where the signal-to-noise ratio indicates a ratio of a signal component of the input signal to noise generated by the AD converter. The measuring apparatus includes a spectrum compensating section that receives a spectrum of the discrete waveform output from the AD converter, and compensates the received spectrum in accordance with a non-symmetric sideband between an upper sideband and a lower sideband of the received spectrum, where the upper and lower sidebands are defined with respect to a fundamental frequency of the input signal, and a phase noise waveform calculating section that calculates a phase noise waveform of the discrete waveform based on the spectrum which has been compensated by the spectrum compensating section. | 08-20-2009 |
20090281747 | SIGNAL MEASUREMENT APPARATUS, SIGNAL MEASUREMENT METHOD, RECORDING MEDIA AND TEST APPARATUS - Provided is a signal measurement apparatus, including sampling sections that each sample a signal under measurement having a cycle T with a threshold value, where the threshold values of at least two of the sampling sections are different from each other; a waveform reconfiguring section that shapes a reconfigured waveform having the cycle T by rearranging ordinal ranks of sample values corresponding to each threshold value obtained by the sampling sections, a distribution generating section that generates a timing distribution of edges in the reconfigured waveform corresponding to each threshold value; and a calculating section that calculates rise time or fall time of the signal under measurement based on the timing distribution corresponding to each threshold value. | 11-12-2009 |
20090281751 | JITTER MEASUREMENT APPARATUS, JITTER MEASUREMENT METHOD, RECORDING MEDIA, COMMUNICATION SYSTEM AND TEST APPARATUS - Provided is a jitter measurement apparatus, including a sampling section that samples a signal under measurement having a cycle T, a waveform reconfiguring section that shapes a reconfigured waveform having the cycle T by rearranging ordinal ranks of sample values sampled by the sampling section, a distribution generating section that generates a timing distribution of edges in the reconfigured waveform, and a statistical value calculating section that calculates a statistical value of the timing distribution. The sampling section may sample the signal under measurement having the cycle T a certain number of times N while the signal under measurement repeats for M cycles, where M and N are coprime. | 11-12-2009 |
20090281752 | SKEW MEASUREMENT APPARATUS, SKEW MEASUREMENT METHOD, RECORDING MEDIA AND TEST APPARATUS - Provided is a skew measurement apparatus, including sampling sections that each sample one of a plurality of signals under measurement having a cycle T, a waveform reconfiguring section that shapes a reconfigured waveform having the cycle T by rearranging ordinal ranks of sample values of the signal under measurement sampled by each sampling section, a distribution generating section that generates a timing distribution of edges in the reconfigured waveform of the corresponding signal under measurement, and a skew calculating section that calculates skew between the signals under measurement being compared based on the timing distribution of each signal under measurement. | 11-12-2009 |
20090304053 | DIGITAL MODULATOR, DIGITAL MODULATING METHOD, DIGITAL TRANSCEIVER SYSTEM, AND TESTING APPARATUS - Provided is a digital modulator, including a carrier wave output section that outputs a carrier wave, a variable delay section that delays the carrier wave, and a delay amount setting section that sets a delay amount by which the variable delay section delays the carrier wave based on transmission data being transmitted by the carrier wave. The variable delay section may include a multi-stage delay buffer circuit in which delay buffers that delay an input signal by a unit shift amount are connected in a cascade connection, the multi-stage delay buffer circuit may receive the carrier wave at a first-stage delay buffer as input, and the delay amount setting section may include a multiplexer that selects either an output from the carrier wave output section or an output from each stage of the multi-stage delay buffer circuit. | 12-10-2009 |
20100106470 | DETERMINISTIC COMPONENT IDENTIFYING APPARATUS, IDENTIFYING, PROGRAM, RECORDING MEDIUM, TEST SYSTEM AND ELECTRONIC DEVICE - Provided is a deterministic component identifying apparatus that identifies a distribution shape of a deterministic component included in a probability density function supplied thereto, comprising a standard deviation calculating section that calculates a standard deviation of the probability density function; a spectrum calculating section that calculates a spectrum of the probability density function; a null frequency detecting section that detects a null frequency of the spectrum; and a ratio calculating section that calculates a ratio between a top portion and a bottom portion of a distribution of the deterministic component, based on the standard deviation of the probability density function and the null frequency of the spectrum. | 04-29-2010 |
20100107020 | CALCULATION APPARATUS, CALCULATION METHOD, PROGRAM, RECORDING MEDIUM, TEST SYSTEM AND ELECTRONIC DEVICE - Provided is a calculating apparatus that calculates a characteristic of a target signal, comprising a designating section that receives a designation of either a bit error rate or a sampling timing; and a calculating section that calculates a range of sampling timings over which the bit error rate is less than a designated value or a bit error rate at a designated sampling timing by using a relational expression between the sampling timing and the bit error rate in a transmission model for transmitting a signal having jitter that includes a random component and a deterministic component having a prescribed probability density distribution, the relational expression achieved by substituting, as parameters, a standard deviation of a random component in jitter of the target signal and a peak-to-peak value of a deterministic component in the jitter of the target signal. | 04-29-2010 |
20110054827 | TEST APPARATUS AND METHOD FOR MODULATED SIGNAL - A test apparatus tests a modulated signal under test received from a DUT. A cross timing data generating unit generates cross timing data which indicates a timing at which the level of the signal under test crosses each of multiple thresholds. An expected value data generating unit generates timing expected value data which indicates a timing at which an expected value waveform of the signal under test crosses each of the multiple thresholds when the expected value waveform is compared with each of the multiple thresholds. A timing comparison unit compares the cross timing data with the timing expected value data. | 03-03-2011 |
20110181308 | TEST APPARATUS AND TESTING METHOD - A main power supply supplies a power supply voltage to a power supply terminal of a DUT. A control pattern generator generates a control pattern including a pulse sequence. A compensation circuit intermittently injects a compensation current to the power supply terminal of the DUT via a path different from that of the main power supply. A switch is arranged between an output terminal of a voltage source and the power supply terminal of the DUT, and is turned on and off according to the control pattern. | 07-28-2011 |
20120086462 | TEST APPARATUS - A power supply compensation circuit generates a compensation pulse current when a switch element is turned on. A pattern generator generates a test pattern that specifies a test signal to be output from a driver and a control signal to be output from the driver. In a calibration step, a voltage measurement unit measures the power supply voltage. A current adjustment unit adjusts the compensation pulse current to be generated in a test step after the calibration step. | 04-12-2012 |
20120112783 | TEST APPARATUS - A test apparatus tests a DUT formed on a wafer. A power supply compensation circuit includes source and a sink switches each controlled according to a control signal. When the source or sink switch is turned on, a compensation pulse current is generated, and the compensation pulse current is injected into a power supply terminal of the DUT via a path that differs from that of a main power supply, or is drawn from the power supply current that flows from the main power supply to the DUT via a path that differs from that of the power supply terminal of the DUT. Of components forming the power supply compensation circuit, including the source and sink switches, a part is formed on the wafer. Pads are formed on the wafer in order to apply a signal to such a part of the power supply compensation circuit formed on the wafer. | 05-10-2012 |
20120146416 | TEST APPARATUS - A DUT comprises a notifying circuit configured to generate a notification signal which is used to notify an external circuit of an event that leads to a change in the operating current of the DUT before such an event occurs. A main power supply supplies electric power to a power supply terminal of the DUT. A power supply compensation circuit comprises a switch element which is controlled according to a control signal, and is configured to generate a compensation pulse current according to the on/off state of the switch element. A compensation control circuit receives the notification signal from the DUT, and outputs, to the power supply compensation circuit, a control signal which is used to control the switch element, and which is generated based upon at least the notification signal. | 06-14-2012 |
20120323519 | TEST APPARATUS - A pattern generator PG generates control data which specifies a threshold voltage to be compared with a signal under test input to an I/O terminal, and generates expected value data which represents an expected value for the comparison result between the signal under test and the threshold voltage. A threshold voltage generator generates the threshold voltage having a voltage level that corresponds to the control data at every setting timing indicated by a first timing signal. A level comparator compares the voltage level of the signal under test with its corresponding threshold voltage. A timing comparator latches the output of the level comparator at a strobe timing indicated by a second timing signal so as to generate a comparison signal. A timing adjustment unit adjusts the phase of the first timing signal. | 12-20-2012 |
20130115723 | Method of manufacturing semiconductor device and semiconductor manufacturing system - In a method of manufacturing a semiconductor device using an electron beam lithography apparatus configured to emit an electron beam to perform lithography of a pattern, processing including pattern formation with the electron beam lithography apparatus is performed on a wafer, and an electric characteristic of the thus manufactured semiconductor devices is measured by a semiconductor testing apparatus. Then, electron beam lithography data to be used by the electron beam lithography apparatus is adjusted based on a result of measurement of the electric characteristic so as to reduce a variation in the electric characteristic of the semiconductor device within a surface of the wafer. | 05-09-2013 |
20130147499 | TEST APPARATUS AND TEST METHOD - A pattern generator generates a pattern signal which represents a test signal to be supplied to a DUT. A driver generates a test signal having a level that corresponds to the pattern signal, and outputs the test signal thus generated to the DUT. A voltage modulator changes, in a predetermined voltage range, the voltage level of the test signal output from the driver DR. | 06-13-2013 |
20130170583 | TRANSMITTING SYSTEM, RECEIVING SYSTEM, TRANSMITTING METHOD, AND RECEIVING METHOD - Provided are a transmitting system including a pulse amplitude modulator section that pulse amplitude modulates an input signal into a set of first and second pulse amplitude modulated signals, a first frequency signal output section that outputs a first frequency signal, a first amplitude shift keying modulator section that amplitude shift keying modulates, using the first frequency signal, the first pulse amplitude modulated signal into an amplitude shift keying modulated signal, an adder section that adds together the amplitude shift keying modulated signal and the second pulse amplitude modulated signal to generate a transmission signal, and a transmitter section that transmits the transmission signal, a transmitting method, a receiving system for receiving the signal transmitted from the transmitting system and a receiving method. | 07-04-2013 |
20130229197 | TEST APPARATUS - A main power supply is arranged such that its output terminal Po is connected to a power supply terminal of a DUT via a power supply line, and is configured to feedback control an output voltage V | 09-05-2013 |
20130249307 | WIRELESS COMMUNICATION APPARATUS AND WIRELESS COMMUNICATION SYSTEM - To realize a wireless communication apparatus with high transceiver coil mounting density, provided is a wireless communication apparatus comprising a plurality of differential coil pairs that respectively transmit and receive differential signals to and from a plurality of external differential coil pairs, through magnetic coupling, wherein one coil in a first differential coil pair among the differential coil pairs is provided at a distance from each of two coils of a second differential coil pair among the differential coil pairs that is less than or equal to a distance between the two coils of the second differential coil pair, and the other coil of the first differential coil pair is provided at a distance from each of the two coils of the second differential coil pair that is greater than the distance between the two coils of the second differential coil pair. | 09-26-2013 |
20140091830 | TEST APPARATUS - A judgment unit judges the pass/fail of DUTs. A power supply circuit has changeable characteristics, and supplies a power supply signal to the DUTs. A condition setting unit performs a pilot test before a main test for the DUTs, and acquires a test condition to be used in the main test. The condition setting unit executes: (a) measuring a first device characteristic value for each of multiple pilot samples sampled from among the DUTs while emulating a power supply characteristic close to what is used in a user environment in which the DUT is actually used; (b) measuring a predetermined second device characteristic value for each of the multiple pilot sample devices while emulating a power supply characteristic close to what is used in a tester environment in which the main test is performed; and (c) determining the test condition based on the first and second device characteristic values. | 04-03-2014 |
20140188436 | TEST APPARATUS AND TEST METHOD - Provided is a test apparatus that tests a device under test, comprising a plurality of comparators that each receive a signal under measurement output by the device under test, have a common reference level set therein, and compare a signal level of the signal under measurement to the reference level; and a signal processing section that generates a single result signal based on the plurality of comparison results output by the comparators. Also provided is a test method using the test apparatus. | 07-03-2014 |