Patent application number | Description | Published |
20080303588 | REFERENCE VOLTAGE GENERATING CIRCUIT AND CONSTANT VOLTAGE CIRCUIT - A reference voltage generating circuit for producing a predetermined reference voltage at an output node includes a depletion-type n-channel field-effect transistor serving as a first field-effect transistor having one node thereof coupled to a power supply voltage, a second field-effect transistor having one node thereof coupled to another node of the first field-effect transistor and having a highly-doped n-type gate, and a third field-effect transistor having one node thereof coupled to another node of the second field-effect transistor, another node thereof coupled to a ground voltage, and a highly-doped p-type gate. | 12-11-2008 |
20090064791 | STRESS-DISTRIBUTION DETECTING SEMICONDUCTOR PACKAGE GROUP AND DETECTION METHOD OF STRESS DISTRIBUTION IN SEMICONDUCTOR PACKAGE USING THE SAME - A disclosed stress-distribution detecting semiconductor package group includes multiple stress-distribution detecting semiconductor packages each formed by resin-encapsulating a stress detecting semiconductor chip of the same size using an identical resin encapsulation structure. Each stress detecting semiconductor chip includes a piezoelectric element for stress detection and at least two electrode pads electrically connected to the piezoelectric element to measure an electrical property of the piezoelectric element. The piezoelectric elements of the stress detecting semiconductor chips are respectively disposed on the corresponding stress detecting semiconductor chips to be located at different positions from one another when superimposed on a single imaginary semiconductor chip plane having the same plane size as that of the stress detecting semiconductor chips. | 03-12-2009 |
20100193887 | Stress-Distribution Detecting Semiconductor Package Group And Detection Method Of Stress Distribution In Semiconductor Package Using The Same - A disclosed stress-distribution detecting semiconductor package group includes multiple stress-distribution detecting semiconductor packages each formed by resin-encapsulating a stress detecting semiconductor chip of the same size using an identical resin encapsulation structure. Each stress detecting semiconductor chip includes a piezoelectric element for stress detection and at least two electrode pads electrically connected to the piezoelectric element to measure an electrical property of the piezoelectric element. The piezoelectric elements of the stress detecting semiconductor chips are respectively disposed on the corresponding stress detecting semiconductor chips to be located at different positions from one another when superimposed on a single imaginary semiconductor chip plane having the same plane size as that of the stress detecting semiconductor chips. | 08-05-2010 |
20110155913 | TEMPERATURE SENSOR AND LIVING BODY DETECTOR USING TEMPERATURE SENSOR - Disclosed is a temperature sensor using a work-function-difference-based radiant-ray detecting element that outputs, as a detecting signal of radiant rays, a work function difference between gate electrodes of first and second field-effect transistors sensing the radiant rays. The temperature sensor includes at least a pair of a first work-function-difference-based radiant-ray detecting element having a positive output temperature coefficient; and a second work-function-difference-based radiant-ray detecting element having a negative output temperature coefficient of which an absolute value is equal to an absolute value of the output temperature coefficient of the first work-function-difference-based radiant-ray detecting element. | 06-30-2011 |
20110185326 | NET LIST GENERATION METHOD AND CIRCUIT SIMULATION METHOD - Disclosed is a net list generation method of generating a net list based on layout data; stress map data indicating stress distribution on a silicon chip, the stress being generated due to packaging of the silicon chip; and standard curve data indicating a relationship between the stress and characteristic variation of a device. The method includes the steps of reading data items from the layout data; reading a value of stress at the position of the device from the stress map data; reading the characteristic variation of the device, the characteristic variation corresponding to the value of the stress, from the standard curve data corresponding to the device; and correcting characteristics of the device based on the characteristic variation. | 07-28-2011 |
20130127504 | METHOD FOR RESETTING PHOTOELECTRIC CONVERSION DEVICE, AND PHOTOELECTRIC CONVERSION DEVICE - A reset method of an photoelectric conversion device at least including a phototransistor having a first collector, a first base, and a first emitter, and a first field-effect transistor having a first source, a first drain, and a first gate, includes: connecting the first base, and one of the first source and the first drain of the first field-effect transistor by having a common region, or a continuous region, without a base electrode; supplying a base reset potential to the other of the first source and the first drain; and overlapping a time in which a first emitter potential is supplied to the first emitter and a time in which a first ON-potential that turns on the first field-effect transistor is supplied to the first gate. | 05-23-2013 |
20130187030 | SENSE CIRCUIT AND METHOD OF OPERATION THEREOF AND PHOTOELECTRIC CONVERSION ARRAY - A sense circuit includes a differential amplifier circuit including an inverting input section, a non-inverting input section and an output section, an electrical capacitor connected between the inverting input section and the output section, and a field effect transistor including a source, a drain, and a gate. One of the source and the drain is connected to the inverting input section, and the other of the source and the drain is connected to the output section. A reference potential is supplied to the non-inverting input section, and an output section of a photoelectric conversion cell having an added switching function is connected to the inverting input section. | 07-25-2013 |
20150214413 | PHOTOTRANSISTOR AND SEMICONDUCTOR DEVICE - A phototransistor includes a first emitter region, a first base region having at least a portion exposed to a light-receiving side, and a first collector region in this order from the light-receiving side in a depth direction. The first collector region includes a second collector region and a third collector region that is in contact with a downstream side of the second collector region in the depth direction and has a resistance lower than that of the second collector region. The phototransistor further includes a first region that is spaced away from the first base region at an outer side of the first base region on a light-receiving side surface thereof, the first region having a conductivity type opposite to that of the first collector region. | 07-30-2015 |
20150264280 | IMAGING DEVICE AND ELECTRONIC DEVICE - An imaging device includes a photoelectric conversion element which photoelectrically converts incident light and generates a charge, accumulates and amplifies the charge, and outputs a photocurrent, wherein a level of an output signal when a charge which is accumulated in the photoelectric conversion element is outputted over a saturated amount of accumulable charge includes a level of an output signal of a charge of a photocurrent of DC component which is generated in the photoelectric conversion element and outputted during a readout time when the charge which is accumulated in the photoelectric conversion element is outputted. | 09-17-2015 |
20160027835 | IMAGING DEVICE, CONTROL METHOD OF IMAGING DEVICE, AND PIXEL STRUCTURE - An imaging device having phototransistors in photodetectors of pixels is disclosed. The imaging device includes an implanted electrode configured to separate the pixels, a first emitter disposed at a position adjacent to the implanted electrode, and a second emitter disposed such that a distance from the implanted electrode to the second emitter is longer than a distance from the implanted electrode to the first emitter. | 01-28-2016 |
Patent application number | Description | Published |
20120092220 | ANTENNA APPARATUS AND ELECTRONIC DEVICE - An antenna apparatus is provided with a first antenna element, a second antenna element, a first ground element, a first ground plane and a second ground plane each formed by a conductive pattern. The first antenna element and the second antenna element are electrically connected by a first through-hole, and also form a first capacitive coupling portion in which they partially overlap across a substrate and are capacitively coupled. Such a configuration enables the antenna apparatus to be realized at low cost, since an antenna can be formed with only a substrate and conductive patterns, without requiring additional elements such as sheet metal. The antenna apparatus also can be reduced in profile and size, since only the conductive patterns are formed on a first surface and a second surface of the substrate, and there are no members that project significantly from the plane of the substrate. | 04-19-2012 |
20140078001 | SMALL ANTENNA APPARATUS OPERABLE IN MULTIPLE FREQUENCY BANDS - An antenna apparatus is provided with a dielectric substrate, a feed point, a first radiation conductor, a second radiation conductor, and a through-hole conductor. The first radiation element is capacitively coupled to the second radiation element in a portion where the first and second radiation conductors overlaps with each other via the dielectric substrate. At least one of the first and second radiation elements has a meander portion formed in the portion where the first and second radiation elements are capacitively coupled to each other, and an LC resonator is formed of the meander portion, and the portion where the first and second radiation elements are capacitively coupled to each other. | 03-20-2014 |
Patent application number | Description | Published |
20080224281 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - A semiconductor device comprises: a semiconductor chip; a first frame; a solder layer which bonds the solder bonding metal layer of the semiconductor chip and the first frame; and a second frame bonded to the rear face of the semiconductor chip. The semiconductor chip includes: a semiconductor substrate; a first metal layer provided on a major surface of the semiconductor substrate and forming a Schottky junction with the semiconductor substrate; a second metal layer provided on the first metal layer and primarily composed of aluminum; a third metal layer provided on the second metal layer and primarily composed of molybdenum or titanium; and a solder bonding metal layer provided on the third metal layer and including at least a forth metal layer which is primarily composed of nickel, ion or cobalt. | 09-18-2008 |
20110207263 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME - The present invention relates to a method of manufacturing a semiconductor device including (1) forming a laminated structure on a major surface of a semiconductor substrate, the laminated structure comprising at least a first metal layer that forms a Schottky junction with the semiconductor substrate, a second metal layer primarily composed of aluminum, and a third metal layer primarily composed of molybdenum or titanium, (2) patterning the laminated structure into a predetermined configuration, (3) forming a solder bonding metal layer comprising at least nickel, ion or cobalt on the major surface of the semiconductor substrate having the patterned laminated structure formed thereon, (4) patterning the solder bonding metal layer into a pattern configuration identical to that of the laminated structure, (5) cutting the semiconductor substrate on which the laminated structure and the solder bonding metal layer are patterned to form a plurality of semiconductor chips, and (6) bonding the semiconductor chip to a first frame using at least one solder layer formed on the solder bonding metal layer on the major surface of the semiconductor substrate, and bonding a rear face of the semiconductor chip to a second frame. | 08-25-2011 |
Patent application number | Description | Published |
20100247764 | Method For Surface Treatment of Ti-Al Alloy and Ti-Al Alloy Obtained by The Method - There is provided a surface treatment method for improving high temperature resistance oxidizability of a Ti—Al alloy in a manner suitable for mass production and the Ti—Al alloy. A Ti—Al alloy base material containing 15 at % or more to 55 at % or less of Al is heated and held in a gas atmosphere containing a fluorine source gas to form a fluorine inspissation layer with a thickness of 0.1 μm or more to 10 μm or less on the surface of the Ti—Al alloy base material, and a maximum concentration of F in the fluorine inspissation layer is made to be 2 at % or more to 35 at % or less. Thereby, when exposed to a high temperature oxidizing atmosphere, the surface of the Ti—Al alloy base is coated with an Al | 09-30-2010 |
20110159184 | METHOD OF FLUORIDATION, THE UNIT OF FLUORIDATION, AND THE DIRECTIONS FOR USE OF THE UNIT OF FLUORIDATION - A method of fluoridation that can maintain a stable treatment quality is provided. The method of the fluoridation treatment performs the fluoridation treatment by heating and keeping a workpiece in a fluoridation treatment space filled with a predetermined fluoride atmosphere. By exposing an interior space structure that is reactive against fluorine within the fluoridation treatment space, forming a fluoride layer in advance on a surface of the interior space structure exposed within the fluoridation treatment space, and performing the fluoridation treatment, a fluoridation source gas supplied for the fluoridation treatment of the workpiece is not significantly consumed for fluoridating the surface of the interior space structure during the fluoridation treatment. Further, even when a fluoridation potential of the supplied fluoridation source gas is insufficient, the fluoride layer on the surface of the interior space structure discharges the fluoridation gas. Thereby, the fluoride atmosphere in the fluoridation treatment space during the fluoridation treatment can be appropriately maintained. | 06-30-2011 |
20110162758 | FURNACE OF HEAT TREATMENT, THE METHOD OF HEAT TREATMENT, AND THE DIRECTIONS FOR USE OF FURNACE OF HEAT TREATMENT - A furnace of heat treatment capable of keeping a stable nitriding quality for a long period of time is provided. The furnace of heat treatment performs a halogenation treatment and a nitriding treatment by heating a steel material under a predetermined atmosphere. An alloy containing Ni ranging between 50 mass % or more and 80 mass % or less and Fe ranging between 0 mass % or more and 20 mass % or less is used as a material of surfaces of core internals exposed to a treatment space where the nitriding treatment is performed. Accordingly, a nitriding reaction is hardly caused on the surfaces of the core internals, and the halogenation treatment and the nitriding treatment to an article to be treated can be stably executed for a long period of time. Further, a nitrided layer can be stably formed according to purposes on any types of steel materials including a steel type hard to be nitride. | 07-07-2011 |
Patent application number | Description | Published |
20100008857 | NOVEL HEXATRIENE-BETA-CARBONYL COMPOUND - A label with which labeling is easy when labeling a molecule, i.e., a label that has a high reaction rate upon labeling and that produces a high reaction yield, as well as a precursor for the production of the label are provided. This is achieved by a hexatriene-β-carbonyl compound represented by Formula (I), a hexatriene-β-carbonyl compound represented by Formula (II), a hexatriene-β-carbonyl compound represented by Formula (III) and a hexatriene-β-carbonyl compound represented by Formula (IV). | 01-14-2010 |
20110237774 | METHOD FOR INTRODUCING DOTA - The invention provides a method for introducing 1,4,7,10-tetraazacyclododecane-N,N′,N″,N′″-tetraacetic acid (DOTA) into a compound such as a peptide. The method comprises a first step for preparing a mixed liquid of DOTA having no protecting group and dimethylsulfoxide, and a second step for contacting the mixed liquid with the compound carried on a solid-phase carrier. | 09-29-2011 |
20110288424 | HUMAN FATIGUE ASSESSMENT DEVICE AND HUMAN FATIGUE ASSESSMENT METHOD - A human fatigue assessment device capable of performing highly accurate fatigue assessment is provided. The human fatigue assessment device ( | 11-24-2011 |
20120101266 | 18F-LABELED AZIDE COMPOUND, REAGENT FOR 18F-LABELING AND METHOD FOR 18F-LABELING OF ALKYNE COMPOUND USING SAME | 04-26-2012 |
20140180145 | HUMAN FATIGUE ASSESSMENT DEVICE AND HUMAN FATIGUE ASSESSMENT METHOD - A human fatigue assessment device capable of performing highly accurate fatigue assessment is provided. The human fatigue assessment device includes: a physiological signal measuring unit configured to measure a heartbeat or pulse wave of a user as a physiological signal; a feature value extracting unit configured to extract feature values each indicating amount of parasympathetic nerve activity and each obtained from the measured physiological signal measured; a storage unit in which the extracted feature values are stored; and a fatigue type determining unit configured to determine a type of fatigue of the user as to whether the fatigue of the user is due to a first work or due to a second work more monotonous than the first work, using the extracted feature values. | 06-26-2014 |