Patent application number | Description | Published |
20080303096 | Semiconductor devices and methods of manufacture thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes forming a transistor, the transistor including a fin having a first side and a second side opposite the first side. The transistor includes a first gate electrode disposed on the first side of the fin and a second gate electrode disposed on the second side of the fin. The method includes forming a silicide or germanide of a metal on the first gate electrode and the second gate electrode of the transistor. The amount of the metal of the silicide or germanide is substantially homogeneous over the first gate electrode and the second gate electrode proximate the fin. | 12-11-2008 |
20090008707 | SRAM DEVICE - An integrated circuit device has a base area defining a longitudinal axis. Four in-line transistors, which are NMOS transistors in exemplary embodiments, are each centered on the longitudinal axis. Two off-set transistors, which are PMOS transistors in exemplary embodiments, are off-set to first and second sides of the longitudinal axis, respectively. | 01-08-2009 |
20090041406 | INTEGRATED CIRCUIT INCLUDING NON-PLANAR STRUCTURE AND WAVEGUIDE - One embodiment provides an integrated circuit including a first non-planar structure and a waveguide configured to provide electromagnetic waves to the first non-planar structure. The first non-planar structure provides a first signal in response to at least some of the electromagnetic waves. | 02-12-2009 |
20090101975 | Integrated Circuit Arrangement Comprising a Field Effect Transistor, Especially a Tunnel Field Effect Transistor - An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric (GD | 04-23-2009 |
20090114955 | Method for Fabricating a Fin-Shaped Semiconductor Structure and a Fin-Shaped Semiconductor Structure - A fin-shaped structure is formed from a semiconductor material. The fin-shaped structure is processed to generate a tensile strain within the semiconductor material along a longitudinal direction of the fin. | 05-07-2009 |
20090209097 | METHOD OF FORMING INTERCONNECTS - A method of forming interconnects includes etching a first set of openings in a hard mask using a first photo resist layer with a first pattern of openings as a first etch mask, and etching a second set of openings in the hard mask using a second photo resist layer with a second pattern of openings as a second etch mask. The method includes shrinking the openings in at least one of the first pattern and the second pattern prior to etching the openings in the hard mask. | 08-20-2009 |
20100062573 | METHOD FOR PRODUCING AN ELECTRONIC COMPONENT, METHOD FOR PRODUCING A THYRISTOR, METHOD FOR PRODUCING A DRAIN-EXTENDED MOS FILED-EFFECT TRANSISTOR, ELECTRONIC COMPONENT, DRAIN-EXTENDED MOS FIELD-EFFECT TRANSISTOR, ELECTRONIC COMPONENT ARRANGEMENT - In a method for producing an electronic component, a first doped connection region and a second doped connection region are formed on or above a substrate; a body region is formed between the first doped connection region and the second doped connection region; at least two gate regions separate from one another are formed on or above the body region; at least one partial region of the body region is doped by means of introducing dopant atoms, wherein the dopant atoms are introduced into the at least one partial region of the body region through at least one intermediate region formed between the at least two separate gate regions. | 03-11-2010 |
20100123250 | Feature Patterning Methods and Structures Thereof - Methods of patterning features, methods of manufacturing semiconductor devices, and semiconductor devices are disclosed. In one embodiment, a method of patterning a feature includes forming a first portion of the feature in a first material layer. A second portion of the feature is formed in the first material layer, and a third portion of the feature is formed in a second material layer. | 05-20-2010 |
20100163995 | Semiconductor Device With Cooling Element - Some embodiments discussed herein include a semiconductor having a source region, a drain region and an array of fins operatively coupled to a gate region controlling current flow through the fins between the source region and the drain region. The semiconductor also has at least one cooling element formed at least in part of a material having a heat capacity equal to or larger than the heat capacity of the material of the source region, drain region and array of fins, the cooling elements being in close vicinity to fins of the array of fins electrically isolated from the fins of the array, the source region and the drain region. Other embodiments are also disclosed | 07-01-2010 |
20100176479 | METHOD OF FABRICATING A SEMICONDUCTOR DEVICE - A method of fabricating a semiconductor device including depositing a hardmask layer on a layer of the semiconductor device, selectively etching a pattern of continuous lines in the hardmask layer, depositing an antireflective coating over remaining portions of the hardmask layer, depositing a photoresist layer on the antireflective coating, patterning the photoresist layer with a plurality of isolation trenches via a lithography process, each of the isolation trenches extending perpendicular to and crossing portions of at least one of the continuous lines of the underlying hardmask layer, and with each isolation trench having an initial width. The method further includes reducing the width of each of the isolation trenches from the initial width to desired width via a shrinking process, etching the antireflective coating underlying the isolation trenches to expose intersecting portions of the underlying continuous lines, and etching the exposed intersecting portions of the underlying continuous lines of the hardmask layer to form a pattern of line segments having line ends separated by the desired width. | 07-15-2010 |
20100252874 | Memory Device - One or more embodiments relate to a floating gate memory device, comprising: a substrate; a floating gate disposed over the substrate; and a control gate substantially laterally surrounding at least a portion of the floating gate. | 10-07-2010 |
20110013668 | SEMICONDUCTOR CIRCUIT ARRANGEMENT AND ASSOCIATED METHOD FOR TEMPERATURE DETECTION - A semiconductor circuit arrangement and a method for temperature detection is disclosed. One embodiment includes a semiconductor substrate, on which is formed a first insulating layer and thereon a thin active semiconductor region, which is laterally delimited by a second insulating layer. In the active semiconductor region, a first and second doping zone are formed on the surface of the first insulating layer for the definition of a channel zone, wherein there is formed at the surface of the channel zone a gate dielectric and thereon a control electrode for the realization of a field effect transistor. In the active semiconductor region, a diode doping zone is formed on the surface of the first insulating layer, which zone realizes a measuring diode via a diode side area with the first or second doping zone and is delimited by the second insulating layer at its further side areas. | 01-20-2011 |
20110215479 | Feature Patterning Methods and Structures Thereof - Methods of patterning features, methods of manufacturing semiconductor devices, and semiconductor devices are disclosed. In one embodiment, a method of patterning a feature includes forming a first portion of the feature in a first material layer. A second portion of the feature is formed in the first material layer, and a third portion of the feature is formed in a second material layer. | 09-08-2011 |
20120119297 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes forming a transistor, the transistor including a fin having a first side and a second side opposite the first side. The transistor includes a first gate electrode disposed on the first side of the fin and a second gate electrode disposed on the second side of the fin. The method includes forming a silicide or germanide of a metal on the first gate electrode and the second gate electrode of the transistor. The amount of the metal of the silicide or germanide is substantially homogeneous over the first gate electrode and the second gate electrode proximate the fin. | 05-17-2012 |
20120252172 | Method for producing a thyristor - In a method for producing a thyristor, first and second connection regions are formed on or above a substrate; the first connection region is doped with dopant atoms of a first conductivity type and the second connection region is doped with dopant atoms of a second conductivity type; first and second body regions are formed between the connection regions, wherein the first body region is formed between the first connection region and second body region, and the second body region is formed between the first body region and second connection region; the first body region is doped with dopant atoms of the second conductivity type and the second body region is doped with dopant atoms of the first conductivity type, wherein the dopant atoms are in each case introduced into the respective body region using a Vt implantation method; a gate region is formed on or above the body regions. | 10-04-2012 |
20140124827 | Integrated Circuit Arrangement Comprising a Field Effect Transistor, Especially a Tunnel Field Effect Transistor - Integrated circuit arrangement comprising a field effect transistor, especially a tunnel field effect transistor. An explanation is given of, inter alia, tunnel field effect transistors having a thicker gate dielectric in comparison with other transistors on the same integrated circuit arrangement. As an alternative or in addition, said tunnel field effect transistors have gate regions at mutually remote sides of a channel forming region or an interface between the connection regions of the tunnel field effect transistor. | 05-08-2014 |
20140203366 | Semiconductor Devices and Methods of Manufacture Thereof - Semiconductor devices and methods of manufacture thereof are disclosed. A complimentary metal oxide semiconductor (CMOS) device includes a PMOS transistor having at least two first gate electrodes comprising a first parameter, and an NMOS transistor having at least two second gate electrodes comprising a second parameter, wherein the second parameter is different than the first parameter. The first parameter and the second parameter may comprise the thickness or the dopant profile of the gate electrode materials of the PMOS and NMOS transistors. The first and second parameter of the at least two first gate electrodes and the at least two second gate electrodes establish the work function of the PMOS and NMOS transistors, respectively. | 07-24-2014 |
20140203455 | Feature Patterning Methods and Structures Thereof - Methods of patterning features, methods of manufacturing semiconductor devices, and semiconductor devices are disclosed. In one embodiment, a method of patterning a feature includes forming a first portion of the feature in a first material layer. A second portion of the feature is formed in the first material layer, and a third portion of the feature is formed in a second material layer. | 07-24-2014 |
20140205233 | INTEGRATED CIRCUIT INCLUDING NON-PLANAR STRUCTURE AND WAVEGUIDE - One embodiment provides an integrated circuit including a first non-planar structure and a waveguide configured to provide electromagnetic waves to the first non-planar structure. The first non-planar structure provides a first signal in response to at least some of the electromagnetic waves. | 07-24-2014 |