Patent application number | Description | Published |
20100169846 | METHODS FOR GATE-LENGTH BIASING USING ANNOTATION DATA - Methods for generating a biased layout for making an integrated circuit are disclosed. One such method includes obtaining a nominal layout defined by one or more cells, where each cell has one or more transistor gate features with a nominal gate length. Then, obtaining an annotated layout. The annotated layout contains information describing gate-length biasing of one or more of the transistor gate features in one or more cells of the nominal layout. A biased layout is produced by modifying the nominal layout using the information from the annotated layout. The biasing modifies a gate length of those transistor gate features identified by the information of the annotated layout. | 07-01-2010 |
20100169847 | STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING - A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device. | 07-01-2010 |
20130014071 | STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING - A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device. | 01-10-2013 |
20130014072 | STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING - A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device. | 01-10-2013 |
20130014073 | STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING - A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device. | 01-10-2013 |
Patent application number | Description | Published |
20080235645 | Method and apparatus for detecting lithographic hotspots - Method for detecting hotspots in a circuit layout includes constructing a layout graph having nodes, corner edges and proximity edges from the circuit layout, converting the layout graph to a corresponding dual graph, and iteratively selecting edges and nodes having weights greater than a predetermined threshold value at each iteration as hotspots. | 09-25-2008 |
20100023917 | TOOL FOR MODIFYING MASK DESIGN LAYOUT - An embodiment of the invention provides a tool for modifying a mask design layout to be printed. The tool is executed by a computer system, and includes code for establishing a first level of correction for a mask design layout for a predetermined parametric yield without cost of correction to area of the mask design layout. The tool also includes code for correcting the mask design layout at said first level of correction based on a correction algorithm, the correction algorithm selecting a cell of the mask design layout having an edge placement error (EPE) for each gate feature in the cell. The correction algorithm selects the cell without loss to parametric yield as established by the predetermined parametric yield. | 01-28-2010 |
20110078638 | LAYOUT DECOMPOSITION FOR DOUBLE PATTERNING LITHOGRAPHY - The invention provides systems and methods for layout decomposition to produce exposure layouts that can be used to perform double patterning lithography (DPL). Preferred embodiment methods of the invention are executed by a computer and provide alternate methods for layout decomposition for double patterning lithography (DPL) using integer linear programming (ILP) formulations. Embodiments of the invention meet a key optimization goals, which is to reduce the total cost of layout decomposition, considering the abovementioned aspects that contribute to cost of prior conventional DPL techniques. Embodiments of the invention provide integer linear programming (ILP), phase conflict detection (PCD) and node election bipartization (NBD) formulations for the optimization of DPL layout decomposition, with a process-aware cost function that avoids small jogging line-ends, and maximizes overlap at dividing points of polygons. The cost function can also make preferential splits at landing pads, junctions and long runs. | 03-31-2011 |
20130159945 | LAYOUT DECOMPOSITION FOR DOUBLE PATTERNING LITHOGRAPHY - The invention provides systems and methods for layout decomposition to produce exposure layouts that can be used to perform double patterning lithography (DPL). Preferred embodiment methods of the invention are executed by a computer and provide alternate methods for layout decomposition for double patterning lithography (DPL) using integer linear programming (ILP) formulations. Embodiments of the invention meet a key optimization goals, which is to reduce the total cost of layout decomposition, considering the abovementioned aspects that contribute to cost of prior conventional DPL techniques. Embodiments of the invention provide integer linear programming (ILP), phase conflict detection (PCD) and node election bipartization (NBD) formulations for the optimization of DPL layout decomposition, with a process-aware cost function that avoids small jogging line-ends, and maximizes overlap at dividing points of polygons. The cost function can also make preferential splits at landing pads, junctions and long runs. | 06-20-2013 |
20130254734 | Standard Cells having transistors annotated for gate-length biasing - A standard cell library is disclosed. The standard cell library contains cells wherein at least one transistor in at least one cell is annotated for gate length biasing. Gate length biasing includes the modification of the gate length, so as to change the speed or power consumption of the modified gate length. The standard cell library is one used in the manufacturing of semiconductor devices (e.g., that result as semiconductor chips), by way of fabricating features defined on one or more layouts of geometric shapes. The annotations serve to identify which ones of the transistor gate features are to be modified before using the geometric shapes for manufacturing the semiconductor device. | 09-26-2013 |
20140059105 | ACCURACY CONFIGURABLE ADDERS AND METHODS - A preferred method of accuracy configuration with an approximate adder receives two input operands and generates a first approximate adder output with a plurality of sub-adders having a first accuracy under a first condition. Error detection and correction is selectively enabled to generate a next approximate adder output having a second accuracy that is higher than the first accuracy under a second condition. In preferred embodiments, a pipelined architecture provides selectable stages and the enablement of each successive stage provides a high level of accuracy. Power gated control can achieve enablement of error correction stages to conserve power. | 02-27-2014 |
20140223404 | Gate-Length Biasing for Digital Circuit Optimization - Methods and apparatus for a gate-length biasing methodology for optimizing integrated digital circuits are described. The gate-length biasing methodology that changes a nominal gate-length of a transistor to a biased gate-length, where the biased gate-length includes a bias length that is small compared to the nominal gate-length. | 08-07-2014 |
20140245245 | STANDARD CELLS HAVING TRANSISTORS ANNOTATED FOR GATE-LENGTH BIASING - Methods, layouts and chip design layouts that use annotations for communicating gate-length biasing amounts to post-layout tools are disclosed. One method includes receiving a chip design layout designed to includes select ones of a plurality of nominal cell layouts and an annotated cell layout. The chip design layout is defined by a plurality of layers and the plurality of nominal cell layouts define transistors, wherein each of the plurality of nominal cell layouts define nominal length transistors, and the annotated cell layout also defines transistors. The annotated cell layout is associated with an annotation layer that identifies a gate-length biasing to be applied to at least one transistor of the annotated cell layout. The gate-length biasing identifies an amount of change for a gate length and not width-sizing of a gate width of the at least one transistor of the annotated cell layout. The annotation layer is used to communicate design-specific directives that require implementation. The method uses a processor to process the chip design layout, with reference to the annotation layer, to apply the gate-length biasing to the annotated cell of the chip design layout. | 08-28-2014 |
Patent application number | Description | Published |
20130223447 | NETWORK SYSTEM - A method for packet processing in a network including a plurality of terminals, includes generating, by a first terminal, a packet including a geographical address. The first terminal transmits the packet transmitted to a destination. The geographical address includes a location information field having location information of the first terminal and a range field indicating whether the destination is a single destination representing that the destination is a target terminal or an area destination representing the destination is a target area. The range field has range information of the target area in the case that the destination is the area destination. | 08-29-2013 |
20130235862 | IPV6 ADDRESS MANAGEMENT METHOD AND GATEWAY PERFORMING THE SAME - A management method for an IPv6 address for use in a gateway is provided. The method includes receiving a packet including an IPv6 address, extracting a MAC address from the IPv6 address of the packet, generating a compressed address by inserting a previously defined bit sequence into the MAC address, and storing the compressed address and the IPv6 address in a mapping table. The packet is received from a WPAN (Wireless Personal Area Network) node. | 09-12-2013 |
20130315102 | NETWORK SYSTEM - A NETWORK ADDRESS GENERATION DEVICE OF A NODE IS CAPABLE OF GENERATING A NETWORK ADDRESS INCLUDING A FLEXIBLE ADDRESS INCLUDING A LOCATOR THAT DEFINES LOCATION INFORMATION OF A POINT WHERE THE NODE IS LOCATED, AND A NODE IDENTIFIER THAT INCLUDES IDENTIFICATION INFORMATION OF THE NODE. | 11-28-2013 |
20150043364 | DYNAMIC ROUTING METHOD IN AD-HOC NETWORK AND NETWORK DEVICE THEREFOR - A dynamic routing method of a network device in an ad-hoc network is provided. The method includes (a) collecting a factor comprising at least one of the number of neighboring network devices, a moving speed and an amount of data traffic; (b) setting a routing information transmission mode based on a value of the collected factor; and (c) processing at least one of transmission and non-transmission of routing information according to the set routing information transmission mode, wherein in the step (b), when setting the routing information transmission mode, if the value of the factor is less than a preset threshold value, the routing information transmission mode is set to an active mode, and if the value of the factor exceeds the threshold, the routing information transmission mode is set to an inactive mode. | 02-12-2015 |
Patent application number | Description | Published |
20080303085 | SEMICONDUCTOR DEVICE INCLUDING ACTIVE PATTERN WITH CHANNEL RECESS, AND METHOD OF FABRICATING THE SAME - A semiconductor device including an active pattern having a channel recess portion, and a method of fabricating the same, are disclosed. In one embodiment, the semiconductor device includes an active pattern including first active regions and a second active region interposed between the first active regions. The active pattern protrudes above a surface of a semiconductor substrate and includes a channel recess portion above the second active region and between the first active regions. A device isolation layer surrounds the active pattern and has a groove exposing side walls of the recessed second active region. A distance between opposing side walls of the first active regions exposed by the channel recess portion is greater than a distance between side walls of the groove. A gate pattern is located in the channel recess portion and extends along the groove. | 12-11-2008 |
20090186471 | METHOD OF FABRICATING SEMICONDUCTOR DEVICE FOR REDUCING THERMAL BURDEN ON IMPURITY REGIONS OF PERIPHERAL CIRCUIT REGION - A method of fabricating a semiconductor device for reducing a thermal burden on impurity regions of a peripheral circuit region includes preparing a substrate including a cell active region in a cell array region and peripheral active regions in a peripheral circuit region. A cell gate pattern and peripheral gate patterns may be formed on the cell active region and the peripheral active regions. First cell impurity regions may be formed in the cell active region. A first insulating layer and a sacrificial insulating layer may be formed to surround the cell gate pattern and the peripheral gate patterns. Cell conductive pads may be formed in the first insulating layer to electrically connect the first cell impurity regions. The sacrificial insulating layer may be removed adjacent to the peripheral gate patterns. First and second peripheral impurity regions may be sequentially formed in the peripheral active regions adjacent to the peripheral gate patterns. | 07-23-2009 |
20100140692 | METHODS OF FABRICATING SEMICONDUCTOR DEVICES HAVING MULTIPLE CHANNEL TRANSISTORS AND SEMICONDUCTOR DEVICES FABRICATED THEREBY - In methods of fabricating a semiconductor device having multiple channel transistors and semiconductor devices fabricated thereby, the semiconductor device includes an isolation region disposed within a semiconductor substrate and defining a first region. A plurality of semiconductor pillars self-aligned with the first region and spaced apart from each other are disposed within the first region, and each of the semiconductor pillars has at least one recessed region therein. At least one gate structure may be disposed across the recessed regions, which crosses the semiconductor pillars and extends onto the isolation region. | 06-10-2010 |
20100200933 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device is fabricating using a photoresist mask pattern, and selectively removing portions of a liner nitride layer in a cell region and a peripheral circuit region. A modified FinFET is formed to reduce the influence of signals transmitted by adjacent gate lines in a cell region. A double FinFET and a substantially planar MOSFET are formed in a core region and in a peripheral region, respectively, concurrently with the formation of the modified FinFET. | 08-12-2010 |
20130043519 | SEMICONDUCTOR DEVICES USING SHAPED GATE ELECTRODES - A device includes a semiconductor substrate and a gate insulation film lining a trench in an active region of the substrate. A gate electrode pattern is recessed in the trench on the gate insulation film and has an upper surface that has a nonuniform height. A dielectric pattern may be disposed on the gate electrode pattern in the trench. | 02-21-2013 |
20130344666 | Methods of Fabricating Semiconductor Devices Having Increased Areas of Storage Contacts - Methods of fabricating semiconductor device are provided including forming first through third silicon crystalline layers on first through third surfaces of an active region; removing the first silicon crystalline layer to expose the first surface; forming a bit line stack on the exposed first surface; forming bit line sidewall spacers on both side surfaces of the bit line stack to be vertically aligned with portions of the second and third silicon crystalline layers of the active region; removing the second and third silicon crystalline layers disposed under the bit line sidewall spacers to expose the second and third surfaces of the active region; and forming storage contact plugs in contact with the second and third surfaces of the active region. | 12-26-2013 |
Patent application number | Description | Published |
20110248793 | BAND-PASS FILTER BASED ON CRLH RESONATOR AND DUPLEXER USING THE SAME - A CRLH resonator-based band-pass filter includes at least two CRLH resonators. The resonators are connected by capacitive coupling. The resonators includes a microstrip line having input and output ports. The microstrip line includes a first interdigital line serial-connected to the input port, a second interdigital line serial-connected to the output port, a connection line connecting the first and second interdigital lines, and an inductor line parallel-connected to the connection line and provided with a grounded end. | 10-13-2011 |
20120235867 | META-MATERIAL MIMO ANTENNA - A meta-material MIMO antenna is disclosed, wherein the meta-material MIMO antenna includes a substrate; a first top radiator formed at one side of top surface of the substrate, and including an inner radiator and an outer radiator discrete from the inner radiator to encompass the inner radiator from outside; a second top radiator symmetrically formed against the first top radiator and formed on the other side of the top surface of the substrate; a first bottom radiator electrically connected to the first top radiator and formed on one side of bottom surface of the substrate; a second bottom radiator symmetrically formed against the first bottom radiator and formed on the other side of the bottom surface of the substrate; and a coupler remover interposed between the first and second bottom radiators, whereby the antenna can be miniaturized to enhance a high isolation. | 09-20-2012 |
20120256703 | BANDPASS FILTER AND ELECTRONIC DEVICE - A bandpass filter includes resonator coupling line on which a plurality of composite right/left-handed (CRLH) resonators are disposed. The plurality of CRLH resonators are inductively coupled with each other. The design variables can be increased through inductive coupling in the resonance period. Also, the skirt characteristics and the isolation can be improved. | 10-11-2012 |