Patent application number | Description | Published |
20080197891 | Frequency synthesizer using two phase locked loops - The application discloses system and method embodiments related to a frequency synthesizer. Embodiments of a frequency synthesizer can have a low phase noise and a narrow channel spacing. Embodiments of a frequency synthesizer can use two phase locked loops. One embodiment of a frequency synthesizer can include a reference frequency oscillator for outputting a signal having a reference frequency, an integer-N phase locked loop to generate a first output frequency signal based on the reference frequency signal, a fractional-N phase locked loop to generate a second output frequency based on the reference frequency signal and a circuit to generate an output frequency signal by combining the first output frequency and the second output frequency. | 08-21-2008 |
20080205502 | APPARATUS FOR MEASURING IQ IMBALANCE - The present general inventive concept relates to apparatuses and/or methods for measuring an IQ imbalance. In one embodiment, a detector can measure an error caused by an IQ imbalance using a first IQ signal including a desired signal and a corresponding image signal by the IQ imbalance. The detector can include a derotator to derotate the first IQ signal by a first angular frequency to obtain a second IQ signal and derotate the first IQ signal by a second angular frequency to obtain a third IQ signal, a DC estimator to obtain a fourth IQ signal corresponding to a DC component of the second IQ signal and a fifth IQ signal corresponding to a DC component of the third IQ signal and a controller can determine a gain error or a phase error from the fourth IQ signal and the fifth IQ signal. | 08-28-2008 |
20080212662 | APPARATUS FOR MEASURING IQ IMBALANCE - The present general inventive concept relates to apparatuses and/or methods for measuring an IQ imbalance. In one embodiment, a signal generator can provide a first IQ signal of a DC component during a first period and the first IQ signal of a first angular frequency during a second period, an IQ up-conversion mixer can up-convert the first IQ signal by a second angular frequency during the first period and up-convert the first IQ signal by a third angular frequency during the second period to output a second IQ signal, an IQ down-conversion mixer can down-convert the second IQ signal by the third angular frequency to output a third IQ signal and an IQ imbalance detector can obtain a first IQ imbalance (e.g., Rx IQ imbalance) from the third IQ signal during the first period and a second IQ imbalance (e.g., Tx/Rx IQ imbalance) during the second period. | 09-04-2008 |
20080252383 | Phase locked loop and method for compensating temperature thereof - Embodiments of a phase lock loop and a method for compensating a temperature thereof can output an initial tuning digital value for a voltage controlled oscillator configured to output a desired phase lock loop frequency compensated according to a temperature change. Embodiments of a phase lock loop and a method for compensating a temperature thereof can simultaneously perform a digital coarse tuning and an analog fine tuning to compensate for a temperature in a limited time. | 10-16-2008 |
20080253277 | OFDM receiving circuit having multiple demodulation paths using oversampling analog-to-digital converter - Embodiments according to the application relates to an OFDM (orthogonal frequency division multiplexing) receiving circuit and methods thereof configured to have a plurality of demodulation paths for an oversampling ADC, which can increase or improve an overall performance of the circuit. | 10-16-2008 |
20080253470 | OFDM receiving circuit having multiple demodulation paths - Embodiments according to the application relate to an OFDM (orthogonal frequency division multiplexing) receiving circuit and methods thereof configured to have a plurality of demodulation paths, which can increase or improve a performance of an ADC and/or a filter. | 10-16-2008 |
20090028231 | APPARATUS FOR MEASURING IQ IMBALANCE - The present invention relates to an apparatus and a method for measuring an IQ imbalance. One embodiment according to the present general inventive concept can provide a method for measuring a Tx IQ imbalance generated in an IQ up-conversion mixer and an Rx IQ imbalance generated in an IQ down-conversion mixer, that includes measuring a first IQ imbalance corresponding to a first combination of the Rx IQ imbalance with the Tx IQ imbalance, measuring a second IQ imbalance corresponding to a second combination of the Rx IQ imbalance with the Tx IQ imbalance and obtaining the Tx IQ imbalance and the Rx IQ imbalance from the first IQ imbalance and the second IQ imbalance. | 01-29-2009 |
20090115496 | VPP VOLTAGE GENERATOR FOR GENERATING STABLE VPP VOLTAGE - The present invention relates to a VPP voltage generator that generates a stable VPP voltage. The VPP voltage generator of the present invention generates a stable VPP voltage. Therefore, power consumption can be saved, a precharge time of word line can be prevented from increasing and a tRCD characteristic can be improved. It is thus possible to improve the operational performance of semiconductor memory devices. | 05-07-2009 |
20090249138 | Semiconductor memory apparatus for reducing bus traffic between NAND flash memory device and controller - Provided is a semiconductor memory apparatus that may use an efficient protocol between an NAND flash memory device and a controller to reduce bus traffic. The flash memory device may include a memory cell array and an error correction encoder. The memory cell array may include a plurality of pages. The error correction encoder may generate first parity data based on normal data to be written to the memory cell array, compare the first parity data and second parity data encoded with the normal data stored in the memory cell array, and check an error. The error position detector may detect an error position in response to the error signal transmitted from the error correction encoder. Thus, since the semiconductor memory apparatus may transmit and receives parity data or a syndrome between an NAND flash memory device and the controller by detecting and correcting an error in the same memory chip, bus traffic may be reduced. | 10-01-2009 |
20100082890 | Method of managing a solid state drive, associated systems and implementations - A solid state drive may include one or more memory cell arrays divided into a plurality of blocks. A first portion of the blocks may be designated for storing user data and a second portion of the blocks may be designated as reserved blocks for replacing defective blocks in the first portion. In one embodiment, the method includes reformatting, by a memory controller, the solid state drive to convert one or more blocks in the first portion into reserved blocks. | 04-01-2010 |
20110216587 | NONVOLATILE MEMORY DEVICE, METHODS OF PROGRAMING THE NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE NONVOLATILE MEMORY DEVICE - Embodiments of the inventive concept provide a nonvolatile memory device. The nonvolatile memory device includes a memory cell array, a read/write circuit, and a backup circuit. The memory cell array includes a first memory block including a first word line having first memory cells and a second word line having second memory cells. Each of the first memory cells and second memory cells configured to store first-bit data and second-bit data. The read/write circuit is configured to program data into the first and second memory cells and read data stored in the first and second memory cells. The backup circuit is configured to, after first-bit data are programmed into the first word line, but before second-bit data are programmed into the first word line, store first-bit data stored in the second memory cells of the second word line | 09-08-2011 |
20110238900 | Method of managing a solid state drive, associated systems and implementations - In one embodiment, the method includes storing, by a status checking module, status information for a solid state drive, and determining a status state of the solid state drive based on the status information. The status state is one of a good state, an intermediate state and a bad state, and the intermediate state is a state between the good state and the bad state. | 09-29-2011 |
20110238971 | Method of managing a solid state drive, associated systems and implementations - One embodiment of a method includes loading, by a memory controller, a boot image from a solid state drive to an operating memory of a computing system during an initialization operation of the computing system. The initialization operation initializes components of the computing system. | 09-29-2011 |
20110292729 | Method of Controlling Non-Volatile Memory Device - A method of controlling a non-volatile memory device includes comparing the number of banks that are in operating states with a threshold value. If the number of the banks is smaller than the threshold value, data stored in a standby bank is read. If there is no bank having data to be read, a standby bank is programmed. If the number of the banks is equal to or greater than the threshold value or if the reading or the programming is performed, it is determined whether there is a reading or programming command to be performed. If there is the reading or programming command to be performed, the process is repeated from the comparing step. The programming may include programming of a most significant bit (MSB) page or a least significant bit (LSB) page. | 12-01-2011 |
20120089767 | STORAGE DEVICE AND RELATED LOCK MODE MANAGEMENT METHOD - A storage device comprises at least one nonvolatile memory and a lock mode management module. The lock mode management module places the storage device in a soft lock mode in which only predetermined writing operations are allowed, upon determining that a number of reserved blocks in a flash memory is less than or equal to a reference value. | 04-12-2012 |
20150026449 | METHOD OF MANAGING A SOLID STATE DRIVE, ASSOCIATED SYSTEMS AND IMPLEMENTATIONS - One embodiment of a method includes loading, by a memory controller, a boot image from a solid state drive to an operating memory of a computing system during an initialization operation of the computing system. The initialization operation initializes components of the computing system. | 01-22-2015 |