Patent application number | Description | Published |
20080205461 | Optical phase conjugation laser diode - A phase-conjugating resonator that includes a semiconductor laser diode apparatus that comprises a phase-conjugating array of retro-reflecting hexagon apertured hexahedral shaped corner-cube prisms, an electrically and/or optically pumped gain-region, a distributed bragg reflecting mirror-stack, a gaussian mode providing hemispherical shaped laser-emission-output metalized mirror. Wherein, optical phase conjugation is used to neutralize the phase perturbating contribution of spontaneous-emission, acoustic phonons, quantum-noise, gain-saturation, diffraction, and other intracavity aberrations and distortions that typically destabilize any stimulated-emission made to undergo amplifying oscillation within the inventions phase-conjugating resonator. Resulting in stablized high-power laser-emission-output into a single low-order fundamental transverse cavity mode and reversal of intra-cavity chirp that provides for high-speed internal modulation capable of transmitting data at around 20-Gigabits/ps. | 08-28-2008 |
20080305560 | Method for eliminating defects from semiconductor materials - Using a helium cryostat, the temperature for a substrate wafer(s) is reduced to 2.2 Kelvin over a period of twenty-four hours. Next, a soak segment will hold the temperature of the substrate wafer at 2.2 Kelvins for a period of ninety-six hours. At these low temperatures, alloys such as GaAs, InP, and GaP will form dipole molecular moments, which will re-align along lines of internal magnetic force as molecular bonds condense. Next the substrate wafer's temperature is ramped up to room temperature over a period of twenty-four hours. Next, the temperature of the substrate wafer is ramped up to assure that the temperature gradients made to occur within the wafer are kept low. Typically, a temper ramp up temperature will range between 300° F. to 1100° F. and depends upon the single crystal material used to construct the substrate wafer. Next, the substrate wafer undergoes a temper hold segment, which assures that the entire substrate wafer has had the benefit of the tempering temperature. A typical temper hold segment is around 3 hours and depends upon the material, thickness, and diameter size of the substrate wafer. | 12-11-2008 |
20090162948 | METHOD FOR ELIMINATING DEFECTS FROM SEMICONDUCTOR MATERIALS - Using a helium cryostat, the temperature for a substrate wafer(s) is reduced to 2.2 Kelvin over a period of twenty-four hours. Next, a soak segment will hold the temperature of the substrate wafer at 2.2 Kelvins for a period of ninety-six hours. At these low temperatures, alloys such as GaAs, InP, and GaP will form dipole molecular moments, which will re-align along lines of internal magnetic force as molecular bonds condense. Next the substrate wafer's temperature is ramped up to room temperature over a period of twenty-four hours. Next, the temperature of the substrate wafer is ramped up to assure that the temperature gradients made to occur within the wafer are kept low. Typically, a temper ramp up temperature will range between 300° F. to 1100° F. and depends upon the single crystal material used to construct the substrate wafer. Next, the substrate wafer undergoes a temper hold segment, which assures that the entire substrate wafer has had the benefit of the tempering temperature. A typical temper hold segment is around 3 hours and depends upon the material, thickness, and diameter size of the substrate wafer. | 06-25-2009 |
20090273839 | Method for constructing a phase conjugate mirror - A method that provides for a phase conjugate mirror | 11-05-2009 |
20100279446 | OPTICAL PHASE CONJUGATION LASER DIODE - A phase-conjugating resonator that includes a semiconductor laser diode apparatus that comprises a phase-conjugating array of retro-reflecting hexagon apertured hexahedral shaped corner-cube prisms, an electrically and/or optically pumped gain-region, a distributed bragg reflecting mirror-stack, a gaussian mode providing hemispherical shaped laser-emission-output metalized mirror. Wherein, optical phase conjugation is used to neutralize the phase perturbating contribution of spontaneous-emission, acoustic phonons, quantum-noise, gain-saturation, diffraction, and other intracavity aberrations and distortions that typically destabilize any stimulated-emission made to undergo amplifying oscillation within the inventions phase-conjugating resonator. Resulting in stablized high-power laser-emission-output into a single low-order fundamental transverse cavity mode and reversal of intra-cavity chirp that provides for high-speed internal modulation capable of transmitting data at around 20-Gigabits/ps. | 11-04-2010 |
Patent application number | Description | Published |
20080318137 | Lithography masks for improved line-end patterning - In one embodiment, a mask for use in semiconductor processing comprises a first region formed from a first material that is primarily opaque, a second region formed from a second material that is primarily transmissive, and a third region in which at least a portion of the second material is removed to generate a phase shift in radiation applied to the mask. | 12-25-2008 |
20090098469 | Process for fabrication of alternating phase shift masks - Design rules are described for a phase alternating shift mask for minimum chrome width and maximum segment length, where an embodiment employs during a cleaning process of the mask a megasonic power of 50 Watts at 1 MHz, and 30 Watts at 3 MHz. Some embodiments utilize an dry etch Carbon Tetrafluoride and Dioxygen based process. Other embodiments are described and claimed. | 04-16-2009 |
20120164563 | HIGH RESOLUTION PHASE SHIFT MASK - Techniques are disclosed for fabricating lithography masks, which include a first level process comprising lithography and etching to form mask frame and in-die areas, and a second level process comprising lithography and etching to form one or more mask features in the in-die area. At least one of the mask features has a smallest dimension in the nanometer range (e.g., 32 nm technology node, or smaller). The techniques may be embodied, for example, in a lithography mask for fabricating semiconductor circuits. In one such example case, the mask includes a frame area and an in-die area formed after the frame area. The in-die area includes one or more mask features, at least one of which has a smallest dimension of less than 100 nm. The mask has a critical dimension bias of less than 20 nm and a structure that comprises a substrate and an absorber layer. | 06-28-2012 |
20130216941 | LITHOGRAPHY MASK HAVING SUB-RESOLUTION PHASED ASSIST FEATURES - Techniques are disclosed for using sub-resolution phased assist features (SPAF) in a lithography mask to improve through process pattern fidelity and/or mitigate inverted aerial image problems. The technique also may be used to improve image contrast in non-inverted weak image sites. The use of SPAF in accordance with some such embodiments requires no adjustment to existing design rules, although adjustments can be made to enable compliance with mask inspection constraints. The use of SPAF also does not require changing existing fab or manufacturing processes, especially if such processes already comprehend phased shift mask capabilities. The SPAFs can be used to enhance aerial image contrast, without the SPAFs themselves printing. In addition, the SPAF phase etch depth can be optimized so as to make adjustments to a given predicted printed feature critical dimension. | 08-22-2013 |