Patent application number | Description | Published |
20090013029 | DEVICE, SYSTEM AND METHOD OF OPERATING A PLURALITY OF VIRTUAL LOGICAL SITES - Some demonstrative embodiments of the invention include, for example, devices, systems and methods of operating one or more virtual logical sites. A method may include, for example, running on a server at least one first virtual machine implementing at least part of a first virtual logical site, and at least one second virtual machine implementing at least part of a second virtual logical site interchangeable with the first virtual logical site. Other embodiments are described and claimed. | 01-08-2009 |
20090319580 | Hypervisor Service to Provide Image Version Control Support - A revision control service is included in a hypervisor. The revision control service manages revision control operations relating virtual machine images transparently to the virtual machine. The revision control service interacts with a conventional revision control program, stores relevant revision control metadata external to the virtual machine image with file-level granularity, and synchronizes virtual machine operations with the revision control operations. From the perspective of the virtual machine, the revision control service provides a clean image from which to boot, without modification of the revision control program. | 12-24-2009 |
20120240110 | OPTIMIZED DEPLOYMENT AND REPLICATION OF VIRTUAL MACHINES - Systems and methods for deploying a virtual machine (VM) on a host are provided. An exemplary method comprises notifying a host to download a master copy of a VM image from a remotely located network storage device, in response to a service provider providing a definition manifest for a service request supported by the VM, wherein the host deploys the VM directly from the VM image downloaded to a storage medium locally connected to the host machine, wherein deployment of the VM allows the host to locally service the service request associated with the definition manifest, wherein the host replicates copies of the VM image, in response to receiving additional service requests to create one or more VM clones; wherein the host customizes the one or more VM clones based on the definition manifest. | 09-20-2012 |
Patent application number | Description | Published |
20110209155 | SPECULATIVE THREAD EXECUTION WITH HARDWARE TRANSACTIONAL MEMORY - In an embodiment, if a self thread has more than one conflict, a transaction of the self thread is aborted and restarted. If the self thread has only one conflict and an enemy thread of the self thread has more than one conflict, the transaction of the self thread is committed. If the self thread only conflicts with the enemy thread and the enemy thread only conflicts with the self thread and the self thread has a key that has a higher priority than a key of the enemy thread, the transaction of the self thread is committed. If the self thread only conflicts with the enemy thread, the enemy thread only conflicts with the self thread, and the self thread has a key that has a lower priority than the key of the enemy thread, the transaction of the self thread is aborted. | 08-25-2011 |
20130198749 | SPECULATIVE THREAD EXECUTION WITH HARDWARE TRANSACTIONAL MEMORY - In an embodiment, if a self thread has more than one conflict, a transaction of the self thread is aborted and restarted. If the self thread has only one conflict and an enemy thread of the self thread has more than one conflict, the transaction of the self thread is committed. If the self thread only conflicts with the enemy thread and the enemy thread only conflicts with the self thread and the self thread has a key that has a higher priority than a key of the enemy thread, the transaction of the self thread is committed. If the self thread only conflicts with the enemy thread, the enemy thread only conflicts with the self thread, and the self thread has a key that has a lower priority than the key of the enemy thread, the transaction of the self thread is aborted. | 08-01-2013 |
Patent application number | Description | Published |
20080301656 | METHOD OF PROCEDURE CONTROL DESCRIPTOR-BASED CODE SPECIALIZATION FOR CONTEXT SENSITIVE MEMORY DISAMBIGUATION - A computer implemented method, apparatus, and computer program product for compiling source code. The source code is scanned to identify a candidate region. A procedure control descriptor is corresponding to the candidate region is generated. The procedure control descriptor identifies, for the candidate region, a condition which, if true at runtime means that the candidate region can be specialized. Responsive to a determination during compile time that satisfaction of at least one condition will be known only at runtime, the procedure control descriptor is used to specialize the candidate region at compile time to create a first version of the candidate region for execution in a case where the condition is true and a second version of the candidate region for execution in a case where the condition is false. Also responsive to the determination, code is further generated to correctly select one of the first region and the second region at runtime. | 12-04-2008 |
20090077545 | PIPELINED PARALLELIZATION OF MULTI-DIMENSIONAL LOOPS WITH MULTIPLE DATA DEPENDENCIES - A mechanism for folding all the data dependencies in a loop into a single, conservative dependence. This mechanism leads to one pair of synchronization primitives per loop. This mechanism does not require complicated, multi-stage compile time analysis. This mechanism considers only the data dependence information in the loop. The low synchronization cost balances the loss in parallelism due to the reduced overlap between iterations. Additionally, a novel scheme is presented to implement required synchronization to enforce data dependences in a DOACROSS loop. The synchronization is based on an iteration vector, which identifies a spatial position in the iteration space of the loop. Multiple iterations executing in parallel have their own iteration vector for synchronization where they update their position in the iteration space. As no sequential updates to the synchronization variable exist, this method exploits a greater degree of parallelism. | 03-19-2009 |
20090106745 | Method and Apparatus for Optimizing Software Program Using Inter-Procedural Strength Reduction - Inter-procedural strength reduction is provided by a mechanism of the present invention to optimize software program. During a forward pass, the present invention collects information of global variables and analyzes the information to select candidate computations for optimization. During a backward pass, the present invention replaces costly computations with less costly or weaker computations using pre-computed values and inserts store operations of new global variables to pre-compute the costly computations at definition points of the global variables used in the costly computations. | 04-23-2009 |
20090158018 | Method and System for Auto Parallelization of Zero-Trip Loops Through the Induction Variable Substitution - A method and system of auto parallelization of zero-trip loops that substitutes a nested basic linear induction variable by exploiting a parallelizing compiler is provided. Provided is a use of a max{0,N} variable for loop iterations in case of no information is known about the value of N, for a typical loop iterating from 1 to N, in which N is the loop invariant. For the nested basic induction variables, an induction variable substitution process is applied to the nested loops starting from the innermost loop to the outermost one. Then a removal of the max operator afterwards through a copy propagation pass of the IBM compiler is provided. In doing so, the loop dependency on the induction variable is eliminated and an opportunity for a parallelizing compiler to parallel the outermost loop is provided. | 06-18-2009 |
20100077153 | Optimal Cache Management Scheme - Computer implemented method, system and computer usable program code for cache management. A cache is provided, wherein the cache is viewed as a sorted array of data elements, wherein a top position of the array is a most recently used position of the array and a bottom position of the array is a least recently used position of the array. A memory access sequence is provided, and a training operation is performed with respect to a memory access of the memory access sequence to determine a type of memory access operation to be performed with respect to the memory access. Responsive to a result of the training operation, a cache replacement operation is performed using the determined memory access operation with respect to the memory access. | 03-25-2010 |
20100162220 | Code Motion Based on Live Ranges in an Optimizing Compiler - Optimizing program code in a static compiler by determining the live ranges of variables and determining which live ranges are candidates for moving code from the use site to the definition site of source code. Live ranges for variables in a flow graph are determined. Selected live ranges are determined as candidates in which code will be moved from a use site within the source code to a definition site within the source code. Optimization opportunities within the source code are identified based on the code motion. | 06-24-2010 |
20110289303 | SETJMP/LONGJMP FOR SPECULATIVE EXECUTION FRAMEWORKS - A process for check pointing in speculative execution frameworks, identifies calls to a set of setjmp/longjmp instructions to form identified calls to setjmp/longjmp, determines a control flow path between a call to a setjmp and a longjmp pair of instructions in the identified calls to setjmp/longjmp and replaces calls to the setjmp/longjmp pair of instructions with calls to an improved_setjmp and improved_longjmp instruction pair. The process creates a context data structure in memory, computes a non-volatile save/restore set and replaces the call to improved_setjmp of the setjmp/longjmp pair of instructions with instructions to save all required non-volatile and special purpose registers and replaces a call to improved_longjmp of the setjmp/longjmp pair of instructions with instructions to restore all required non-volatile and special purpose registers and to branch to an instruction immediately following a block of code containing the call to improved_setjmp. | 11-24-2011 |