Patent application number | Description | Published |
20090019425 | DATA SPLITTING FOR RECURSIVE DATA STRUCTURES - Embodiments of the present invention provide a method, system and computer program product for the data splitting of recursive data structures. In one embodiment of the invention, a method for data splitting recursive data structures can be provided. The method can include identifying data objects of a recursive data structure type, such as a linked list, within source code, the recursive data structure type defining multiple different data fields. The method further can include grouping the data objects into some memory pool units, each of which can contain the same number of data objects. Each memory pool unit can be seen as an array of data objects. The method can include data splitting, which could be maximal array splitting in each different memory pool unit. Finally, the method can include three different approaches, including field padding, field padding and field splitting, to handle irregular field sizes in the data structure. | 01-15-2009 |
20090064119 | Systems, Methods, And Computer Products For Compiler Support For Aggressive Safe Load Speculation - Systems, methods and computer products for compiler support for aggressive safe load speculation. Exemplary embodiments include a method for aggressive safe load speculation for a compiler in a computer system, the method including building a control flow graph, identifying both countable and non-countable loops, gathering a set of candidate loops for load speculation, for each candidate loop in the set of candidate loops gathered for load speculation performing computing an estimate of the iteration count, delay cycles, and code size, performing a profitability analysis and determine an unroll factor based on the delay cycles and the code size, transforming the loop by generating a prologue loop to achieve data alignment and an unrolled main loop with loop directives, indicating which loads can safely be executed speculatively and performing low-level instruction on the generated unrolled main loop. | 03-05-2009 |
20090064121 | SYSTEMS, METHODS, AND COMPUTER PRODUCTS FOR IMPLEMENTING SHADOW VERSIONING TO IMPROVE DATA DEPENDENCE ANALYSIS FOR INSTRUCTION SCHEDULING - Systems, methods and computer products for implementing shadow versioning to improve data dependence analysis for instruction scheduling. Exemplary embodiments include a method to identify loops within the code to be compiled, for each loop a dependence initializing a matrix, for each loop shadow identifying symbols that are accessed by the loop, examining dependencies, storing, comparing and classifying the dependence vectors, generating new shadow symbols, replacing the old shadow symbols with the new shadow symbols, generating alias relationships between the newly created shadow symbols, scheduling instructions and compiling the code. | 03-05-2009 |
20110016460 | MULTIPLE PASS COMPILER INSTRUMENTATION INFRASTRUCTURE - A method includes configuring one or more processors to perform operations. The operations include instrumenting at least one code region of an application with at least one annotation for generating profile data when the at least one code region is executed. The operations include executing the application to generate profile data for the at least one code region. The operations also include identifying, from the profile data, a delinquent code region from the generated profile data. The operations include instrumenting the delinquent code region with annotations for generating profile data when the code regions are executed. The operations include executing the application to generate additional profile data for the at least one code region, including the delinquent code region. | 01-20-2011 |
20110072419 | MAY-CONSTANT PROPAGATION - May-constant propagation is a technique used to propagate a constant through the call graph and control flow graph by ignoring possible kills and re-definitions with low probability. Variables associated with constants in program code are determined. Execution flow probabilities are executed for code segments of the program code that comprise the variables. The execution flow probabilities are calculated based on flow data for the program code. At least a first of the code segments is determined to have a high execution flow probability. The first of the constants associated with the first variable are propagated through the flow data to generate modified flow data. | 03-24-2011 |
Patent application number | Description | Published |
20080229297 | METHOD AND SYSTEM FOR REDUCING MEMORY REFERENCE OVERHEAD ASSOCIATED WITH TREADPRIVATE VARIABLES IN PARALLEL PROGRAMS - A computer implemented method, system and computer program product for accessing threadprivate memory for threadprivate variables in a parallel program during program compilation. A computer implemented method for accessing threadprivate variables in a parallel program during program compilation includes aggregating threadprivate variables in the program, replacing references of the threadprivate variables by indirect references, moving address load operations of the threadprivate variables, and replacing the address load operations of the threadprivate variables by calls to runtime routines to access the threadprivate memory. The invention enables a compiler to minimize the runtime routines call times to access the threadprivate variables, thus improving program performance. | 09-18-2008 |
20080301656 | METHOD OF PROCEDURE CONTROL DESCRIPTOR-BASED CODE SPECIALIZATION FOR CONTEXT SENSITIVE MEMORY DISAMBIGUATION - A computer implemented method, apparatus, and computer program product for compiling source code. The source code is scanned to identify a candidate region. A procedure control descriptor is corresponding to the candidate region is generated. The procedure control descriptor identifies, for the candidate region, a condition which, if true at runtime means that the candidate region can be specialized. Responsive to a determination during compile time that satisfaction of at least one condition will be known only at runtime, the procedure control descriptor is used to specialize the candidate region at compile time to create a first version of the candidate region for execution in a case where the condition is true and a second version of the candidate region for execution in a case where the condition is false. Also responsive to the determination, code is further generated to correctly select one of the first region and the second region at runtime. | 12-04-2008 |
20090106745 | Method and Apparatus for Optimizing Software Program Using Inter-Procedural Strength Reduction - Inter-procedural strength reduction is provided by a mechanism of the present invention to optimize software program. During a forward pass, the present invention collects information of global variables and analyzes the information to select candidate computations for optimization. During a backward pass, the present invention replaces costly computations with less costly or weaker computations using pre-computed values and inserts store operations of new global variables to pre-compute the costly computations at definition points of the global variables used in the costly computations. | 04-23-2009 |
20100077153 | Optimal Cache Management Scheme - Computer implemented method, system and computer usable program code for cache management. A cache is provided, wherein the cache is viewed as a sorted array of data elements, wherein a top position of the array is a most recently used position of the array and a bottom position of the array is a least recently used position of the array. A memory access sequence is provided, and a training operation is performed with respect to a memory access of the memory access sequence to determine a type of memory access operation to be performed with respect to the memory access. Responsive to a result of the training operation, a cache replacement operation is performed using the determined memory access operation with respect to the memory access. | 03-25-2010 |
20100095271 | Fine-Grained Software-Directed Data Prefetching Using Integrated High-Level and Low-Level Code Analysis Optimizations - A mechanism for minimizing effective memory latency without unnecessary cost through fine-grained software-directed data prefetching using integrated high-level and low-level code analysis and optimizations is provided. The mechanism identifies and classifies streams, identifies data that is most likely to incur a cache miss, exploits effective hardware prefetching to determine the proper number of streams to be prefetched, exploits effective data prefetching on different types of streams in order to eliminate redundant prefetching and avoid cache pollution, and uses high-level transformations with integrated lower level cost analysis in the instruction scheduler to schedule prefetch instructions effectively. | 04-15-2010 |