Hsu, NY
Anna Hsu, Larchmont, NY US
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20130096988 | NOMINATION ENGINE - A system and method for nominating candidate enterprises for inclusion in a competitive set assembled for the purpose of competitively analyzing a subject enterprise. Characteristics of the subject enterprise in which the subject enterprise is comparable to a plurality of candidate enterprises are identified. The characteristics may include location, size of the physical presence, a dollar volume of revenue, classification of the business engaged, market share, average purchase size; of the subject purchase frequency of customers; size of customer base; demographic characteristics of the customer base, location of customers, degree of customer loyalty, and share of the customer's wallet. A list candidate enterprises is compiled based upon a predetermined degree of similarity between the subject enterprise and/or an identified competitor enterprise on the one hand, and the candidate enterprise on the other. A plurality of nominee enterprises are selected from the list of candidates to populate the competitive set. | 04-18-2013 |
20130226803 | METHOD AND SYSTEM FOR AUTHENTICATING AN ENTITY USING TRANSACTION PROCESSING - A system for authenticating an entity includes a database configured to store a profile associated with an entity, the profile including at least an authentication status; a supplying device configured to supply transaction details including a unique virtual payment number (VPN) to a third party entity to be authenticated; a receiving means for receiving an authorization request that includes transaction details that include a VPN; and a processor configured to capture, from the authorization request, transaction details for a payment card transaction wherein the transaction details includes at least a payment card number, authenticate the entity requesting a transaction by comparing the captured transaction details including a payment card number to the supplied unique VPN, and update, in the database, the authentication status in the profile associated with the entity based on the authenticating of the entity based on said authentication. | 08-29-2013 |
Chun-Ming Hsu, Hopewell Junction, NY US
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20100329403 | DYNAMIC QUADRATURE CLOCK CORRECTION FOR A PHASE ROTATOR SYSTEM - A system and method for closed loop clock correction includes adjusting two or more input signals comprising at least one in-phase clock and one quadrature clock, and applying adjusted quadrature clock signals to a device capable of generating a 4-quadrant interpolated output clock phase. An interpolated output clock phase is delayed to form a clock for a measurement device. Two or more adjusted input signals are measured on a measurement device over a range of interpolated output clock phases. Errors are determined on the in-phase clock and the quadrature clock using sampled information from the measurement device. The in-phase clock and the quadrature clock are adapted using determined error information. | 12-30-2010 |
Chunwei Hsu, New York, NY US
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20130156076 | Circuits and Methods for a Combined Phase Detector - Circuits and methods for a combined phase detector are provided. In some embodiments, circuits for a combined phase detector are provided, the circuits comprising: a tri-state phase frequency detector and charge pump that receives a reference signal and a first input signal, and that produces a first output signal; and a sub-sampling phase detector that receives the reference signal and a second input signal, and that outputs a second output signal, wherein the first output signal and the second output signal are coupled together. | 06-20-2013 |
David H. Hsu, Great Neck, NY US
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20100085916 | Systems and Methods for Hybrid Wired and Wireless Universal Access Networks - A method for operating a network having one or more nodes wherein each of the nodes having one or more resources, comprising the steps of: forming the network using one or more nodes, wherein certain one or more of the nodes is a gateway connecting to two or more different network connection types; and managing the one or more nodes of the network; wherein the nodes are segregated into one or more cells each having one or more of the nodes and one or more supernodes; wherein the nodes within the same cell are interconnected; and wherein the supernodes are interconnected. | 04-08-2010 |
20100085948 | Apparatuses for Hybrid Wired and Wireless Universal Access Networks - A gateway switch comprises: two or more transceiving modules, wherein each of the transceiving modules is capable of transmitting and receiving data, wherein the data is an analog signal or a digital signal, and wherein each of the transceiving modules provides a different network connection type; a system module for processing the received data in accordance with one or more rules; and a switching module for symmetrically switching the processed data from any one of the transceiving modules to a selected one of the transceiving modules for transmission of the processed data; wherein the system module selects one of the transceiving modules for the transmission of the processed data as a function of the rules. | 04-08-2010 |
Georgiana Hsu, Bronx, NY US
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20080295371 | Exit sign illuminated by color LEDs - An exit sign comprising a housing and a plurality of LEDs that activates to produce yellow color light. The plurality of LEDs are mounted in the housing. Means for passing light from the plurality of LEDs in the form of indicia symbolizing an exit enables viewing by an observer, such means includes a stencil having four independent letters forming the word EXIT. DC circuitry is in operative electrical connection with the plurality of LEDs. A source of AC electrical power activates the DC circuitry. The plurality of LEDs can be both red color output LEDs and green color output LEDs, or the plurality of LEDs can be bicolor red and green LEDs having the capability of producing both red light and green light. The red light and green light are additively mixed to produce yellow light. In the alternative, the plurality of LEDs can be yellow color output LEDs or the plurality of LEDs can be white color output LEDs. The color light from the plurality of LEDs pass through either a red color diffusion filter to produce red light indicia, or a green color diffusion filter to produce green light indicia. An emergency power backup battery is connected to the plurality of LEDs. Means for producing emergency light is optional. | 12-04-2008 |
20110057572 | Voltage regulating devices in LED lamps with multiple power sources - LED driver circuits containing voltage reducing devices, voltage regulating devices, and voltage converting devices are disclosed as the main components to provide power to LEDs. The LED driver circuits are designed to work with a ballast, mains alternating current voltage, direct current voltage, and electromagnetic induction power. The voltage regulating devices can be a resistor in series with at least one zener diode or a voltage regulator both in parallel with and providing power to the LEDs. The LEDs can also be anti-parallel diode pairs consisting of one diode and one LED or two LEDs, or the LEDs can be anti-parallel diode string pairs consisting of diodes and LEDs or all LEDs. The LED driver circuits will be incorporated into LED replacement lamps, and in particular to LED lamps to replace fluorescent lamps for use with existing ballasts and other power sources where the ballast may be removed or bypassed. | 03-10-2011 |
20110232143 | Exit sign illuminated by color leds - An exit sign comprising a housing, a plurality of green color LEDs and red color LEDs or bicolor green and red color LEDs positioned in the housing for emitting both a green color light and a red color light with a filter holder for holding a selected green color filter or a selected red color filter for passing the selected green color light or selected red color light to a stencil having openings for passing the selected green color light or selected red color light to an observer. Yellow color LEDs can be alternatively positioned in the housing for emitting yellow color light comprising both green color light and red color light. White color LEDs can also be alternatively positioned in the housing for emitting white color light also comprising both green color light and red color light. | 09-29-2011 |
Jason J. Hsu, New York, NY US
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20100055116 | Methods and Compositions for Targeting c-Rel - The present invention relates to compositions and methods for targeting c-Rel. In particular, the present invention provides compositions and methods for treating cancers, inflammatory diseases, autoimmune diseases, and transplant rejection by inhibiting c-Rel activity and for regulating c-Rel for research and drug screening applications. | 03-04-2010 |
Johnny Hsu, Brooklyn, NY US
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20150025999 | Product Selection Packaging and Method of Use Thereof - Product selection packaging for a consumer product that improves the consumer's ability to quickly sort through numerous criteria in a complex decision making process and determine whether that particular consumer product is appropriate for his or her purchase and use is disclosed. The product selection packaging, which is designed for a consumer product includes (a) an interface; and (b) at least one product selection indicia associated with the interface, wherein the selection indicia assist the consumer with determining whether or not the product is appropriate for the consumer's purchase or use. | 01-22-2015 |
Katharine Hsu, New York, NY US
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20150361506 | DONOR KIR3DL1 AND HLA-B SUBTYPES AND LEUKEMIA CONTROL IN HLA-COMPATIBLE ALLOGENIC HEMATOPOIETIC STEM CELL TRANSPLANTATION - This disclosure generally relates to donor selection for hematopoietic stem cell transplantation. In particular, this disclosure relates to typing KIR3DL1 and HLA-B alleles as basis for donor selection. | 12-17-2015 |
Louis Hsu, Fishkill, NY US
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20080301597 | Method to Determine the Root Causes of Failure Patterns by Using Spatial Correlation of Tester Data - A method for determining the root causes of fail patterns in integrated circuit chips is provide wherein a known integrated circuit chip layout is used to identify a plurality of potential defects and a plurality of potential fail patterns in the integrated circuit chip. Correlations between the potential defects and the potential fail patterns that result from those defects are identified. Based on this identification, the potential fail patterns are grouped by common potential defect. An actual integrated circuit chip that is manufactured in accordance with the test layout is tested for failure patterns. These failure patterns are then compared to the groupings of potential fail patterns. When a match is found, that is when a given group of fail patterns is found in the actual integrated circuit chip, then the potential defect associated with the potential fail patterns to which the actual fail patterns are matched is identified. This defect is the root cause of the failure pattern in the actual chip. | 12-04-2008 |
20090033355 | Method And Apparatus To Measure Threshold Shifting Of A MOSFET Device And Voltage Difference Between Nodes - An on-chip circuit to quantitatively measure threshold voltage shifts of a MOSFET. The circuit includes a programmable Vt reference sensor; a programmable Vt monitoring sensor; and a comparator for receiving inputs from the reference and monitoring sensors providing an output flag signal. The shifting of the MOSFET device voltage threshold monitors process variations, geometry sensitivity, plasma damage, stress, and hot carriers and other device damages. The same circuit also measures voltage differences between any two nodes in an integrated circuit chip or wafer. | 02-05-2009 |
20090111235 | Semiconductor Integrated Circuit Devices Having High-Q Wafer Back-Side Capacitors - Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip capacitors formed on the chip back-side and connected to integrated circuits on the chip front-side using through-wafer interconnects. In one aspect, a semiconductor device includes a semiconductor substrate having a front side, a back side, and a buried insulating layer interposed between the front and back sides of the substrate. An integrated circuit is formed on the front side of the semiconductor substrate, an integrated capacitor is formed on the back side of the semiconductor substrate, and an interconnection structure is formed through the buried insulating layer to connect the integrated capacitor to the integrated circuit. | 04-30-2009 |
20090312046 | INTELLIGENT WIRELESS POWER CHARGING SYSTEM - A system and methodology for intelligent power management of wirelessly networked devices. The system provides for reliable wireless communication via a wireless power charging method and, a method to maintain power capacity of batteries in a wireless device. The batteries are charged via an RF harvesting unit embedded inside the wireless device. An intelligent wireless power charging system further comprises at least two batteries and at least two RF adaptor devices coupled to an AC power line. The first adaptor is set for data communication while the second adaptor is used to transmit the power. In addition, when a first battery is in use during active mode, the second battery is subjected to wireless charging. | 12-17-2009 |
Louis C. Hsu, Hopewell Junction, NY US
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20080298520 | High-speed multi-mode receiver - A data receiver is provided which is operable to receive a signal controllably pre-distorted and transmitted by a transmitter, to generate information for adjusting the pre-distortion applied to the signal transmitted by the transmitter, and to transmit the information to the transmitter. The receiver is further operable to perform adaptive equalization to receive the signal transmitted by the transmitter. | 12-04-2008 |
Louis C. Hsu, Fishikill, NY US
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20090302387 | INTEGRATED CIRCUIT CHIP WITH FETS HAVING MIXED BODY THICKNESSES AND METHOD OF MANUFACTURE THEREOF - An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FETs. The SOI FETs may include Partially Depleted SOI (PD-SOI) FETs and Fully Depleted SOI (FD-SOI) FETs and the chip may include bulk FETs as well. The FETs are formed by contouring the surface of a wafer, conformally implanting oxygen to a uniform depth, and planarizing to remove the Buried OXide (BOX) in bulk FET regions. | 12-10-2009 |
Louis L. Hsu, Hopewell Junction, NY US
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20110069425 | MODULARIZED THREE-DIMENSIONAL CAPACITOR ARRAY - A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage. | 03-24-2011 |
Louis L. Hsu, Fishkil, NY US
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20080258555 | MULTI-LEVEL POWER SUPPLY SYSTEM FOR A COMPLEMENTARY METAL OXIDE SEMICONDUCTOR CIRCUIT - There is provided a circuit for managing a multi-level power supply. The circuit includes a comparator that compares a voltage level (Vs1) of a lower voltage supply bus to a voltage level (Vs2) of a higher voltage supply bus, and a switch that routes current from the lower voltage supply bus to the higher voltage supply bus if Vs210-23-2008 | |
20100201403 | MULTI-LEVEL POWER SUPPLY SYSTEM FOR A COMPLEMENTARY METAL OXIDE SEMICONDUCTOR - There is provided a method that includes comparing a voltage level (Vs | 08-12-2010 |
Louis L. Hsu, Fish Kill, NY US
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20080229144 | FLEXIBLE ROW REDUNDANCY SYSTEM - A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; wherein the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size. | 09-18-2008 |
Louis L.c. Hsu, Fishkill, NY US
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20080239784 | HIGH DENSITY PLANAR MAGNETIC DOMAIN WALL MEMORY APPARATUS - A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a single write wire having a longitudinal axis substantially orthogonal to a longitudinal axis of each of the coplanar shift register structures. | 10-02-2008 |
20080239785 | HIGH DENSITY PLANAR MAGNETIC DOMAIN WALL MEMORY APPARATUS - A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a write wire having a constriction therein, the constriction located at a point corresponding to the location of the plurality of discontinuities in the associated shift register structure. | 10-02-2008 |
20080243972 | HIGH DENSITY PLANAR MAGNETIC DOMAIN WALL MEMORY APPARATUS AND METHOD OF FORMING THE SAME - A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a single write wire having a longitudinal axis substantially orthogonal to a longitudinal axis of each of the coplanar shift register structures. | 10-02-2008 |
20080253177 | Write Operations for Phase-Change-Material Memory - Improved write operation techniques for use in phase-change-material (PCM) memory devices are disclosed. By way of one example, a method of performing a write operation in a phase-change-material memory cell, the memory cell having a set phase and a reset phase associated therewith, comprises the following steps. A word-line associated with the memory cell is monitored. Performance of a write operation to the memory cell for the set phase is initiated when the word-line is activated. The write operation to the memory cell for the set phase may then be continued when valid data for the set phase is available. A write operation to the memory cell for the reset phase may be performed when valid data for the reset phase is available. Other improved PCM write operation techniques are disclosed. | 10-16-2008 |
Louis L. C. Hsu, Fishkill, NY US
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20080308801 | STRUCTURE FOR STOCHASTIC INTEGRATED CIRCUIT PERSONALIZATION - A method of forming a stochastically based integrated circuit encryption structure includes forming a lower conductive layer over a substrate, forming a short prevention layer over the lower conductive layer, forming an intermediate layer over the short prevention layer, wherein the intermediate layer is characterized by randomly structured nanopore features. An upper conductive layer is formed over the random nanopore structured intermediate layer. The upper conductive layer is patterned into an array of individual cells, wherein a measurable electrical parameter of the individual cells has a random distribution from cell to cell with respect to a reference value of the electrical parameter. | 12-18-2008 |
20090190413 | SELF-REPAIR INTEGRATED CIRCUIT AND REPAIR METHOD - A method for repairing degraded field effect transistors includes forward biasing PN junctions of one of a source and a drain of a field effect transistor (FET), and a body of the FET. Charge is injected from a substrate to a gate region to neutralize charge in the gate region. The method is applicable to CMOS devices. Repair circuits are disclosed for implementing the repairs. | 07-30-2009 |
20090302405 | METHOD FOR FORMING SLOT VIA BITLINE FOR MRAM DEVICES - A magnetic random access memory (MRAM) device includes a magnetic tunnel junction (MTJ) stack formed over a lower wiring level, a hardmask formed on the MTJ stack, and an upper wiring level formed over the hardmask. The upper wiring level includes a slot via bitline formed therein, the slot via bitline in contact with the hardmask and in contact with an etch stop layer partially surrounding sidewalls of the hardmask. | 12-10-2009 |
20130223172 | SELF-REPAIR INTEGRATED CIRCUIT AND REPAIR METHOD - A method for repairing degraded field effect transistors includes forward biasing PN junctions of one of a source and a drain of a field effect transistor (FET), and a body of the FET. Charge is injected from a substrate to a gate region to neutralize charge in the gate region. The method is applicable to CMOS devices. Repair circuits are disclosed for implementing the repairs. | 08-29-2013 |
Ming Feng Hsu, Niskayuna, NY US
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20090004379 | METHOD OF PREPARING WETTING-RESISTANT SURFACES AND ARTICLES INCORPORATING THE SAME - The present invention provides methods for manufacturing an article having a wetting-resistant surface. The method includes providing a mixture comprising a plurality of micron-sized first particles and a plurality of nano-sized second particles, and a binder; depositing the mixture onto a substrate to form a wetting-resistant surface via a thermal spray process. The mixture is deposited without substantial melting of the first and second particles. The wetting-resistant surface has wettability sufficient to generate, with a reference fluid, a static contact angle of greater than about 90 degrees. | 01-01-2009 |
20100034335 | ARTICLES HAVING ENHANCED WETTABILITY - Articles having surfaces with enhanced wetting properties are presented. One embodiment is an article having a surface configured for promoting a phase transformation from a liquid phase to a vapor phase. The article comprises an element comprising a surface disposed to be in contact with a liquid to be transformed to a vapor, and the surface comprises a plurality of surface features having a median feature size, a, and a median feature spacing, b, such that the ratio b/a is up to about 8. The surface comprises a material disposed to contact the liquid, and this material has a nominal wettability sufficient to generate a nominal contact angle of up to about 80 degrees with a drop of the liquid. Another embodiment is a fuel rod for a nuclear reactor comprising a surface configured as described above. | 02-11-2010 |
Nelson Hsu, New York, NY US
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20100328714 | PRINTING APPARATUS AND CONTROLLER THEREFOR - A computer program embodied on a computer readable medium, said computer program configured to control a controller to: output, to a display driver, data for causing the display driver to drive a display of a printing apparatus to display, in a first area of the display, a plurality of images including a first image, wherein the plurality of images are representative of a plurality of respective different types of label data field, and to display a second image representative of the appearance of a label medium occupying a second area of the display that is different from the first area; and in response to receiving, from a selector, information comprising data representative of an operation of the selector by a user to select the first image and data representative of a position within the second area, output, to the display driver, data for causing the display driver to drive the display to display a revised version of the second image representative of the appearance of the label medium; wherein the revised version of the second image comprises a label data field of the type of label data field of which the first image is representative, and wherein the label data field comprised in the revised version of the second image is located at a location determined in dependence on said position within the second area. | 12-30-2010 |
Timothy Hsu, Jackson Heights, NY US
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20110251239 | COMBINATION THERAPY FOR THE TREATMENT OF DEMENTIA - Provided herein is a combination therapy useful for the treatment of Alzheimer's disease and Alzheimer's disease related dementia. The combination comprises memantine in an immediate or sustained release form and donepezil in a sustained release form. | 10-13-2011 |
Tony Hsu, Flushing, NY US
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20090125438 | TRADING TOOL TO ENHANCE STOCK AND COMMODITY INDEX EXECUTION - The invention provides systems and methods for providing replicable financial instrument orders, and establishing a fill price that is better than the theoretical upper limit of the industries' best order execution. The system has the capability of transforming a client's index order into a replicable product, such as index futures and/or baskets of the underlying stocks. The system selects whichever method and combination of securities that will achieve the best expected execution for the particular market. The system achieves the best price and execution efficiency by utilizing dynamic market information across all possible liquidity formats, liquidity pools, and high performance trading systems, delivering a product that has multiple forms at the best possible price. The result is a better final execution price that outperforms current industry practices for best order execution. The system delivers the fill order in the original liquidity format at the price, or equivalent price, of the replicable product. | 05-14-2009 |
Tsungda Hsu, New York, NY US
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20120141533 | MYCOBACTERIAL MUTANTS INDUCING IL-12 - Provided are mycobacteria deleted in at least a portion of a region 3 ESAT-6-like gene cluster. Also provided are mycobacteria comprising a mutation in an roc-1 gene. Additionally, vaccines comprising these mycobacteria are provided. Further provided are methods of making a recombinant mycobacterium, methods of inducing an immune response in a mammal, methods of inhibiting IL-12 production in a mammal, and methods of stimulating IL-12 production in a mammal. Vaccine adjuvants are also provided, as are methods of inducing immunity to a target antigen in a mammal. | 06-07-2012 |
Yanshen Hsu, Staten Island, NY US
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20100113193 | BAMBOO BAT HAVING FIBER-FUSED CORE AND METHOD OF MANUFACTURING THE SAME - A baseball bat has a core section formed exclusively of bamboo fibers fused together and an outer section substantially surrounding the core section. In a method for fabricating a blank from which a baseball bat is fabricated, a core section is fabricated through harvesting elongated bamboo pieces, removing the epidermis or skin from the bamboo pieces, cutting the bamboo pieces into a predetermined length, fiberizing the bamboo pieces, fusing the bamboo fibers to form a solid and unitary core blank, and processing the solid core blank to provide a core section have a substantially square cross section having opposite front and rear sides and opposite top and bottom sides. | 05-06-2010 |
20100323831 | BAMBOO BAT HAVING FIBER-FUSED CORE AND METHOD OF MANUFACTURING THE SAME - A baseball bat has a core section formed of wood fibers artificially fused together and an outer section substantially surrounding the core section. The core section can be made exclusively of bamboo fibers artificially fused together. The core section can be substantially square having opposite front and rear sides and opposite top and bottom sides. The outer section has opposite side subsections, adhered to the sides of the core section. The side subsections have material strips arranged substantially in a first direction. The outer section further has a top subsection and a bottom subsection, adhered to the top and bottom of the core section, respectively. The top and bottom subsection have material strips arranged substantially in a second direction. The first direction and the second direction can be perpendicular to each other. | 12-23-2010 |
20110312452 | BAT HAVING FIBER-FUSED CORE SECTION AND METHOD OF MANUFACTURING THE SAME - A bat has a core section made from wood or grass material fibers artificially fused together and an outer section for substantially surrounding the core section. The core section can be made exclusively of bamboo fibers artificially fused together. The outer section has opposite bottom and top subsections and opposite side subsections, adhered to corresponding sides of the core section. The outer section can be made of bamboo strips. The bat also has an insert or plug made of a wood material. The insert or plug is disposed in a void provided in a distal end portion of the bat. | 12-22-2011 |