Patent application number | Description | Published |
20080301593 | Method For Automatic Clock Gating To Save Power - A power optimization method of deriving gated circuitry in a synthesized netlist of an integrated circuit (IC) design is provided. A block in the synthesized netlist is identified as an idle candidate block. Sub-blocks on the chip are clustered into a cluster. For the cluster, a clock gating structure optimized for power savings is determined, based on the idle candidate block. One or more inflexible clock gates are inserted in the netlist according to the clock gate structure. | 12-04-2008 |
20080301594 | Method For Optimized Automatic Clock Gating - A method of optimizing clock-gated circuitry in an integrated circuit (IC) design is provided. A plurality of signals which feed into enable inputs of a plurality of clock gates is determined, where the clock gates gate a plurality of sequential elements in the IC design. Combinational logic which is shared among the plurality of signals is identified. The clock-gated circuitry is transformed into multiple levels of clock-gating circuitry based on the shared combinational logic. | 12-04-2008 |
20090100296 | System and method for verifying the transmit path of an input/output component - A system and method for verifying the transmit path of an input/output device such as a network interface circuit. The device's operation with various different input sources (e.g., hosts, input buses) and output sources (e.g., output buses, networks) is modeled in a verification layer that employs multiple queues to simulate receipt of input data, submission to an output port and transmission from the device. Call backs are employed to signal completion of events related to receipt of data at the device and modeling of data processing within the verification layer. As call backs are resolved, corresponding tasks are executed to advance the processing of the data through the verification layer. A device-specific algorithm is executed in the verification layer to predict the ordering of output from the device, and that output is compared to the predicted output by a transmission checker. | 04-16-2009 |
20090100297 | System and method for verifying the receive path of an input/output component - A system and method for verifying the receive path of an input/output device such as a network interface circuit. The device's operation with various different input sources (e.g., networks) and output sources (e.g., hosts, host buses) is modeled in a verification layer that employs multiple queues to simulate receipt of packets, calculation of destination addresses and storage of the packet data by the device. Call backs are employed to signal completion of events related to storage of packet data by the device and modeling of data processing within the verification layer. Processing of tokens within the verification layer to mimic the device's processing of corresponding packets is performed according to a dynamic DMA policy modeled on the device's policy. The policy is dynamic and can be updated or replaced during verification without interrupting the verification process. | 04-16-2009 |
20090168657 | System and Method for Validating Packet Classification - A system and method for validating packet classification within an input/output device or component. Based on a target DMA engine within the device, and a protocol path for testing the DMA engine, sets of packet attributes are generated and used to format packets for input to the device. The output of the device is examined to determine if the correct DMA engine was used within the device. The DMA policy specifying which DMA engine to use for a particular packet configuration or set of protocol attributes can be dynamically replaced or modified without halting the validation process. | 07-02-2009 |
20090187679 | Universal DMA (Direct Memory Access) Architecture - A universal DMA (Direct Memory Access) engine can be dynamically configured to function in either a receive or transmit mode. DMAs are logically assembled and bound as needed, without limitation to a fixed, pre-determined number of receive engines and transmit engines. Because a DMA engine may be dynamically assembled to support the flow of data in either direction, varied usage models are enabled, and components used to assemble a receive DMA engine for one application may be subsequently used to assemble a transmit engine for a different application. An application may request a specific number of each type of engine, depending on the nature of its input/output traffic. The number of receive or transmit engines can be dynamically increased or decreased without suspending or rebooting the host. A universal DMA architecture provides a unified software framework, thereby decreasing the complexity of the software and the hardware gate count cost. | 07-23-2009 |
20100100717 | MECHANISM FOR PERFORMING FUNCTION LEVEL RESET IN AN I/O DEVICE - An I/O device having function level reset functionality includes a host interface that may include a master reset unit, a plurality of client interfaces, each corresponding to one or more functions, and a plurality of hardware resources. Each hardware resource may be associated with a respective function. In response to receiving a reset request to reset a specific function, the master reset unit may provide to each client interface, a request signal corresponding to the reset request, and a signal identifying the specific function. Each client interface having an association with the specific function may initiate a reset operation of the associated hardware resources, and also provide a client reset done signal for the specific function to the master reset unit in response to completion of the reset operations of the hardware resources. The master reset unit provides a reset done signal for the specific function to the host interface. | 04-22-2010 |
20100329253 | METHOD AND APPARATUS FOR PACKET CLASSIFICATION AND SPREADING IN A VIRTUALIZED SYSTEM - Some embodiments of the present invention provide a system for packet classification and spreading in a virtualized system. The system can use information in a packet's header to determine a destination system-image in the virtualized system, and a packet-spreading policy for the destination system-image. The system can determine a key using the information in a packet's header. Alternatively, the system can hash the information in the packet's header to obtain an index value. Next, the system can use the key or the index value to perform a lookup in a table which associates keys or index values with system images and/or packet-spreading policies. Once the destination system-image and the packet-spreading policy are determined, the system can deliver the packet to a thread on the destination system-image according to the packet-spreading policy. | 12-30-2010 |
20110055346 | DIRECT MEMORY ACCESS BUFFER MANAGEMENT - Disclosed are systems and methods for reclaiming posted buffers during a direct memory access (DMA) operation executed by an input/output device (I/O device) in connection with data transfer across a network. During the data transfer, the I/O device may cancel a buffer provided by a device driver thereby relinquishing ownership of the buffer. A condition for the I/O device relinquishing ownership of a buffer may be provided by a distance vector that may be associated with the buffer. The distance vector may specify a maximum allowable distance between the buffer and a buffer that is currently fetched by the I/O device. Alternatively, a condition for the I/O device relinquishing ownership of a buffer may be provided by a timer. The timer may specify a maximum time that the I/O device may maintain ownership of a particular buffer. In other implementations, a mechanism is provided to force the I/O device to relinquish some or all of the buffers that it controls. | 03-03-2011 |
20110078342 | System and Method for Direct Memory Access Using Offsets - A DMA device may include an offset determination unit configured to determine a first offset for a DMA transfer and a data transfer unit. The data transfer unit may be configured to receive a first buffer starting address identifying a starting location of a first buffer allocated in memory for the DMA transfer and to generate a first buffer offset address by applying the first offset to the first buffer starting address. The data transfer unit may be further configured to use the first buffer offset address as a starting location in the first buffer for data transferred in the DMA transfer. By applying various offsets, such DMA devices may spread memory access workload across multiple memory controllers, thereby achieving better workload balance and performance in the memory system. | 03-31-2011 |
20110134915 | APPARATUS AND METHOD FOR MANAGING PACKET CLASSIFICATION TABLES - Methods and apparatus are provided for managing classification of packets within a multi-function input/output device, and for allowing the device's classification tables to be cleared in a non-blocking manner. The input/output device conveys multiple communication connections corresponding to multiple physical and/or virtual PCIe (Peripheral Component Interconnect Express) functions bound to software images executing on hosts. The device comprises gate logic configured to indicate statuses of the functions or the DMA engines bound to the functions. When the gate logic indicates a particular destination function is valid, the packet is transferred normally after being classified. A portion of the logic corresponding to a given function is reprogrammed to indicate the function is invalid when that function is reinitialized (e.g., FLR or Function Level Reset). The function's entries in packet classification tables are cleared afterward. When the logic indicates a function is invalid, packets destined for that function are dropped. | 06-09-2011 |
20110191506 | VIRTUALIZATION OF AN INPUT/OUTPUT DEVICE FOR SUPPORTING MULTIPLE HOSTS AND FUNCTIONS - Methods and apparatus are provided for simultaneously supporting multiple hosts with a single communication port; each host may host multiple functions. The input/output device comprises multiple buffers; each buffer stores packets for one host, but can be dynamically reallocated to a different host. Multiple buffers may simultaneously support the same host and all of its functions. After a packet is received and classified, it is stored in at least one buffer, along with control information for processing the packet upon egress from the buffer. Egress managers for each buffer extract packets and transfer them to destination host/functions, by speculatively moving the packets forward even while DMA engines perform their processing to facilitate their transfer. | 08-04-2011 |
20110191518 | VIRTUALIZATION OF AN INPUT/OUTPUT DEVICE FOR SUPPORTING MULTIPLE HOSTS AND FUNCTIONS - Methods and apparatus are provided for simultaneously supporting multiple hosts with a single communication port; each host may host multiple functions. The input/output device comprises multiple buffers; each buffer stores packets for one host, but can be dynamically reallocated to a different host. Multiple buffers may simultaneously support the same host and all of its functions. After a packet is received and classified, it is distributed to buffer ingress managers. Within a set of ingress managers serving one buffer, each manager corresponds to one function of the buffer's corresponding host, and is programmed with criteria for identifying packets desired by that function. One copy of the packet is stored in a buffer if at least one of the buffer's ingress managers accepts it, along with control information for processing the packet upon egress from the buffer. Egress managers for each buffer extract packets and transfer them to destination host/functions. | 08-04-2011 |
20110289242 | MANAGING INTERRUPTS IN A VIRTUALIZED INPUT/OUTPUT DEVICE SUPPORTING MULTIPLE HOSTS AND FUNCTIONS - Methods and apparatus are provided for managing interrupts within a virtualizable communication device. Through virtualization, one port of the device may be able to support multiple hosts (e.g., computers) and multiple functions operating on each host. Any number of interrupt resources may be allocated to the supported functions, and may include receive/transmit DMAs, receive/transmit mailboxes, errors, and so on. Resources may migrate from one function to another, such as when a function requests additional resources. Each function's set of allocated resources is isolated from other functions' resources so that their interrupts may be managed and reported in a non-blocking manner. If an interrupt cannot be immediately reported to a destination host/function, the interrupt may be delayed, retried, cancelled or otherwise handled in a way that avoids blocking interrupts to other hosts and functions. | 11-24-2011 |
20120207039 | METHOD AND SYSTEM FOR VALIDATING NETWORK TRAFFIC CLASSIFICATION IN A BLADE SERVER - A system and method for validating network traffic routing within a blade chassis, involving generating a first packet for sending to a first packet receiver by a first route; inserting a first session identifier into a payload of the first packet, where the first session identifier identifies a first session of the first packet receiver; sending the first packet to a packet classifier; sending a first copy packet to a first expect queue, where the first copy packet is a duplicate of the first packet; receiving the first packet by the packet classifier; classifying the first packet by the packet classifier to obtain a first classified packet; extracting the first session identifier from the first classified packet to obtain a first extracted session identifier; and determining whether the first extracted session identifier matches the first session identifier. | 08-16-2012 |
20120207156 | METHOD AND SYSTEM FOR ROUTING NETWORK TRAFFIC FOR A BLADE SERVER - A system and method for routing network traffic for a blade server chassis, involving receiving a packet by a network express manager (NEM); obtaining the L2 address, the L3 address, and the L4 address from the packet; obtaining a first mapping that associates the L2 address with a network function; obtaining a second mapping that associates the network function with a configuration; generating a key based on the network function, the L3 address, and the L4 address; obtaining a third mapping that associates the key with a policy; making a determination to transmit the packet based on the policy; based on the determination, selecting a direct memory access (DMA) engine for transmitting the packet based on the configuration; and based on the determination, transmitting the packet to a blade using the DMA engine and the network function. | 08-16-2012 |
20120207158 | METHOD AND SYSTEM FOR CLASSIFICATION AND MANAGEMENT OF INTER-BLADE NETWORK TRAFFIC IN A BLADE SERVER - A system and method for classifying a multicast packet, involving receiving, at a classification engine, the multicast packet sent from a packet source; determining, based on a source address of the multicast packet, a Direct Memory Access (DMA) filter vector; determining, based on a destination address of the multicast packet, a DMA target vector, where the DMA target vector includes a listing of DMA channels which are available to transfer the multicast packet; determining a DMA final vector based on the DMA filter vector and the DMA target vector; and sending the multicast packet according to the DMA final vector. | 08-16-2012 |
20140269311 | PARALLELIZING PACKET CLASSIFICATION AND PROCESSING ENGINES - An apparatus that recursively classifies packets includes a hierarchical set of classification engines that perform parallel classification of the packets in a packet processing queue. In particular, a first classification engine separates the packets based on physical-layer information and/or link-layer information in the packets. Then, second classification engines further separate the packets into multiple parallel pipelines based on layer information in the packets that is other than the physical-layer information and the link-layer information. The first classification engine and the second classification engines maintain a relative ordering of the packets in network sub-flows while allowing changes in relative ordering among different network flows. | 09-18-2014 |
20140269686 | VIRTUAL ROUTER AND SWITCH - An input/output (I/O) switch fabric includes input physical ports that convey packets associated with at least a first network flow. Moreover, virtual routers in the I/O switch fabric, which have associated routing tables, provide types of service and/or routes for different source-destination pairs based on link-layer information and network-layer information in the packets. Note that different virtual routers can provide different types of service and/or different routes. For example, a type of service associated with a first virtual router may include changing packet headers when crossing service domains in a global network, and a type of service associated with a second virtual router may avoid changing packet headers when providing connectivity in the network. Furthermore, the I/O switch fabric includes output physical ports that convey packets associated with at least a second network flow. The virtual routers may facilitate InfiniBand inter-subnet crossing. | 09-18-2014 |
20140269720 | SCALABLE INFINIBAND PACKET-ROUTING TECHNIQUE - An InfiniBand switch fabric is described. This InfiniBand switch fabric includes a hierarchy of switches having physical ports. These physical ports have associated local routing tables for nearest-neighbor connections to the physical ports. Moreover, relationships between the nearest-neighbor connections to each of the physical ports specified in the local routing tables are based in part on network-layer global identifiers that are assigned based on the hierarchy. Furthermore, local routing tables in the switches facilitate paths or routes for packets through the InfiniBand switch fabric without using a global routing table in the switches. In addition, the InfiniBand switch fabric includes a fabric manager, coupled to the switches, having the global routing table to assign the network-layer global identifiers. | 09-18-2014 |
20140269743 | VIRTUAL-PORT NETWORK SWITCH FABRIC - An input/output (I/O) switch fabric includes first physical ports that convey multiple network flows. Moreover, classifiers in the I/O switch fabric separate packets for network flows associated with different types of service. Then, the I/O switch fabric conveys the packets to different virtual switch ports without interference between the separated packets associated with different network flows. Furthermore, second physical ports in the I/O switch fabric output the packets, where a given second physical port outputs packets for at least some of the network flows associated with different types of service. In this way, the given second physical port can output packets having: the same source and destination; different sources and the same destination; or the same source and different destinations. | 09-18-2014 |