Patent application number | Description | Published |
20080301402 | Method and System for Stealing Interrupt Vectors - A system for stealing interrupt vectors from an operating system. Custom interrupt handler extensions are copied into an allocated block of memory from a kernel module. Also, operating system interrupt handlers are copied into a reserved space in the allocated block of memory from an interrupt vector memory location. In response to copying the operating system interrupt handlers into the reserved space in the allocated block of memory, custom interrupt handlers from the kernel module are copied over the operating system interrupt handlers in the interrupt vector memory location. The custom interrupt handlers after being copied into the interrupt vector memory location handle all interrupts received by the operating system. | 12-04-2008 |
20090024873 | System and Method for Increasing Error Checking Performance by Calculating CRC Calculations After Multiple Test Patterns for Processor Design Verification and Validation - A system and method to reduce verification time by sharing memory between multiple test patterns and performing results checking after each test pattern executes one time is presented. A test pattern generator generates multiple test pattern sets, each of which including multiple test patterns. Each test pattern set is executed by a corresponding thread/processor until each test pattern included in the test pattern set has executed at least once. After all test patterns have executed at least once, a test pattern executor performs a memory error detection check to determine whether the system is functioning correctly. Since the invention described herein waits until all test patterns have executed before performing a memory error detection check, less time is spent on memory error detection checks, which allows more time to execute test patterns. | 01-22-2009 |
20090024876 | System and Method for Verification of Cache Snoop Logic and Coherency Between Instruction & Data Caches for Processor Design Verification and Validation - A system and method for verifying cache snoop logic and coherency between instruction cache and data cache using instruction stream “holes” that are created by branch instructions is presented. A test pattern generator includes instructions that load/store data into instruction stream holes. In turn, by executing the test pattern, a processor thread loads an L2 cache line into both instruction cache (icache) and data cache (dcache). The test pattern modifies the data in the dcache in response to a store instruction. In turn, the invention described herein identifies whether snoop logic detects the change and updates the icache's corresponding cache line accordingly. | 01-22-2009 |
20090024877 | System and Method for Creating Different Start Cache and Bus States Using Multiple Test Patterns for Processor Design Verification and Validation - A system and method for creating different start cache and bus states using multiple test patterns for processor design verification and validation is presented. A test pattern generator/tester re-uses test patterns in different configurations that alter cache states and translation lookaside buffer (TLB) states, which produces different timing scenarios on a broadband bus. The test pattern generator/tester creates multiple test patterns for a multi-processor system and executes the test patterns repeatedly in different configurations without rebuilding the test patterns. This enables a system to dedicate more time executing the test patterns instead of building the test patterns. By repeatedly executing the same test patterns in a different configuration, the invention described herein produces different start cache states, different TLB states, along with other processor units, each time the test patterns execute that, in turn, changes the bus timing. | 01-22-2009 |
20090024886 | System and Method for Predicting lwarx and stwcx Instructions in Test Pattern Generation and Simulation for Processor Design Verification and Validation - A system and method for predicting lwarx (Load Word And Reserve Index form) and stwcx (Store Word Conditional) instruction outcome is presented. A lwarx instruction establishes a reservation on an address/granule, and a stwcx instruction targeted to the same address/granule “succeeds” only if the reservation for the granule still exists (conditional store). Since the reservation may be lost due to situations such as, for example, a processor (or another processor) executing a different lwarx or ldarx instruction (or other mechanism), which clears the first reservation and establishes a new reservation, the invention described herein builds test patterns in a manner that ensures, stwcx success and failure predictability. As a result, stwcx instructions are testable during test pattern execution. | 01-22-2009 |
20090024891 | System and Method for Pseudo-Random Test Pattern Memory Allocation for Processor Design Verification and Validation - A system and method for pseudo-randomly allocating page table memory for test pattern instructions to produce complex test scenarios during processor execution is presented. The invention described herein distributes page table memory across processors and across multiple test patterns, such as when a processor executes “n” test patterns. In addition, the page table memory is allocated using a “true” sharing mode or a “false” sharing mode. The false sharing mode provides flexibility of performing error detection checks on the test pattern results. In addition, since a processor comprises sub units such as a cache, a TLB (translation look aside buffer), an SLB (segment look aside buffer), an MMU (memory management unit), and data/instruction pre-fetch engines, the test patterns effectively use the page table memory to test each of the sub units. | 01-22-2009 |
20090024892 | System and Method of Testing using Test Pattern Re-Execution in Varying Timing Scenarios for Processor Design Verification and Validation - A system and method processor testing using test pattern re-execution is presented. A processor re-executes test patterns using different timing scenarios in order to reduce test pattern build time and increase system test coverage. The invention described herein varies initial states of a processor's memory (cache, TLB, SLB, etc.) that, in turn, varies the timing scenarios when re-executing test patterns. By re-executing the test patterns instead of rebuilding new test patterns, verification quality is improved since more time is available for execution, verification and validation. In addition, since the test patterns result in the same final state, the invention described herein also simplifies error checking. | 01-22-2009 |
20090024894 | SYSTEM AND METHOD FOR PREDICTING IWARX AND STWCX INSTRUCTIONS IN TEST PATTERN GENERATION AND SIMULATION FOR PROCESSOR DESIGN VERIFICATION/VALIDATION IN INTERRUPT MODE - During a test pattern build, a test pattern generator pseudo-randomly selects an address for a selected lwarx instruction and builds the lwarx instruction using the pseudo-random address into a test pattern. Subsequently, the test pattern generator builds a store instruction after the lwarx instruction using the pseudo-random address. The store instruction is adapted to store the pseudo-random address in a predetermined memory location. The test pattern generator also builds an interrupt service routine that services an interrupt associated with the interrupt request; checks the predetermined memory location; determines that the pseudo-random address is located in the predetermined memory location; and executes a subsequent lwarx instruction using the pseudo-random address. | 01-22-2009 |
20090070532 | System and Method for Efficiently Testing Cache Congruence Classes During Processor Design Verification and Validation - A system and method for using a single test case to test each sector within multiple congruence classes is presented. A test case generator builds a test case for accessing each sector within a congruence class. Since a congruence class spans multiple congruence pages, the test case generator builds the test case over multiple congruence pages in order for the test case to test the entire congruence class. During design verification and validation, a test case executor modifies a congruence class identifier (e.g., patches a base register), which forces the test case to test a specific congruence class. By incrementing the congruence class identifier after each execution of the test case, the test case executor is able to test each congruence class in the cache using a single test case. | 03-12-2009 |
20090070546 | System and Method for Generating Fast Instruction and Data Interrupts for Processor Design Verification and Validation - A system and method for intentionally invaliding translation entry valid bits in order to provoke storage interrupts when executing a test case is presented. Prior to executing the test case, an interrupt handler pseudo-randomly invalidates a number of translation entries included in a translation lookaside buffer (TLB) by changing particular valid bits in order to provoke initial storage interrupts, such as an instruction storage interrupt (ISI) or a data storage interrupt (DSI). Once the processor executes the test case that, in turn, triggers a storage interrupt, the interrupt handler uses an index counter to validate particular valid bits and invalidate other valid bits, thus provoking subsequent storage interrupts. In one embodiment, the interrupt handler also changes valid bits in a page table when the processor executes in a mode that accesses the page table in addition to the TLB. | 03-12-2009 |
20090070570 | System and Method for Efficiently Handling Interrupts - A system and method for including independent instructions into a test case for intentionally provoking interrupts that may be used in conjunction with an instruction shuffling process is presented. A test case generator builds a test case that includes intentional interrupt instructions, which are constructed to intentionally provoke an interrupt, such as an instruction storage interrupt (ISI), a data storage interrupt (DSI), and alignment interrupt, and/or a program interrupt (PI). When a processor executes the test case and invokes an interrupt to an interrupt handler, the interrupt handler does not resolve the interrupt, but rather increments an instruction address register or a link register and resumes test case execution at an instruction subsequent to the instruction that caused the interrupt. | 03-12-2009 |
20090070629 | System and Method for Testing Multiple Processor Modes for Processor Design Verification and Validation - A system and method for generating a test case and a bit mask that allows a test case executor the ability to re-execute the test case multiple times using different machine state register bit sets. A test case generator creates a bit mask based upon identified invariant bits and semi-invariant bits. The test case generator includes compensation values corresponding to the semi-invariant bits into a test case, and provides the test case, along with the bit mask, to a test case executor. In turn, the test case executor dispatches the test case multiple times, each time with a different machine state register bit set, to a processor. Each of the machine state register bit sets places the processor in different modes. | 03-12-2009 |
20090070631 | System and Method for Re-Shuffling Test Case Instruction Orders for Processor Design Verification and Validation - A system and method for creating multiple test case scenarios from one test case by shuffling the test case instruction order while maintaining relative sub test case instruction order intact is presented. A test case generator generates and provides a test case that includes multiple sub test cases to a test case executor. In turn, the test case executor recursively schedules and dispatches the test case with different shuffled instruction orders to a processor in order to efficiently test the processor. In one embodiment, the test case generator provides multiple test cases to the test case executor. In another embodiment, the test case generator provides test cases to multiple test case executors that, in turn, shuffle the test cases and provide the shuffled test cases to their respective processor. | 03-12-2009 |
20090070632 | System and Method for Testing SLB and TLB Cells During Processor Design Verification and Validation - A system and method for re-executing a test case and modifying the test case's effective addresses, effective segment identifiers (ESIDs), and virtual segment identifiers (VSIDs) in order to fully test a processor's SLB and TLB cells is presented. A test case generator generates a test case that includes an initial set of test case effective addresses, an initial set of ESIDs, and an initial set of VSIDs. The test case executor uses an effective address arithmetic function and a virtual address arithmetic function to modify the test case effective addresses, the ESIDs, and the VSIDs on each re-execution that, in turn, sets/unsets each bit within each SLB and TLB entry. In one embodiment, the invention described herein sequentially shifts segment lookaside buffer entries, whose ESIDs are in single bit increments, in order to fully test each ESID bit location within each SLB entry. | 03-12-2009 |
20090070643 | System and Method for Testing a Large Memory Area During Processor Design Verification and Validation - A system and method for replicating a memory block throughout a main memory and modifying real addresses within an address translation buffer to reference the replicated memory blocks during test case set re-executions in order to fully test the main memory is presented. A test case generator generates a test case set (multiple test cases) along with an initial address translation buffer that includes real addresses that reference an initial memory block. A test case executor modifies the real addresses after each test case set re-execution in order for a processor to test each replicated memory block included in the main memory. | 03-12-2009 |
20090070768 | System and Method for Using Resource Pools and Instruction Pools for Processor Design Verification and Validation - A system and method for using resource pools and instruction pools for processor design verification and validation is presented. A test case generator organizes processor resources into resource pools using a resource pool mask. Next, the test case generator separates instructions into instruction pools based upon the resources that each instruction requires. The test case generator then creates a test case using one or more sub test cases by assigning a resource pool to each sub test case, identifying instruction pools that correspond the assigned test case, and building each sub test case using instructions included in the identified instruction pools. | 03-12-2009 |
20090144736 | Performance Evaluation of Algorithmic Tasks and Dynamic Parameterization on Multi-Core Processing Systems - A method for evaluating performance of DMA-based algorithmic tasks on a target multi-core processing system includes the steps of: inputting a template for a specified task, the template including DMA-related parameters specifying DMA operations and computational operations to be performed; evaluating performance for the specified task by running a benchmark on the target multi-core processing system, the benchmark being operative to generate data access patterns using DMA operations and invoking prescribed computation routines as specified by the input template; and providing results of the benchmark indicative of a measure of performance of the specified task corresponding to the target multi-core processing system. | 06-04-2009 |
20090144738 | Performance Evaluation of Algorithmic Tasks and Dynamic Parameterization on Multi-Core Processing Systems - Apparatus for evaluating the performance of DMA-based algorithmic tasks on a target multi-core processing system includes a memory and at least one processor coupled to the memory. The processor is operative: to input a template for a specified task, the template including DMA-related parameters specifying DMA operations and computational operations to be performed; to evaluate performance for the specified task by running a benchmark on the target multi-core processing system, the benchmark being operative to generate data access patterns using DMA operations and invoking prescribed computation routines as specified by the input template; and to provide results of the benchmark indicative of a measure of performance of the specified task corresponding to the target multi-core processing system. | 06-04-2009 |
20090144744 | Performance Evaluation of Algorithmic Tasks and Dynamic Parameterization on Multi-Core Processing Systems - A method for evaluating performance of DMA-based algorithmic tasks on a target multi-core processing system includes the steps of: inputting a template for a specified task, the template including DMA-related parameters specifying DMA operations and computational operations to be performed; evaluating performance for the specified task by running a benchmark on the target multi-core processing system, the benchmark being operative to generate data access patterns using DMA operations and invoking prescribed computation routines as specified by the input template; and providing results of the benchmark indicative of a measure of performance of the specified task corresponding to the target multi-core processing system. | 06-04-2009 |
20090144745 | Performance Evaluation of Algorithmic Tasks and Dynamic Parameterization on Multi-Core Processing Systems - Apparatus for evaluating the performance of DMA-based algorithmic tasks on a target multi-core processing system includes a memory and at least one processor coupled to the memory. The processor is operative: to input a template for a specified task, the template including DMA-related parameters specifying DMA operations and computational operations to be performed; to evaluate performance for the specified task by running a benchmark on the target multi-core processing system, the benchmark being operative to generate data access patterns using DMA operations and invoking prescribed computation routines as specified by the input template; and to provide results of the benchmark indicative of a measure of performance of the specified task corresponding to the target multi-core processing system. | 06-04-2009 |
20090307468 | Generating a Test Case Micro Generator During Processor Design Verification and Validation - A main generator generates a micro generator and initial test cases based upon a processor architecture specifications and user input, such as general purpose register availability, translation information, instruction sequences, base register available, target real memory pages, etc. In turn, the micro generator tests a processor using the initial test cases and subsequent test cases generated by the micro generator. The subsequent test cases may include modified test case properties such as changed machine state register bits, changed instruction sequence (shuffling), changed effective segment ID bits, and/or changed virtual segment ID bits. In addition to generating subsequent test cases, the micro generator performs functions such as test case dispatching, test case scheduling, test case execution, and interrupt handling. | 12-10-2009 |
20100011248 | LIGHT WEIGHT AND HIGH THROUGHPUT TEST CASE GENERATION METHODOLOGY FOR TESTING CACHE/TLB INTERVENTION AND DIAGNOSTICS - A test case manager selects a first test case and a second test case from a plurality of test cases. The test case manager provides the first test case to a first processor and provides the second test case to a second processor. As such, the first processor executes the first test case and the second processor executes the second test case. After the execution, the test case manager loads the first test case onto the second processor and loads the second test case onto the first processor. In turn, the first processor executes the second test case and the second processor executes the first test case. | 01-14-2010 |
20100023697 | Testing Real Page Number Bits in a Cache Directory - Testing real page number bits in a cache directory is provided. A specification of a cache to be tested is retrieved in order to test the real page number bits of the cache directory associated with the cache. A range within a real page number address of the cache directory is identified for performing page allocations using the specification of the cache. A random value x is generated that identifies a portion of the real page number bits to be tested. A first random value y is generated that identifies a first congruence class from a set of congruence classes within the portion of the cache to be tested. Responsive to the first congruence class failing to be allocated a predetermined number of times, one page size of memory for the first congruence class is allocated and a first allocation value is incremented by a value of 1. | 01-28-2010 |
20140032966 | Hardware verification using ACCELERATION platform - A method, apparatus and product for hardware verification using acceleration platform. The method comprising executing a first post-silicon testing program by a reference model, wherein during said executing the first post-silicon testing program one or more test-cases are generated; generating a second post-silicon testing program that is configured to execute the one or more test-cases; and executing the second post-silicon testing program on an acceleration platform. | 01-30-2014 |
20140236561 | EFFICIENT VALIDATION OF COHERENCY BETWEEN PROCESSOR CORES AND ACCELERATORS IN COMPUTER SYSTEMS - A method of testing cache coherency in a computer system design allocates different portions of a single cache line for use by accelerators and processors. The different portions of the cache line can have different sizes, and the processors and accelerators can operate in the simulation at different frequencies. The verification system can control execution of the instructions to invoke different modes of the coherency mechanism such as direct memory access or cache intervention. The invention provides a further opportunity to test any accelerator having an original function and an inverse function by allocating cache lines to generate an original function output, allocating cache lines to generate an inverse function output based on the original function output, and verifying correctness of the original and inverse functions by comparing the inverse function output to the original function input. | 08-21-2014 |
20140237194 | EFFICIENT VALIDATION OF COHERENCY BETWEEN PROCESSOR CORES AND ACCELERATORS IN COMPUTER SYSTEMS - A method of testing cache coherency in a computer system design allocates different portions of a single cache line for use by accelerators and processors. The different portions of the cache line can have different sizes, and the processors and accelerators can operate in the simulation at different frequencies. The verification system can control execution of the instructions to invoke different modes of the coherency mechanism such as direct memory access or cache intervention. The invention provides a further opportunity to test any accelerator having an original function and an inverse function by allocating cache lines to generate an original function output, allocating cache lines to generate an inverse function output based on the original function output, and verifying correctness of the original and inverse functions by comparing the inverse function output to the original function input. | 08-21-2014 |