Patent application number | Description | Published |
20120299622 | Internal Clock Gating Apparatus - An internal clock gating apparatus comprises a static logic block and a domino logic block. The static logic block is configured to receive a clock signal and a clock enable signal. The domino logic block is configured to receive the clock signal and a control signal from an output of the static logic block. The static logic block and the domino logic block are further configured such that an output of the domino logic block generates a signal similar to the clock signal in phase when the clock enable signal has a logic high state. On the other hand, the output of the domino logic block generates a logic low signal when the clock enable signal has a logic low state. Furthermore, the static logic block and the domino logic block can reduce the setup time and delay time of the internal clock gating apparatus respectively. | 11-29-2012 |
20150121030 | HIGH DENSITY MEMORY STRUCTURE - A semiconductor memory comprises a plurality of sub banks each including one or more rows of memory bit cells connected to a set of local bit lines, wherein the sub banks share a same set of global bit lines for reading/writing data from/to the memory bit cells of the sub banks. The semiconductor memory chip further comprises a plurality of switch elements for each of the sub banks, wherein each of the switch elements connects the local bit line and the global bit line of a corresponding one of the memory bit cells in the sub bank for data transmission between the local bit line and the global bit line. The semiconductor memory chip further comprises a plurality of bank selection signal lines each connected to the switch elements in a corresponding one of the sub banks, wherein the bank selection signal lines carry a plurality of bank selection signals to select one of the sub banks for data transmission between the local bit lines and the global bit lines. | 04-30-2015 |
20150131364 | NEGATIVE BITLINE BOOST SCHEME FOR SRAM WRITE-ASSIST - A device includes a transistor switch coupled between a bit line voltage node and a ground node and a boost signal circuit coupled to a gate node of the transistor switch, where the boost signal circuit providing a boost signal responsive to a write enable signal. The device also includes a first delay element and a first capacitor in series with the first delay element. The first capacitor has a first end coupled to the bit line voltage node and a second end coupled to the gate node through the first delay element. | 05-14-2015 |
20150262655 | NEGATIVE BITLINE BOOST SCHEME FOR SRAM WRITE-ASSIST - A device includes a transistor switch coupled between a bit line voltage node and a ground node and a boost signal circuit coupled to a gate node of the transistor switch, where the boost signal circuit providing a boost signal responsive to a write enable signal. The device also includes a first delay element and a first capacitor in series with the first delay element. The first capacitor has a first end coupled to the bit line voltage node and a second end coupled to the gate node through the first delay element. | 09-17-2015 |
Patent application number | Description | Published |
20090244556 | Technical Documents Capturing And Patents Analysis System And Method - Disclosed is a system and method for capturing technical documents and reading and commentating captured documents thereof. The system may comprise a capturing system and a reading with commentating system. The capturing system selects related drawings from a group of technical documents. It then provides important information and the related drawings onto an image for the readers' review. The reading with commentating system allows the readers to process technical classification, management and export/import for the group of technical documents. Readers may make comments on an information sharing platform after reviewing the technical documents. Besides, other materials collected or generated from the technical analysis on the technical documents may be attached to the information sharing platform. | 10-01-2009 |
20100049769 | System And Method For Monitoring And Managing Patent Events - Disclosed relates to a system and a method for monitoring and managing patent events. The system comprises a patent event selection unit and a monitoring and managing patent unit. The patent event selection unit verifies any combination of the time, prosecution status, qualification and contents of a patent event according to the inputted information related to the patent event. The unit also monitors and analyzes the patent event. The monitoring and managing patent unit sets up alert and/or warning activated, generates corresponding responses or provides related comments or actions. | 02-25-2010 |
20130120809 | Technical Documents Capturing And Patents Analysis System And Method - Disclosed is a system and method for capturing technical documents and reading and commentating captured documents thereof. The system may comprise a capturing system and a reading with commentating system. The capturing system selects related drawings from a group of technical documents. It then provides important information and the related drawings onto an image for the readers' review. The reading with commentating system allows the readers to process technical classification, management and export/import for the group of technical documents. Readers may make comments on an information sharing platform after reviewing the technical documents. Besides, other materials collected or generated from the technical analysis on the technical documents may be attached to the information sharing platform. | 05-16-2013 |
Patent application number | Description | Published |
20080300066 | GOLF CLUB HEAD - A golf club head includes a head body and a striking plate. The head body has a front open end, and a limiting rib projecting inwardly from an inner wall face of the head body and proximate to the front open end. The limiting rib has two opposite first rib sections, and two opposite second rib sections interconnecting the first rib sections. Each second rib section has a thickness smaller than that of each first rib section. The striking plate covers the front open end, and abuts against front sides of the first and second rib sections. The striking plate has a sweet spot closer to the first rib sections than the second rib sections. | 12-04-2008 |
20080305887 | GOLF CLUB HEAD FOR AN IRON - A golf club head for an iron includes a back part, a striking plate covering the back part, and a fixing unit to join the striking plate and the back part. The fixing unit has a looped groove provided between the striking plate and the back part, and a welding material interconnecting the striking plate and the back part and filled in the looped groove. | 12-11-2008 |
20090288282 | Method of Making a Golf Club Head - A method of making a golf club head includes the steps of: preparing a head body formed with at least one cavity, and at least one flange protruding from the head body and proximate to the cavity; mounting a counterweight unit in the cavity; bending the flange toward the cavity and pressing the flange against the counterweight unit; joining the counterweight unit to the head body using a solder; and polishing the head body and the counterweight unit to remove excess of the flange and the solder. | 11-26-2009 |
20090288285 | METHOD OF MAKING A GOLF CLUB HEAD - A method of making a golf club head includes the steps of: preparing a head body including a front engaging face, a back face, an opening extending through the front engaging face and the back face, a groove extending around the opening and recessed inwardly from the front engaging face, a peripheral edge surrounding the groove, and at least one flange extending along the peripheral edge and protruding away from the front engaging face; mounting a striking plate on the front engaging face to cover the opening; bending the flange toward the striking plate and pressing the flange against the striking plate; joining the striking plate to the head body using a solder; and polishing the head body and the striking plate to remove excess of the flange and the solder. | 11-26-2009 |
Patent application number | Description | Published |
20120113070 | GATE DRIVER CIRCUIT AND ARRANGEMENT METHOD OF THE SAME - An arrangement method, applied to a plurality of gate driver modules coupled in series and arranged on two sides of a panel, includes steps of: placing a first gate driver module on a first side of the panel; placing a gate driver set on a second side of the panel; and placing a fourth gate driver module on the first side of the panel. The gate driver set includes a second gate driver module and a third gate driver module serially connected. The output terminal of the first gate driver module is electrically coupled to the second gate driver module and the output terminal of the third gate driver module is electrically coupled to the fourth gate driver module. A gate driver circuit and an arrangement method applied to a plurality of shift register sets coupled in series and arranged on two sides of a panel are also disclosed. | 05-10-2012 |
20120133392 | MULTIPLEX GATE DRIVING CIRCUIT - A multiplex gate driving circuit includes plural driving modules. In comparison with the prior art, each driving stage of the driving module has less number of transistors. From the first to the seventh example, each driving stage is implemented by only four transistors. In the eighth example and the ninth example, each driving stage is implemented by only two transistors. In other words, the driving stage of the multiplex gate driving circuit has less number of transistors, thereby reducing the layout area of the invisible zone of the LCD panel. | 05-31-2012 |
20120139599 | MULTIPLEX DRIVING CIRCUIT - A multiplex driving circuit receives m master signals and n slave signals, and includes m driving modules for generating m×n gate driving signals. Each driving module includes a voltage boost stage and n driving stages. The voltage boost stage is used for receiving a first master signal of the m master signals and converting the first master signal into a first high voltage signal, wherein a high logic level of the first master signal is increased to a highest voltage by the voltage boost stage. The n driving stages receives the n slave signals, respectively, and receives the first high voltage signal. In response to the highest voltage of the first high voltage signal, the n driving stages sequentially generates n gate driving signals according to the n slave signals. | 06-07-2012 |
20140159799 | MULTIPLEX DRIVING CIRCUIT - A multiplex driving circuit receives m master signals and n slave signals, and includes m driving modules for generating m×n gate driving signals. Each driving module includes a voltage boost stage and n driving stages. The voltage boost stage is used for receiving a first master signal of the m master signals and converting the first master signal into a first high voltage signal, wherein a high logic level of the first master signal is increased to a highest voltage by the voltage boost stage. The n driving stages receives the n slave signals, respectively, and receives the first high voltage signal. In response to the highest voltage of the first high voltage signal, the n driving stages sequentially generates n gate driving signals according to the n slave signals. | 06-12-2014 |