Patent application number | Description | Published |
20080205146 | Nonvolatile RAM - A nonvolatile RAM for reading and writing data in a random manner includes a memory area configured by a plurality of memory cells suited to a nonvolatile-mode write operation, in which the stored content thereof is not lost irrespective of a power-off event, and a volatile-mode write operation, in which the stored content thereof is lost in the power-off event. A register designates a first portion of the memory area adapted to the nonvolatile-mode write operation regarding fixed data such as program codes and a second portion of the memory area serving as a work area adapted to the volatile-mode write operation. A control circuit performs the nonvolatile-mode write operation on the first portion of the memory area while performing the volatile-mode write operation on the second portion of the memory area. | 08-28-2008 |
20080209117 | Nonvolatile RAM - A nonvolatile RAM allows a read/write operation to be performed in a random manner with respect to a memory area, which is divided into a plurality of memory arrays each including a plurality of memory cells. Upon detection of an initialization signal, initialization is performed on at least one memory array, which is selected in advance. In addition, a disconnection control signal occurs so as to disconnect an access by an external device during a prescribed period for performing the initialization. The nonvolatile RAM is capable of protecting data from being irregularly read, modified, and reloaded with respect to at least one memory array, which is selected in advance, even when the nonvolatile RAM is frequently accessed by a prescribed application. | 08-28-2008 |
20080232155 | MOLECULAR BATTERY MEMORY DEVICE AND DATA PROCESSING SYSTEM USING THE SAME - Each memory cell of a molecular battery memory device includes a combination of a molecular battery and a selection transistor, and a parasitic capacitance is present in the molecular battery. A PN junction is present in the selection transistor, and is inversely biased. Therefore, a junction leak current flows. Accordingly, a charge accumulated in the parasitic capacitance is gradually discharged by a junction leak of the selection transistor, and a final potential of a node decreases toward a substrate potential Vs of the transistor. However, a difference between a substrate potential Vs and a reference potential Vp (=Vs−Vp) is set substantially equal to an open-circuit voltage of the molecular battery. Because the potential of the node converges to the open-circuit voltage without exception from the viewpoint of a plate wiring, an S/N ratio at the data reading time can be increased. | 09-25-2008 |
20080253159 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises word lines, global bit lines intersecting with the word lines; local bit lines partitioned into N sections along the global bit lines and aligned with a same pitch as the global bit lines; N memory cell arrays each including memory cells formed at intersections of the word lines and the local bit lines and being arranged corresponding to the sections of the local bit lines; local sense amplifiers for amplifying a signal read out from a selected memory cell to the local bit line and for outputting the signal to the global bit line; global sense amplifiers for amplifying the signal transmitted from the local sense amplifier corresponding to the selected memory cell through the global bit line and for selectively coupling the signal to an external data line. | 10-16-2008 |
20080259707 | Semiconductor storage device - A semiconductor storage device for storing data to unit blocks of a memory cell array, comprising: two rows of sense amplifiers arranged on both sides of bit lines and each including sense amplifiers; a switch means for switching a connecting state between one row of sense amplifiers and one side of bit lines and switching a connecting state between the other row of sense amplifiers and the other side of bit lines; a control means which sets at least one row of sense amplifiers as a cache memory, and when performing refresh operation of the unit block where row of sense amplifiers to be used as cache memory holds data, controls switch means so that the row of sense amplifiers used as cache memory is disconnected from bit lines and only the row of sense amplifiers not used as said cache memory is used in refresh operation. | 10-23-2008 |
20080276049 | Semiconductor memory apparatus, memory access control system and data reading method - In order to provide a semiconductor memory apparatus which can flexibly change the priority of reading requests when the reading request is issued and which do not exclusively use the memory bus, a semiconductor memory apparatus includes: a main memory which stores data at an address while maintaining a corresponding relationship between the data and the address; a read request input portion receiving a read request which maintains a corresponding relationship between address information that is referred to when reading the data and priority information that indicates priority for reading the data; a read data storing portion which stores the data and priority while maintaining a corresponding relationship thereof; a data reading portion reads the data corresponding to address information which is input by the read request input portion from the main memory; a read data registration portion storing both the priority information input by the read request input and the data read by the data reading portion to the read data storing portion while maintaining a corresponding relationship between the priority information and the data read; and a priority operation control portion which chooses and outputs the data with a highest priority among the priority information and the data that are stored in the read data storing portion while maintaining a corresponding relationship between the priority information and the data. | 11-06-2008 |
20080278991 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises. word lines; global bit lines intersecting with the word lines; local bit lines partitioned into N (N is an integer greater than or equal to two) sections along the global bit lines and aligned with a same pitch as the global bit lines; N memory cell arrays each including memory cells each having cylindrical capacitor structure formed at intersections of the word lines and the local bit lines and being arranged corresponding to the sections of the local bit lines; local sense amplifiers for amplifying a signal read out from a selected memory cell to the local bit line and for outputting the signal to the global bit line; and global sense amplifiers for coupling the signal transmitted from the local sense amplifier corresponding to the selected memory cell through the global bit line to an external data line. | 11-13-2008 |
20080280415 | Method of manufacturing semiconductor memory device - A method of manufacturing a semiconductor memory device of the present invention consists of a step of forming a selection transistor and a separate selection transistor and a step of forming a variable resistance element and a capacitance element, characterized by forming the variable resistance element by sequentially laminating a first electrode that is connected to the selection transistor, a variable resistance layer, and a second electrode; forming the capacitance element by sequentially laminating a third electrode that is connected to the separate selection transistor, a dielectric layer, and a fourth electrode; forming the dielectric layer and the variable resistance layer with a mutually identical material; forming either one of the first electrode or the second electrode with the same material as the third electrode and the fourth electrode; and forming the other one of the first electrode or the second electrode with a different material than the third electrode and the fourth electrode. | 11-13-2008 |
20080291762 | SEMICONDUCTOR MEMORY DEVICE FOR PRECHARGING BIT LINES EXCEPT FOR SPECIFIC READING AND WRITING PERIODS - A semiconductor memory device includes a memory cell having an FET of a floating body type, and a capacitor for storing a data charge; a bit line to which the source or the drain of the FET is connected; a precharging device for performing precharge control so that the bit line has a predetermined precharge voltage; a sense amplifier for amplifying and storing the potential of the bit line, which is set in accordance with the data charge read from the memory cell; a switching device, provided between the bit line and the sense amplifier, for performing selective connection therebetween; and a control part for controlling the precharging device, the sense amplifier, and the switching device. Except for each period for performing data reading or writing, the control part makes the precharging device perform the precharge control and makes the switching device disconnect the bit line from the sense amplifier. | 11-27-2008 |
20080291764 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises: word lines; global bit lines intersecting therewith; local bit lines partitioned into N sections along the global bit lines and aligned with a same pitch as the global bit lines; N memory cell arrays each of which includes memory cells each having a vertical transistor structure connected to the local bit lines at a lower portion and each being formed at an intersection of the word line and the local bit line, and is arranged corresponding to each section of the local bit lines; local sense amplifiers for amplifying a signal read out from a selected memory cell to the local bit line and for outputting the signal to the global bit line; and global sense amplifiers for coupling the signal transmitted from the local sense amplifier corresponding to the selected memory cell through the global bit line to an external data line. | 11-27-2008 |
20080316839 | MEMORY CELL ARRAY AND METHOD OF CONTROLLING THE SAME - To increase the quantity of stored charges of memory cells by a simple configuration to improve the operating margin, and to allow dummy cells to be unnecessary to improve the operating margin of a DRAM without increasing the power consumption and/or the chip area. A voltage of a common plate line is changed from a first voltage to a second voltage lower than the first voltage while a word line is a third voltage which makes the word line a selected state. The voltage of the word line is changed into a fourth voltage which makes the memory cell a non-selected state and is lower than the third voltage and higher than a fifth voltage which makes the word line a non-selected state, and the voltage of the plate line is changed into the first voltage after the voltage of the word line has been changed into the fourth voltage. | 12-25-2008 |
20090003041 | Semiconductor memory device and read method thereof - A semiconductor memory device comprises a plurality of memory cells each capable of storing at least three different states; a first sense amplifier for amplifying a ternary potential read out in accordance with a state stored in a selected memory cell based on a comparison with a first reference potential; and a second sense amplifier for amplifying a ternary potential read out in accordance with a state stored in the selected memory cell based on a comparison with a second reference potential. In the semiconductor memory device, the ternary potential comprises a high potential, a medium potential and a low potential, the first reference potential is set between the low potential and the medium potential, and the second reference potential is set between the high potential and the medium potential. | 01-01-2009 |
20090059644 | Semiconductor memory device having vertical transistors - A semiconductor memory device includes a memory cell array region in which vertical transistors each having a lower electrode connected to a bit line is regularly arranged with a predetermined pitch, including memory cells formed using at least the vertical transistors; a peripheral circuit region arranged adjacent to the memory cell array region in a bit line extending direction; and a predetermined circuit arranged overlapping the peripheral circuit region and the memory cell array region. In the semiconductor memory device, the vertical transistors each having an upper electrode connected to the predetermined circuit are included in an end region of the memory cell array region, in which no word line is provided. | 03-05-2009 |
20090100220 | Memory system, control method thereof and computer system - A memory system includes a memory cell array for storing data; and a register unit including one or more registers for storing system information. In the memory system, when a simultaneous access to the memory cell array and the register unit is requested, write data for the memory cell array is inputted after write data for the register unit is inputted, respectively through a common data input bus in a write operation, and read data from the memory cell array is outputted after read data from the register unit is outputted, respectively through a common data output bus in a read operation. | 04-16-2009 |
20090103389 | Semiconductor memory device and method of providing product families of the same - Disclosed is a semiconductor memory device including a plurality of banks, a plurality of data input/output terminals, control signal terminals, address signal terminals, and at least one or a plurality of virtual chips, each of which has the banks grouped together, thereby being operable as one independent chip. Each of the data input/output terminals are allocated in dedicated manner to the one virtual chip or one of the plurality of virtual chips. The control signal terminals and the address signal terminals are shared among the one or the plurality of virtual chips. | 04-23-2009 |
20090164728 | SEMICONDUCTOR MEMORY DEVICE AND SYSTEM USING SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device includes a data storage region which includes a plurality of unit data regions storing data, an information storage region which includes a plurality of unit information regions each storing information related to the data stored in associated one of the unit data regions, and an address generation circuit which generates an address designating one of the unit data regions and one of the unit information regions associated with each other. | 06-25-2009 |
20090240866 | Multi-port memory and computer system provided with the same - A multi-port memory, comprising: m (m≧2) input/output ports independent of one another; n (n≧2) memory banks independent of one another; and a route switching circuit capable of optionally setting signal routes of a command, an address, and input/output data between the m input/output ports and the n memory banks, wherein the route switching circuit allocates p (1≦p≦m) input/output ports optionally selected from the m input/output ports to a memory bank optionally selected from the n memory banks. | 09-24-2009 |
20090240897 | Multi-port memory and system using the same - A multi-port memory, comprising: a memory array made of a plurality of memory cells arranged at intersection points between a plurality of bit lines and a plurality of word lines, the memory array being divided into n (an integer of 2 or greater) memory banks; m (an integer of 2 or greater) input/output ports, each independently performing input and output of a command, an address, data to and from each of the memory banks; and a route switching circuit that sets signal for the command, address, and data between the memory banks and the input/output ports, the route switching circuit controlling a connection state of signal lines between the plurality of input/output ports and the plurality of memory banks. | 09-24-2009 |
20090251947 | Semiconductor device having single-ended sensing amplifier - A semiconductor device has a DRAM cell configured from an information charge accumulating capacitor and a memory cell selecting transistor, the threshold voltage value of a MOS transistor that constitutes a sense circuit is monitored, and the monitored threshold voltage value of the MOS transistor is converted through the use of a transfer ratio that is determined based on the capacitance of the information charge accumulating capacitor and the parasitic capacitance of the bit line. The converted voltage value is level-shifted so that the pre-charge voltage of a pre-charge circuit is a pre-set voltage, a current feeding capability is added to the level-shifted voltage value, and the voltage is fed as the pre-charge voltage. | 10-08-2009 |
20090251948 | SEMICONDUCTOR MEMORY DEVICE - In a semiconductor memory device, a memory cell is connected with a local sense amplifier and a global sense amplifier via a local bit line and a global bit line. The local sense amplifier is a single-ended sense amplifier including a single MOS transistor, which detects a potential of the local bit line which varies when reading and writing data with the memory cell. The threshold voltage of the MOS transistor is monitored so as to produce a high-level write voltage and a low-level write voltage, which are corrected and shifted based on the monitoring result so as to properly perform a reload operation on the memory cell by the global local sense amplifier. Thus, it is possible to cancel out temperature-dependent variations of the threshold voltage and shifting of the threshold voltage due to dispersions of manufacturing processes. | 10-08-2009 |
20090257268 | Semiconductor device having single-ended sensing amplifier - A sense amplifier in a semiconductor storage device includes a memory cell for storing information on the basis of the size of the resistance value between a signal input/output terminal and a power supply terminal, the semiconductor storage device having a structure in which the bit line capacitance during signal reading from the memory cell is reduced, wherein the amplifier amplifies a signal outputted from an input/output terminal through the use of a single MOS transistor that has a single-ended structure. | 10-15-2009 |
20090257298 | Semiconductor device having single-ended sensing amplifier - A single-ended sense amplifier in a semiconductor storage device having a hierarchical bit line structure includes a first MOS transistor for amplifying a signal outputted from a memory cell to a bit line, a second MOS transistor for feeding the output of the first MOS transistor to a global bit line, and a global bit line voltage determination circuit; and at least the ON/OFF timing of the second MOS transistor or the read timing of a global sense amplifier that includes the global bit line voltage determination circuit is controlled by the output signal of a delay circuit that includes a replica of the first MOS transistor and a replica of the global bit line voltage determination circuit. | 10-15-2009 |
20090268537 | Semiconductor memory device - A semiconductor memory device of the invention comprises unit blocks into which the memory cell array is divided, rows of sense amplifiers arranged at one end and the other end of the plurality of bit lines in the unit block, switch means for switching a connection state between the unit block and the row of sense amplifiers attached to the unit block; and control means for controlling the switch means so as to form a transfer path from the row of sense amplifiers attached to a predetermined the unit block leading to the row of sense amplifiers as a saving destination not attached to the predetermined the unit block. This row of sense amplifiers attached to the predetermined the unit block functions as a cache memory. | 10-29-2009 |
20100054016 | Semiconductor memory device having floating body type NMOS transistor - A semiconductor memory device comprises a memory cell array and a sense amplifier circuit. The memory cell array includes a first NMOS transistor which has a gate electrode connected to a word line and has one source/drain region connected to a bit line. The sense amplifier circuit includes a second NMOS transistor which has a gate electrode connected to the bit line and has one source/drain region connected to a predetermined voltage. In the semiconductor memory device, each of the first and second MOS transistors is a floating body type NMOS transistor, and the predetermined voltage is supplied to the bit line at least in a precharge operation, thereby preventing characteristic deterioration due to accumulation of holes in the floating body. | 03-04-2010 |
20100054065 | Sense amplifier circuit and semiconductor memory device - A single-ended sense amplifier circuit amplifies a signal of a memory cell and transmitted through a bit line, and comprises first and second MOS transistors. The first MOS transistor supplies a predetermined voltage to the bit line and controls connection between the bit line and a sense node in response to a control voltage, and the second MOS transistor has a gate connected to the sense node and amplifies a signal transmitted from the bit line via the first MOS transistor. The predetermined voltage is supplied to the bit line before read operation and is set to a value such that a required voltage difference at the sense node between high and low level data of the memory cell can be obtained near a changing point between a charge transfer mode and a charge distributing mode within a range of a read voltage of the memory cell. | 03-04-2010 |
20100054066 | Memory device, semiconductor memory device and control method thereof - A semiconductor memory device comprises a memory cell array, first and second bit lines, first and second amplifiers, and a sense amplifier control circuit. An amplifying element in the first sense amplifier amplifiers the signal of the first bit line and converts it into an output current. The second bit line is selectively connected to the first bit line via the first sense amplifier. A signal voltage decision unit in the second sense amplifier determines the signal level of the second bit line being supplied with the output current. The sense amplifier control circuit controls connection between the amplifying element and the unit in accordance with a determination timing, which switches the above connection from a connected state to a disconnected state at a first timing in a normal operation and switches in the same manner at a delayed second timing in a refresh operation. | 03-04-2010 |
20100061170 | Sense amplifier circuit and semiconductor memory device - A single-ended sense amplifier circuit comprises first and second MOS transistors and first and second voltage setting circuits. The first MOS transistor supplies a predetermined voltage to the bit line and switches connection between the bit line and a sense node in response to a control voltage, and the second MOS transistor having a gate connected to the sense node amplifies a signal transmitted from the bit line via the first MOS transistor. The first voltage setting circuit sets the bit line to a first voltage, and the second voltage setting circuit sets the sense node to a second voltage. In the sense amplifier circuit, after setting the bit line and the sense node to respective voltages, the bit line is driven in a charge distributing mode via the first MOS transistor so that a signal voltage at the sense node is amplified by the second MOS transistor. | 03-11-2010 |
20110063891 | SEMICONDUCTOR DEVICE, SEMICONDUCTOR MEMORY DEVICE AND DATA PROCESSING SYSTEM COMPRISING SEMICONDUCTOR SYSTEM - A semiconductor device comprises a memory cell, a bit line, a sense amplifier operating between a first voltage and a second voltage higher than the first voltage, a transfer control circuit including a transfer transistor, and a write circuit writing data into the memory cell through the bit line based on the first voltage and a third voltage. The sense amplifier receives and amplifiers the signal voltage at a sense node when the transfer transistor controls the connection between the bit line and the sense node in response to a transfer control voltage. The third voltage is set to a voltage lower than the second voltage and higher than the transfer control voltage, and the sense node is set to a voltage higher than the transfer control voltage in an initial period of a read operation before the data of the memory cell is read out to the bit line. | 03-17-2011 |
20110063892 | SENSE AMPLIFIER CIRCUIT AND SEMICONDUCTOR DEVICE - A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes. | 03-17-2011 |
20110063935 | SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM COMPRISING SEMICONDUCTOR DEVICE - A semiconductor device comprises a sense amplifier circuit amplifying a signal transmitted through the bit line, first/second data lines transmitting the signal amplified by the sense amplifier circuit, a read amplifier circuit driven by a first voltage and amplifying the signal; first/second switch circuits controlling connection between the above components, first/second voltage setting circuits setting the second/third data lines to a second voltage lower than the first voltage. A predetermined voltage obtained by adding the second voltage to a threshold voltage of a transistor in the second/third switch circuit is applied to the gate terminal thereof, and ends of the data lines are connected to the source and drain terminals thereof. | 03-17-2011 |
20110134678 | Semiconductor device having hierarchical structured bit line - A sense operation with respect to simultaneously-accessed two memory cells is performed by time division by using two sense amplifiers, and thereafter restore operations are performed simultaneously. With this arrangement, it is not necessary to provide switches in the middle of global bit lines, and no problem occurs when performing the restore operation by time division. Further, because a parasitic CR model of a first sense amplifier and that of a second sense amplifier become mutually the same, high sensitivity can be maintained. | 06-09-2011 |
20110164460 | Semiconductor device and method of controlling the same - A semiconductor device includes a delay buffer, and a pipeline control circuit. The pipeline control circuit controls the delay buffer to hold read data from outputting to a read/write bus for each of banks based on a read command to the each bank while the pipeline control circuit controlling the delay buffer to output write data to the read/write bus, when a next command to the each bank is a write command for the write data. The read/write bus is common to the banks. | 07-07-2011 |
20110176356 | SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM - A semiconductor device comprises a memory cell including a capacitor and a select transistor with a floating body structure, a bit line connected to the select transistor, a bit line control circuit, and a sense amplifier amplifying a signal read out from the memory cell. The bit line control circuit sets the bit line to a first potential during a non-access period of the memory cell, and thereafter sets the bit line to a second potential during an access period of the memory cell. Thereby, the data retention time can be prolonged by reducing leak current at a data storage node of the memory cell so that an average consumption current for the data retention can be reduced. | 07-21-2011 |
20110179239 | SEMICONDUCTOR MEMORY DEVICE AND INFORMATION DATA PROCESSING APPARATUS INCLUDING THE SAME - A semiconductor memory device includes a plural number of data input/output pins, a plural number of banks, in each of which a plural number of the information data is stored, a selector and a control circuit. In a first access mode, the control circuit simultaneously accesses the multiple banks in response to a single read-out command or to a single write-in command from outside. In the first access mode, the selector coordinates a plurality of data input/output pins with the multiple banks in a predetermined relationship. | 07-21-2011 |
20110188325 | Semiconductor device and data processing system - A semiconductor device comprises a bit line transmitting a signal to be sensed, a single-ended sense amplifier sensing and amplifying the signal transmitted from the bit line to the input node, and a reference voltage supplying circuit outputting a reference voltage. The sense amplifier includes a first transistor for charge transfer between the bit line and an input node, and the voltage value of the reference voltage is controlled in association with a threshold voltage of the first transistor. The reference voltage is set to a first logical value of the transfer control signal which controlled to be first and second logical values. | 08-04-2011 |
20110199840 | Semiconductor storage device - A device includes a memory cell array having a plurality of memory cells; sense amplifiers, which are arranged adjacent to the memory cell array, for amplifying signals that have been read out of corresponding ones of the memory cells; readout signal lines; a plurality of connection circuits for selectively connecting the sense amplifiers and the readout signal lines; a plurality of main amplifiers for amplifying and outputting signals that have been read out of the sense amplifiers via the readout signal lines by the connection circuits selected by selection signals; an enable signal line connected to the main amplifiers; and an enable signal generating circuit for outputting a main amplifier enable signal to the enable signal line. The enable signal generating circuit is placed in close proximity to the connection circuits. | 08-18-2011 |
20110205777 | Semiconductor memory device having vertical transistors - A device includes a first region including a plurality of first memory elements and a plurality of first vertical transistors, the first vertical transistors comprising a plurality of first selective transistors and a first switching transistor, each of the first selective transistors including an upper electrode coupled to a corresponding one of the first memory elements and a lower electrode, the first switching transistor including an upper electrode and a lower electrode coupled in common to the lower electrodes of the first selective transistors through a first signal line, a second region arranged to make a first line with the first region in a first direction and including a plurality of second memory elements and a plurality of second vertical transistors, the second vertical transistors comprising a plurality of second selective transistors and a second switching transistor, and a third region sandwiched between the first and the second regions. | 08-25-2011 |
20110205812 | SEMICONDUCTOR DEVICE - A semiconductor device includes a sense amplifier, transistors selectively establishing electrical connection between the sense amplifier and a data bus, depending on address; a write amplifier connected to the data bus, an external terminal outputting data from a memory cell to outside via the sense amplifier, the transistors, and the data bus in a first operation mode and supplying data from outside to the sense amplifier via the write amplifier, the data bus, and the transistors in a second operation mode, and a control circuit supplying an electric potential to gate electrodes of first transistors that establish the electrical connection depending on the address, wherein in a first operation mode, the control circuit supplies a first electric potential to the gate electrodes of the first transistors, so that the first transistors exhibit a first impedance value and in the second operation mode, the control circuit supplies a second electric potential to gate electrodes of the first transistors, so that the first transistors exhibit a second impedance value, an absolute value thereof being lower than that of the first impedance value. | 08-25-2011 |
20110205820 | Semiconductor device - The semiconductor device comprises first and second memory cells, first and second bit lines connected to the first/second memory cells, first and second amplifiers connected to the second bit line, a local input/output line commonly connected to the first/second amplifiers, first and second local column switches connected between the first/second amplifiers and the local input/output line, a second local column switch connected between the second amplifier and the local input/output line, a column select line, a first global column switch connected between the column select line and the first local column switch and controlling a connection therebetween in response to a first select signal, and a second global column switch connected between the column select line and the second local column switch and controlling a connection therebetween in response to a first select signal. | 08-25-2011 |
20110205824 | Data processing system - A data processing system includes a first semiconductor device that has a plurality of blocks each including plural data, and a second semiconductor device that has a first control circuit controlling the first semiconductor device, and the first control circuit issues a plurality of commands to communicate with the first semiconductor device in units of access units including a plurality of first definitions that define a plurality of burst lengths indicating numbers of different data, respectively, and a plurality of second definitions that define correspondences between certain elements of data among the plural data included in the blocks, respectively, and arrangement orders in the numbers of different data that constitute the burst lengths, respectively, and communicates with the first semiconductor device through the plural data in the numbers of different data according to the first and second definitions. | 08-25-2011 |
20110225355 | SEMICONDUCTOR DEVICE, REFRESH CONTROL METHOD THEREOF AND COMPUTER SYSTEM - A semiconductor device comprises a first memory cell array, a register storing information of whether or not one of the word lines in an active state exists in a unit area and storing address information, and a control circuit controlling a refresh operation for a refresh word line based on the information in the register when receiving a refresh request. When the one of the word lines in an active state does not exist, memory cells connected to the refresh word line are refreshed. When the one of the word lines in an active state exists, the one of the word lines in an active state is set into an inactive state temporarily and the memory cells connected to the refresh word line are refreshed after precharging bit lines of the memory cells. | 09-15-2011 |
20110248697 | Semiconductor device and data processing system - A semiconductor device comprises a first circuit outputting a signal to a first signal line, a first FET applied with a driving signal and having a gate electrode connected to a first node, a second FET controlling an electrical connection between the first signal line and the first node, a third FET amplifying a signal of the first node, a second circuit precharging the first signal line, and a voltage control circuit. A gate capacitance of the first FET is controlled in response to a voltage difference between the first node and the driving signal. The voltage control circuit shifts a potential of the driving signal when the second FET is non-conductive after the signal of the first-circuit is transmitted to the first node, and performs an offset control for the driving signal so as to compensate a variation of a threshold voltage of the first FET. | 10-13-2011 |
20110261631 | SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM COMPRISING SEMICONDUCTOR DEVICE - A semiconductor device comprises a sense amplifier circuit amplifying a signal transmitted through the bit line, first/second data lines transmitting the signal amplified by the sense amplifier circuit, a read amplifier circuit driven by a first voltage and amplifying the signal; first/second switch circuits controlling connection between the above components, first/second voltage setting circuits setting the second/third data lines to a second voltage lower than the first voltage. A predetermined voltage obtained by adding the second voltage to a threshold voltage of a transistor in the second/third switch circuit is applied to the gate terminal thereof, and ends of the data lines are connected to the source and drain terminals thereof. | 10-27-2011 |
20110304382 | Semiconductor device and data processing system - A semiconductor device comprises a first sense amplifier, first to third transmission lines, and first to third switches. The first and second transmission lines are connected to the first sense amplifier. The first and third switches control connections of the first to third transmission lines, and the second switch controls a connection between a fixed potential and third transmission line. When the second transmission line is not accessed, the first and third switches are brought into a non-conductive state and the second switch is brought into a conductive state, and the fixed potential is supplied to the third transmission line, thereby suppressing influence of the coupling noise between the transmission lines. | 12-15-2011 |
20110305097 | Semiconductor device and data processing system - A semiconductor device comprises transmission lines, inverting circuits, first, second and third switches, global sense amplifiers, and a control circuit. The first switch switches between the transmission line and the input of the inverting circuit, the second switch switches between the transmission line and the output of the transmission line, and the third switch switches between the adjacent transmission lines. The control circuit turns off the first and second switches so that the transmission lines are brought into a floating state in a state where signals of the transmission lines are held in the inverting circuits by the global sense amplifiers. After charge sharing of the transmission lines occurs by turning on the third switches within a predetermined period, the control circuit turns off the second switches so that the transmission lines are inverted and driven via the inverting circuits and the second switches. | 12-15-2011 |
20110315945 | Method of manufacturing semiconductor memory device - A semiconductor device includes a semiconductor substrate, a non-volatile semiconductor memory element formed over the semiconductor substrate, including a variable resistance element including a laminate comprising a first electrode, a variable resistance layer, and a second electrode, and a volatile semiconductor memory element formed over the semiconductor substrate, including a capacitance element including a laminate comprising a third electrode, a dielectric layer including a same material as the variable resistance layer, and a fourth electrode. | 12-29-2011 |
20120008368 | Semiconductor device having single-ended sensing amplifier - A semiconductor device includes a bit line, a memory cell coupled to the bit line, the memory cell being configured such that a current flowing there the memory cell is varied in accordance with information stored M the memory cell, a first transistor coupled at a control electrode thereof to the bit line, a second transistor coupled to the bit line and supplied at a control electrode thereof with a first control signal, a global bit line, and a third transistor coupled in series with the first sistor between a node and the global bit line, the third transistor supplied at a control electrode thereof with a second control signal. | 01-12-2012 |
20120063241 | Semiconductor device and control method thereof - A semiconductor device has a hierarchical bit line structure and comprises first and second local bit lines transmitting first and second signals of first and second memory cells corresponding to a selected word line, and first and second global bit lines electrically connected to the first and second local bit lines through first and second switches, first and second sense amplifiers connected to the first and second global bit lines, and a control circuit. During a first period after the first and second memory cells are simultaneously accessed, the control circuit controls the first switch to conduction state so that the first sense amplifier amplifies the first signal and controls the second switch to non conduction state. During a second period after sensing of the first sense amplifier finishes, the control circuit controls the second switch to conduction state so that the second sense amplifier amplifies the second signal. | 03-15-2012 |
20120113735 | Semiconductor device having current change memory cell - A semiconductor device comprises a first transistor connected between a bit line and a sense node, and a second transistor amplifying a signal of the sense node. A first potential applied to a gate of the first transistor, a second potential supplied to the sense node, and a third potential supplied to the bit line are controlled so that the first potential applied to a gate of the first transistor is between the second and third potentials, the second potential is set larger than the third potential, and a predetermined potential obtained by subtracting a threshold voltage of the first transistor from the first potential is smaller than the third potential and higher than a low potential supplied to the second transistor. A potential of the bit line transitions from the third potential toward the low potential in accordance with data of a current change memory cell. | 05-10-2012 |
20120113736 | Semiconductor device having hierachical bit line structure - A semiconductor device of the invention comprise a memory cell array configured with hierarchical local bit lines and global bit lines, in which there are provide local bit lines, global bit lines, switches controlling a connection between the global bit lines, sense amplifiers, and a control circuit controlling the switches. In a first period, each sense amplifier amplifies a signal of one of adjacent global bit lines, and in a second period, each sense amplifier amplifies a signal of the other thereof. Accordingly, coupling between the global bit lines can be suppressed. | 05-10-2012 |
20120127816 | SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE - Disclosed herein is a semiconductor device comprising a memory cell, a local bit line coupled to the memory cell, a global bit line provided correspondingly to the local bit line, and a bit line control circuit coupled between the local bit line and the global bit line. The bit line control circuit includes a restoring circuit that is activated in a refresh mode to refresh data of the memory cell while being in electrical isolation from the global bit line. | 05-24-2012 |
20120147686 | SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE AND CONTROL METHOD THEREOF - Disclosed herein is a semiconductor device comprising a global bit line and a local bit line, and a switch coupled therebetween. Upon performing a precharge operation, a precharge voltage is supplied to the global bit line with turning the switch ON, so that the local bit line receives the precharge voltage through the global bit line and the switch, and after a lapse of a predetermined time, a precharge voltage is further supplied to the local bit line without an intervention of the global bit line and the switch. | 06-14-2012 |
20120195103 | SEMICONDUCTOR DEVICE HAVING COMPLEMENTARY BIT LINE PAIR - Disclosed herein is a semiconductor device comprising complementary pair of bit lines, memory cells connected to the bit lines, dummy cells having the same structure as the memory cells, a differential sense amplifier, an equalizing circuit equalizing potentials of the bit lines, and a control circuit. The memory cells are disconnected from the bit lines and the dummy cells are connected to the bit lines, and subsequently the bit lines are equalized by the equalizing circuit. When accessing a selected memory cell, the equalizing circuit is inactivated, a corresponding dummy cell is disconnected from the bit line, and subsequently the selected memory cell is connected to the bit line. Thereafter, the sense amplifier is activated so that potentials of the bit lines are amplified respectively. | 08-02-2012 |
20120218845 | SEMICONDUCTOR DEVICE AND CONTROL METHOD THEREOF - Disclosed herein is a semiconductor device comprising an array having a hierarchical bit line structure, global bit lines adjacent to each other, local bit lines corresponding to the global bit lines, hierarchical switches, precharge circuits precharging the global bit lines, precharge circuits precharging the local bit lines, and a control circuit. When performing a test of the array, precharge voltages for the global bit lines are set to potentials different from each other, and the control circuit controls the potentials to be applied to the local bit lines through the global bit lines and the hierarchical switches. | 08-30-2012 |
20120236673 | SEMICONDUCTOR DEVICE - Disclosed herein a device that includes a memory cell array including plurality of word lines, a plurality of bit lines each intersecting the word lines and a plurality of memory cells each disposed at an associated one of intersections of the word and bit lines, and the device further includes a driver configured to drive a selected one of the word lines from an inactive level to an active and to drive the selected one of the word lines from the active level to an intermediate level at a first rate and from the intermediated level to the inactive level at a second rate. The intermediate level is between the active and inactive levels, and the first rate is greater than the second rate. | 09-20-2012 |
20120275255 | SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM COMPRISING SEMICONDUCTOR DEVICE - A semiconductor device comprises a sense amplifier circuit amplifying a signal transmitted through the bit line, first/second data lines transmitting the signal amplified by the sense amplifier circuit, a read amplifier circuit driven by a first voltage and amplifying the signal; first/second switch circuits controlling connection between the above components, first/second voltage setting circuits setting the second/third data lines to a second voltage lower than the first voltage. A predetermined voltage obtained by adding the second voltage to a threshold voltage of a transistor in the second/third switch circuit is applied to the gate terminal thereof, and ends of the data lines are connected to the source and drain terminals thereof. | 11-01-2012 |
20130021856 | SEMICONDUCTOR DEVICE - Disclosed herein is a device including a transistor that is connected between a bit line and a data line and turned ON by a first level in date read mode and by a second level in data write mode, the first and second levels being different from each other. The device further includes a write driver that includes an output node coupled to the data line. The write driver drives the output node in data write mode without assertion of data masking, but brings the output node into a high-impedance state in data write mode with assertion of data masking. | 01-24-2013 |
20130070506 | SEMICONDUCTOR DEVICE HAVING STACKED LAYERS - A semiconductor device is disclosed in which there are provided a first substrate including memory cells and at least one bit line electrically coupled to the memory cells, and a second substrate including a sense amplifier. Each of the memory cells includes a first transistor, and the sense amplifier includes a second transistor. The second substrate is stacked with the first substrate such that the sense amplifier amplifies data transferred through the bit line from a selected one of the memory cells. The first transistor is lower in carrier mobility than the second transistor. | 03-21-2013 |
20130082404 | SEMICONDUCTOR DEVICE AND MEMORY SYSTEM - A semiconductor device is disclosed in which a plurality of memory cores are provided on a semiconductor chip. Each of the memory cores comprises: first and second circuit regions and a first and second through electrode groups. a first power supply is supplied in the first circuit region in which a data bus for parallel data is driven, and a second power supply separated from the first power supply is supplied in the second circuit region in which the parallel data and serial data are bidirectionally converted. The first through electrode group includes through electrodes supplying the first power supply to the first circuit region, and the second through electrode group includes through electrodes supplying the second power supply to the second circuit region. | 04-04-2013 |
20130097388 | DEVICE AND DATA PROCESSING SYSTEM - A device is disclosed which includes a register storing a plurality of latency data and a control unit responding to the latency data. Each of the latency data indicates a period of time between issue of a data transfer request command responsive to an access request from one of access request sources and initiation of a data transfer operation responsive to the data transfer request command. The control unit controls an order in issue of data transfer request commands responsive to access requests from the access request sources so that between issue of a first data transfer request command responsive to a first access request and initiation of a first data transfer operation responsive to the first data transfer request command, at least issue of a second data transfer request command responsive to a second access request is performed. | 04-18-2013 |
20130107648 | MEMORY DEVICE, SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD THEREOF | 05-02-2013 |
20130107650 | SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE | 05-02-2013 |
20130173864 | SEMICONDUCTOR DEVICE INCLUDING ROW CACHE REGISTER - Disclosed herein is a device that includes a memory cell array having a plurality of pages, a row cache register, and an array control circuit. The array control circuit is configured to: select one of the pages as a selected page to form an electrical path between the selected page and the row cache register in response to a first command with a row address; cut the electrical path between the selected page and the row cache register; and form the electrical path again between the selected page and the row cache register in response to a second command without the row address. | 07-04-2013 |
20130223170 | SEMICONDUCTOR MEMORY DEVICE - A semiconductor memory device comprises: plurality of global bit lines; plurality of sense amplifier circuits each connected to corresponding one of the plurality of global bit lines; plurality of column selection lines each of which is connected to or disconnected from corresponding one of the plurality of sense amplifier circuits according to column address information; and plurality of local bit lines including first local bit line and second local bit line. The first local bit line is connected to or disconnected from corresponding one of the plurality of global bit lines according to first row address information different from column address information. The second local bit line replaces first local bit line when defect is present in first local bit line and is connected to or disconnected from corresponding global bit line according to second row address information different from column address information. | 08-29-2013 |
20130229857 | SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM - A semiconductor device comprises a memory cell including a capacitor and a select transistor with a floating body structure, a bit line connected to the select transistor, a bit line control circuit, and a sense amplifier amplifying a signal read out from the memory cell. The bit line control circuit sets the bit line to a first potential during a non-access period of the memory cell, and thereafter sets the bit line to a second potential during an access period of the memory cell. Thereby, the data retention time can be prolonged by reducing leak current at a data storage node of the memory cell so that an average consumption current for the data retention can be reduced. | 09-05-2013 |
20130229870 | NONVOLATILE RAM - A semiconductor random access memory device includes a memory cell including a resistor whose resistance varies by formation and disappearance of a filament due to an oxidation-reduction reaction of metal ions, a memory area configured to include a first memory area operable in a nonvolatile mode in which a stored content thereof is not lost by a power-off event, and a second memory area operable in a volatile mode in which the stored content thereof is lost by the power-off event, each of the first memory area and the second memory area including the plurality of the memory cells, a register circuit that stores information including a first address information indicating the first memory area, and a second address information indicating the second memory area, and a control circuit that controls the nonvolatile mode, and the volatile mode, with reference to the information stored in the register circuit. | 09-05-2013 |
20130301364 | SENSE AMPLIFIER CIRUIT AND SEMICONDUCTOR DEVICE - A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes. | 11-14-2013 |
20130315018 | SENSE AMPLIFIER CIRUIT AND SEMICONDUCTOR DEVICE - A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes. | 11-28-2013 |
20130328187 | SEMICONDUCTOR DEVICE - There is provided a semiconductor device which includes a plurality of first through-substrate vias that are used to supply power from a first power supply and that penetrate through a substrate structure, and a plurality of second through-substrate vias that are used to supply power from a second power supply different from the first power supply and that penetrate through a substrate structure. The semiconductor device also includes a through-substrate via string composed by the first and second through-substrate vias, in which the first through-substrate vias are located adjacent to one another and the second through-substrate vias are also located adjacent to one another. The through-substrate via string is disposed in the substrate structure for extending in a first direction. | 12-12-2013 |
20140003116 | SEMICONDUCTOR DEVICE HAVING HIERARCHICAL STRUCTURED BIT LINES | 01-02-2014 |
20140032941 | SEMICONDUCTOR DEVICE EMPLOYING DVFS FUNCTION - Disclosed herein is a device that includes: a memory cell array including a plurality of memory cells, the memory cell array operates on a first internal voltage; a peripheral circuit accessing selected one or ones of the memory cells, the peripheral circuit operates on a second internal voltage; a first internal voltage generation circuit that supplies the first internal voltage to the memory cell array; and a second internal voltage generation circuit that supplies the second internal voltage to the peripheral circuit. The second internal voltage generation circuit sets the second internal voltage to a first voltage value in a first mode, and to a second voltage value that is different from the first voltage value in a second mode. The first internal voltage generation circuit sets the first internal voltage to a third voltage value in both the first and second modes. | 01-30-2014 |
20140056063 | SEMICONDUCTOR DEVICE HAVING CURRENT CHANGE MEMORY CELL - A method includes performing a read operation on a memory cell of a device including a sensing line, a bit line coupled to the memory cell, a first transistor having a source-drain path coupled between the sensing line and the bit line, and a second transistor having a gate coupled to sense the sensing line, the performing including providing a gate of the first transistor with a first voltage, providing the sensing line with a second voltage, and providing the bit line with a third voltage, the third voltage being independent from the second voltage. | 02-27-2014 |
20140078805 | SEMICONDUCTOR MEMORY DEVICE HAVING VERTICAL TRANSISTORS - A device includes first and second regions including first and second amplifiers, respectively and a memory cell array region formed between the first and second regions and includes first and second conductive layers each extending in a first direction, and a plurality of first pillar elements arranged in line in the first direction on the first conductive layer, each of the first pillar elements being coupled to the first conductive layer at one end thereof, and the first pillar elements comprising a plurality of first elements and a second element, and a plurality of second pillar elements arranged in line in the first direction on the second conductive layer, each of the second pillar elements being coupled to the second conductive layer at one end thereof, and the second pillar elements comprising a plurality of third elements and a fourth element. | 03-20-2014 |
20140082306 | SEMICONDUCTOR MEMORY DEVICE AND INFORMATION DATA PROCESSING APPARATUS INCLUDING THE SAME - A semiconductor memory device includes a plural number of data input/output pins, a plural number of banks, in each of which a plural number of the information data is stored, a selector and a control circuit. In a first access mode, the control circuit simultaneously accesses the multiple banks in response to a single read-out command or to a single write-in command from outside. In the first access mode, the selector coordinates a plurality of data input/output pins with the multiple banks in a predetermined relationship. | 03-20-2014 |
20140085997 | SEMICONDUCTOR DEVICE HAVING HIERARCHICAL BIT LINE STRUCTURE - A method includes accessing a memory cell to allow the memory cell to output data stored therein onto a local bit line; transferring, in response to a data read mode, a signal related to the data from the local bit line to a global bit line; and restoring, in response to a refresh mode, the data into the memory cell while keeping the local bit line electrically isolated from the global bit line. | 03-27-2014 |
20140092691 | SEMICONDUCTOR STORAGE DEVICE - A semiconductor includes a memory cell array including a plurality of memory cells. A first amplifier produces, when activated, a first data signal related to data stored in a selected first one of the memory cells. A first transistor is between the output node of the first amplifier and a first data line and is turned ON in response to a first selection signal to convey the first data signal from the first amplifier onto the first data line. A second amplifier is coupled to the first data line and amplifies, when activated, the first data signal, and is further coupled to the first signal line and activated in response to a first activation signal that is transferred through a first signal line. A second transistor is coupled to the first signal line and is turned ON in response to the first selection signal to the first signal line. | 04-03-2014 |
20140133255 | SEMICONDUCTOR DEVICE, REFRESH CONTROL METHOD THEREOF AND COMPUTER SYSTEM - A semiconductor device comprises a first memory cell array, a register storing information of whether or not one of the word lines in an active state exists in a unit area and storing address information, and a control circuit controlling a refresh operation for a refresh word line based on the information in the register when receiving a refresh request. When the one of the word lines in an active state does not exist, memory cells connected to the refresh word line are refreshed. When the one of the word lines in an active state exists, the one of the word lines in an active state is set into an inactive state temporarily and the memory cells connected to the refresh word line are refreshed after precharging bit lines of the memory cells. | 05-15-2014 |
20140169111 | DEVICE INCLUDING A PLURALITY OF MEMORY BANKS AND A PIPELINE CONTROL CIRCUIT CONFIGURED TO EXECUTE A COMMAND ON THE PLURALITY OF MEMORY BANKS - A method for carrying out read and write operations in a synchronous memory device having a shared I/O, includes receiving a read command directed to a first internal memory bank during a first timeslot, activating the first internal memory bank to access read data at a read address requested by the read command, receiving a write command directed to a second internal memory bank during a second timeslot later than the first timeslot, determining whether a data collision between the read data for output to the shared I/O with normal read latency and write data to be received on the shared I/O with normal write latency would occur, and receiving the write data on the shared I/O with the normal write latency during a third timeslot later than the second timeslot. | 06-19-2014 |
20140241088 | SEMICONDUCTOR DEVICE HAVING COMPLEMENTARY BIT LINE PAIR - Disclosed herein is a semiconductor device comprising complementary pair of bit lines, memory cells connected to the bit lines, dummy cells having the same structure as the memory cells, a differential sense amplifier, an equalizing circuit equalizing potentials of the bit lines, and a control circuit. The memory cells are disconnected from the bit lines and the dummy cells are connected to the bit lines, and subsequently the bit lines are equalized by the equalizing circuit. When accessing a selected memory cell, the equalizing circuit is inactivated, a corresponding dummy cell is disconnected from the bit line, and subsequently the selected memory cell is connected to the bit line. Thereafter, the sense amplifier is activated so that potentials of the bit lines are amplified respectively. | 08-28-2014 |
20140293721 | SENSE AMPLIFIER CIRCUIT AND SEMICONDUCTOR DEVICE - A single-ended sense amplifier circuit of the invention comprises first and second MOS transistors and first and second precharge circuits. The first MOS transistor drives the bit line to a predetermined voltage and switches connection between the bit line and a sense node and the second MOS transistor whose gate is connected to the sense node amplifies the signal via the first MOS transistor. The first precharge circuit precharges the bit line to a first potential and the second precharge circuit precharges the sense node to a second potential. Before sensing operation, the bit line is driven to the predetermined voltage when the above gate voltage is controlled to decrease. The predetermined voltage is appropriately set so that a required voltage difference at the sense node between high and low levels can be obtained near a changing point between charge transfer/distributing modes. | 10-02-2014 |
20150046774 | SEMICONDUCTOR DEVICE AND ERROR CORRECTION INFORMATION WRITING METHOD - A semiconductor device includes first and second memory cell arrays, each including a plurality of memory cells, each of which is connected between first and second terminals and is configured to be written to a first resistance state by applying a first current in a first direction between the first and second terminals and be written to a second resistance state by applying a second current in a second direction opposite to the first direction between the first and second terminals. The semiconductor device further includes an error-correction circuit and a control circuit. Additional apparatus and methods are disclosed. | 02-12-2015 |
20150063020 | SEMICONDUCTOR DEVICE - A method includes measuring a first pulse width of a resistance variable memory cell coupled between a first terminal and a second terminal, the first pulse width including a period from starting a first data writing of the resistance variable memory cell by applying a voltage between the first and second terminals to ending the first data writing of the resistance variable memory cell, and measuring a second pulse width of the resistance variable memory cell coupled between the first and the second terminal. The method includes setting longer one of the first and second pulse widths in a first storage area as a pulse width to be used in program. | 03-05-2015 |
20150074493 | SEMICONDUCTOR DEVICE AND ERROR CORRECTION METHOD - A device is provided with: memory cell array including plurality of first and second memory cells and one or more third memory cells; judging circuit that judges plurality of data values held by selected first and second memory cells of the first and second memory cells, by referring to reference potential corresponding to reference data held by a selected third memory cell; and error detection and correction circuit that detects whether or not there is error in the judged data values of the first and/or second memory cells, with judged data value of the first and second memory cells as error correcting code. When the error detection and correction circuit detects that there is error exceeding error correction capability in the judged data values, control is performed to write reference data to the selected third memory cell. | 03-12-2015 |