Patent application number | Description | Published |
20090293055 | Central Office Based Virtual Personal Computer - A virtual personal computer is implemented in a communication system comprising a plurality of central offices each of which communicates with a plurality of client devices over a corresponding access network. A given one of the central offices comprises at least one compute server and at least one storage server. The virtual personal computer is configured by allocating physical processing resources of the compute server and physical storage resources of the storage server to that virtual personal computer. User access is provided to the virtual personal computer via one of the client devices. The virtual personal computer can be dynamically reconfigured by altering the allocation of at least one of the physical processing resources and the physical storage resources to the given virtual personal computer responsive to particular applications selected by the user to run on the given virtual personal computer. | 11-26-2009 |
20090295606 | APPARATUS FOR ENHANCING PACKET COMMUNICATION - An apparatus for enhancing packet communication is disclosed. In one embodiment, the apparatus includes an encoder configured to convert input data to a binary coded base system of an augmented code employing a base of an original code used for coding the input data, wherein the augmented code employs more symbols for coding than the original code, the encoder including: (1) an adder configured to add the input data to a multiplication product to generate a base sum that is binary-coded in the augmented code, (2) a multiplier configured to multiply an accumulated value by a base of the original code to provide the multiplication product that is binary-coded in the augmented code, and (3) an accumulator configured to employ the base sum to provide an accumulated value as an output for the encoder, wherein the accumulated value is binary-coded in the augmented code to represent the input data. | 12-03-2009 |
20100117624 | NETWORK-DISTRIBUTED OSCILLOSCOPE AND METHOD OF OPERATION THEREOF - A system and method for achieving oscilloscope functionality over a network. In one embodiment, the system includes: ( | 05-13-2010 |
20100158051 | Method, Apparatus and System for Frequency Synchronization Between Devices Communicating over a Packet Network - An endpoint or other communication device of a communication system includes a clock recovery module. The communication device is operative as a slave device relative to another communication device that is operative as a master device. The clock recovery module comprises a clock recovery loop configured to control a slave clock frequency of the slave device so as to synchronize the slave clock frequency with a master clock frequency of the master device. The clock recovery loop utilizes a frequency error estimator implemented as a maximum-likelihood estimator with slope fitting based on a sequence of arrival timestamps, and a loop filter implemented as a series combination of an adaptive-bandwidth filter and a proportional-integral controller. The clock recovery module may further comprise a discontinuity detector configured to detect a discontinuity in delays of respective timing messages, and a loop controller operative to place the clock recovery loop in a particular state responsive to detection of the discontinuity. | 06-24-2010 |
20100158181 | Frequency Synchronization with Compensation of Phase Error Accumulation Responsive to a Detected Discontinuity - An endpoint or other communication device of a communication system includes a clock recovery module. The communication device is operative as a slave device relative to another communication device that is operative as a master device. The clock recovery module comprises a clock recovery loop configured to control a slave clock frequency of the slave device so as to synchronize the slave clock frequency with a master clock frequency of the master device. The clock recovery module further comprises a discontinuity detector configured to detect a delay discontinuity in timing messages received in the slave device from the master device, and a loop controller operative to place the clock recovery loop in a particular state responsive to the detected discontinuity. The particular state comprises a state in which a normal operating mode of the loop is interrupted and a compensating drive signal is applied to a clock source of the slave device to at least partially offset phase error accumulation associated with the detected discontinuity. | 06-24-2010 |
20100158183 | Frequency Synchronization Using First and Second Frequency Error Estimators - An endpoint or other communication device of a communication system includes a clock recovery module. The communication device is operative as a slave device relative to another communication device that is operative as a master device. The clock recovery module comprises a clock recovery loop configured to control a slave clock frequency of the slave device so as to synchronize the slave clock frequency with a master clock frequency of the master device. The clock recovery loop comprises a primary loop having a first frequency error estimator for generating a first estimate of error between the master and slave clock frequencies, a second frequency error estimator outside of the primary loop for generating a second estimate of error between the master and slave clock frequencies, and an accumulator coupled between the second frequency error estimator and the primary loop. The second estimate is controllably injected into the primary loop via the accumulator. | 06-24-2010 |
20120069944 | Frequency Synchronization Using Clock Recovery Loop with Adaptive Packet Filtering - An endpoint or other communication device of a communication system includes a clock recovery loop having a phase error estimator. The communication device is operative as a slave device relative to another communication device that is operative as a master device. The clock recovery loop is configured to control a slave clock of the slave device responsive to a phase error estimate generated by the phase error estimator so as to synchronize the slave clock with a master clock of the master device. The phase error estimator comprises a plurality of filters each configured to generate a different estimate of master clock phase using at least a subset of a plurality of packets received from the master device, and control logic for adaptively selecting at least a particular one of the plurality of filters for use in generating the phase error estimate to be processed in the clock recovery loop. | 03-22-2012 |
20120106576 | Transparent Clock Adaptor for a Network Device - A transparent clock adaptor is provided for use with a router, switch or other network device that does not otherwise support transparent clock functionality. The transparent clock adaptor comprises a network port for coupling to a link of a network, a local port for coupling to a port of the network device, transparent clock processing circuitry operative to perform one or more transparent clock timing adjustment operations for each of a plurality of packets including at least one packet arriving in the adaptor via the network port and at least one packet arriving in the adaptor via the local port, and a synchronization interface for communicating with a corresponding synchronization interface of at least one other transparent clock adaptor. The adaptor can operate both as an ingress adaptor for packets arriving over the network link for delivery to the network device and as an egress adaptor for packets arriving from the network device for delivery over the network link. | 05-03-2012 |