Patent application number | Description | Published |
20080268053 | COLLAGEN CARRIER OF THERAPEUTIC GENETIC MATERIAL, AND METHOD - A collagen matrix material is charged with a cell growth-promoting derived nucleic acid sequence. The nucleic acid sequence-charged collagen matrix material may be utilized in a method of promoting regeneration of surface cartilage of a joint. In the method, an area of injury is covered with the nucleic acid sequence-charged collagen matrix material, the collagen matrix material is fixed over the area to be treated, and the area is allowed to heal. | 10-30-2008 |
20080281432 | Method and Device For Synovial Cell-Charged Collagen Membrane or Gel - An implant for repair of a cartilaginous defect in a subject includes a collagen matrix charged with synovial cells. A method preparing an implant for repair of a cartilaginous defect in a subject includes obtaining a fluid containing synovial cells and charging the synovial cells to the matrix. A device for preparing a cell-charged implant includes a first chamber and a second chamber, the first and second chambers being separated by a membrane and a perforated filter. The membrane is adapted to collect cells from a cell-containing fluid introduced into the first chamber and the perforated filter is adapted to permit passage or diffusion of the fluid through the second chamber. A method for preparing a cell-charged implant utilizes the device. | 11-13-2008 |
20090186062 | Method of Repairing Meniscal Tears - A method of repairing a meniscal tear of a subject includes providing a sheet of collagen membrane material having on one side thereof a smooth barrier face which inhibits cell adhesion thereon and inhibits passage of cells therethrough. The sheet has a fibrous face opposite the smooth barrier face, the fibrous face allowing cell growth thereon. The collagen is predominantly collagen I. The sheet of collagen membrane material is fixed over a meniscal tear so that the fibrous face is oriented toward the meniscal tear. | 07-23-2009 |
20110270394 | METHOD AND MEMBRANE FOR SKIN REGENERATION - Skin regeneration or grafting is promoted utilizing a structure including a multi-layer sheet of collagen membrane material which includes a purified collagen barrier sheet material derived from natural collagen-containing tissue, the barrier sheet material including a barrier layer with an outer smooth barrier face and a fibrous face opposite the smooth barrier face. The structure further includes a matrix layer of collagen sponge material adjacent to the fibrous face. The matrix layer of collagen sponge material is resorbed by a body of a subject at a substantially faster rate than the barrier sheet material. | 11-03-2011 |
20110274756 | METHOD AND MEMBRANE FOR TISSUE REGENERATION - Tissue regeneration or grafting is promoted utilizing a structure including a multi-layer sheet of collagen membrane material which includes a purified collagen barrier sheet material derived from natural collagen-containing tissue, the barrier sheet material including a barrier layer with an outer smooth barrier face and a fibrous face opposite the smooth barrier face. The structure further includes a matrix layer of collagen sponge material adjacent to the fibrous face. The matrix layer of collagen sponge material is resorbed by a body of a subject at a substantially faster rate than the barrier sheet material. | 11-10-2011 |
20130011463 | METHOD AND DEVICE FOR SYNOVIAL CELL-CHARGED COLLAGEN MEMBRANE OR GEL - An implant for repair of a cartilaginous defect in a subject includes a collagen matrix charged with synovial cells. A method preparing an implant for repair of a cartilaginous defect in a subject includes obtaining a fluid containing synovial cells and charging the synovial cells to the matrix. A device for preparing a cell-charged implant includes a first chamber and a second chamber, the first and second chambers being separated by a membrane and a perforated filter. The membrane is adapted to collect cells from a cell-containing fluid introduced into the first chamber and the perforated filter is adapted to permit passage or diffusion of the fluid through the second chamber. A method for preparing a cell-charged implant utilizes the device. | 01-10-2013 |
Patent application number | Description | Published |
20130230956 | Trench Electrode Arrangement - A method includes forming a trench extending from a first surface of a semiconductor body into the semiconductor body such that a first trench section and at least one second trench section adjoin the first trench section, wherein the first trench section is wider than the second trench section. A first electrode is formed, in the at least one second trench section, and dielectrically insulated from semiconductor regions of the semiconductor body by a first dielectric layer. An inter-electrode dielectric layer is formed, in the at least one second trench section, on the first electrode. A second electrode is formed, in the at least one second trench section on the inter-electrode dielectric layer, and in the first trench section, such that the second electrode at least in the first trench section is dielectrically insulated from the semiconductor body by a second dielectric layer. | 09-05-2013 |
20140084362 | Semiconductor Device and Method for Manufacturing a Semiconductor Device - A semiconductor device includes a transistor including a source region, a drain region, and a gate electrode. The gate electrode is disposed in a first trench arranged in a top surface of the semiconductor substrate. The device further includes a control electrode. The control electrode is disposed in a second trench arranged in the top surface of the semiconductor substrate. The second trench has a second shape that is different from a first shape of the first trench. | 03-27-2014 |
20140117438 | Semiconductor Device and Method for Manufacturing a Semiconductor Device - A semiconductor device is at least partially formed in a semiconductor substrate, the substrate including first and second opposing main surfaces. The semiconductor device includes a cell field portion and a contact area, the contact area being electrically coupled to the cell field portion, the cell field portion including at least a transistor. The contact area includes a connection substrate portion insulated from other substrate portions and including a part of the semiconductor substrate, an electrode adjacent to the second main surface and in contact with the connection substrate portion, and a metal layer disposed over the first main surface, the connection substrate portion being electrically coupled to the metal layer to form an ohmic contact between the electrode and metal layer. The connection substrate portion is not electrically coupled to a component of the cell field portion by a conductive material disposed between the first and second main surfaces. | 05-01-2014 |
20140151758 | Semiconductor Device and Method of Manufacturing a Semiconductor Device - A semiconductor device includes a transistor, formed in a semiconductor substrate having a first main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, and a gate electrode being adjacent to the channel region, the gate electrode configured to control a conductivity of a channel formed in the channel region. The channel region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The channel region has a shape of a ridge extending along the first direction and the drift zone including a superjunction layer stack. | 06-05-2014 |
20140151798 | Semiconductor Device and Method of Manufacturing a Semiconductor Device - A semiconductor device comprises a transistor formed in a semiconductor substrate having a first main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, and a gate electrode being adjacent to the channel region. The gate electrode is configured to control a conductivity of a channel formed in the channel region, the channel region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The channel region has a shape of a first ridge extending along the first direction, and the transistor includes a first field plate arranged adjacent to the drift zone. | 06-05-2014 |
20140264580 | Semiconductor Device, Integrated Circuit and Method of Manufacturing a Semiconductor Device - A semiconductor device comprises a transistor. The transistor includes a source region, a drain region, a body region, a drift zone, and a gate electrode being adjacent to the body region. The body region, the drift zone, the source region and the drain region are disposed in a first semiconductor layer having a first main surface. The body region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The transistor further comprises a drift control region arranged adjacent to the drift zone, the drift control region being disposed over the first main surface. | 09-18-2014 |
20140312417 | Semiconductor Device and Method of Manufacturing a Semiconductor Device - A semiconductor device formed in a semiconductor substrate includes an isolation trench in the semiconductor substrate to laterally insulate adjacent components of the semiconductor device. A lateral isolation layer is disposed in the isolation trench. The semiconductor device further includes a source region and a drain region, and a body region and a drift region disposed between the source region and the drain region. The semiconductor device additionally includes a gate electrode adjacent to at least a portion of the body region and a field plate adjacent to at least a portion of the drift region. A field dielectric layer is disposed between the drift region and the field plate. A top surface of the field dielectric layer is disposed at a greater height measured from a first main surface of the semiconductor substrate than a top surface of the lateral isolation layer. | 10-23-2014 |
20140339633 | Semiconductor Device, Integrated Circuit and Method of Manufacturing a Semiconductor Device - A semiconductor device includes a transistor. The transistor includes a source region, a drain region, a body region, a drift zone, and a gate electrode adjacent to the body region. The body region, the drift zone, the source region and the drain region are disposed in a first semiconductor layer having a first main surface. The body region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. Trenches are disposed in the first semiconductor layer, the trenches extending in the first direction. The transistor further includes a drift control region arranged adjacent to the drift zone. The drift control region and the gate electrode are disposed in the trenches. | 11-20-2014 |
20140346590 | Semiconductor Device, Method of Manufacturing a Semiconductor Device and Integrated Circuit - A semiconductor device formed in a semiconductor substrate includes a source region, a drain region, a gate electrode, and a body region disposed between the source region and the drain region. The gate electrode is disposed adjacent at least two sides of the body region, and the source region and the gate electrode are coupled to a source terminal. A width of the body region between the two sides of the body region is selected so that the body region is configured to be fully depleted. | 11-27-2014 |
20150028408 | Integrated Circuit and Method of Manufacturing an Integrated Circuit - An integrated circuit is formed in a semiconductor substrate. The integrated circuit includes a trench formed in a first main surface of the semiconductor substrate. The trench includes a first trench portion and a second trench portion. The first trench portion is connected with the second trench portion. Openings of the first and second trench portions are adjacent to the first main surface. The integrated circuit further includes a trench transistor structure including a gate electrode disposed in the first trench portion, and a trench capacitor structure including a capacitor dielectric and a first capacitor electrode. The capacitor dielectric and the first capacitor electrode are disposed in the second trench portion. The first capacitor electrode includes a layer conformal with a sidewall of the second trench portion. | 01-29-2015 |
20150076590 | Semiconductor Device, Integrated Circuit and Method of Manufacturing a Semiconductor Device - A semiconductor device includes a transistor in a semiconductor substrate having a first main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, and a gate electrode adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the first main surface, between the source region and the drain region. The semiconductor device further includes a conductive layer beneath the gate electrode and insulated from the gate electrode. | 03-19-2015 |
20150311317 | Method of Manufacturing a Semiconductor Device - A method of manufacturing a semiconductor device includes forming a transistor in a semiconductor substrate having a first main surface. The transistor is formed by forming a source region, forming a drain region, forming a channel region, forming a drift zone, and forming a gate electrode adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the first main surface, between the source region and the drain region. Forming the semiconductor device further includes forming a conductive layer, a portion of the conductive layer being disposed beneath the gate electrode and insulated from the gate electrode. | 10-29-2015 |
20150333058 | Semiconductor Device in a Semiconductor Substrate and Method of Manufacturing a Semiconductor Device in a Semiconductor Substrate - A semiconductor device in a semiconductor substrate includes a trench in a first main surface of the semiconductor substrate. The trench includes a first trench portion extending in a first direction and a second trench portion extending in the first direction. The first trench portion is connected with the second trench portion in a lateral direction. The first trench portion and the second trench portion are arranged one after the other along the first direction. The semiconductor device further includes a trench conductive structure having a conductive material disposed in the first trench portion, and a trench capacitor structure having a capacitor dielectric and a first capacitor electrode disposed in the second trench portion. The first capacitor electrode includes a layer lining a sidewall of the second trench portion. | 11-19-2015 |
20160093529 | Method of Manufacturing a Semiconductor Device Having a Cell Field Portion and a Contact Area - A semiconductor device is manufactured at least partially in a semiconductor substrate. The substrate has first and second opposing main surfaces. The method includes forming a cell field portion and a contact area, the contact area being electrically coupled to the cell field portion, and forming the cell field portion by at least forming a transistor. The method further includes insulating a part of the semiconductor substrate from other substrate portions to form a connection substrate portion, forming an electrode adjacent to the second main surface so as to be in contact with the connection substrate portion, forming an insulating layer over the first main surface, forming a metal layer over the insulating layer, forming a trench in the first main surface, and filling the trench with a conductive material, and electrically coupling the connection substrate portion to the metal layer via the trench. | 03-31-2016 |
Patent application number | Description | Published |
20150091083 | Semiconductor Device and Method of Manufacturing a Semiconductor Device with Lateral FET Cells and Field Plates - A method of manufacturing a semiconductor device includes providing dielectric stripe structures extending from a first surface into a semiconductor substrate between semiconductor fins. A first mask is provided that covers a first area including first stripe sections of the dielectric stripe structures and first fin sections of the semiconductor fins. The first mask exposes a second area including second stripe and second fin sections. A channel/body zone is formed in the second fin sections by introducing impurities, wherein the first mask is used as an implant mask. Using an etch mask that is based on the first mask, recess grooves are formed at least in the second stripe sections. | 04-02-2015 |
20150091088 | Integrated Circuit and Method of Manufacturing an Integrated Circuit - An integrated circuit includes a transistor in a semiconductor substrate having a main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, a gate electrode, and a gate dielectric adjacent to the gate electrode. The gate electrode is disposed adjacent to at least two sides of the channel region. The channel region and the drift zone are disposed along a first direction parallel to the main surface between the source region and the drain region. The gate dielectric has a thickness that varies at different positions of the gate electrode. | 04-02-2015 |
20150102404 | Semiconductor Device - A semiconductor device includes a transistor formed in a semiconductor substrate including a main surface. The transistor includes a source region, a drain region, a channel region, and a gate electrode. The source region and the drain region are disposed along a first direction, the first direction being parallel to the main surface. The channel region has a shape of a ridge extending along the first direction, the ridge including a top side and a first and a second sidewalls. The gate electrode is disposed at the first sidewall of the channel region, and the gate electrode is absent from the second sidewall of the channel region. | 04-16-2015 |
20150137226 | Semiconductor Device and Method for Producing a Semiconductor Device - A semiconductor device includes a semiconductor substrate having first regions of a first conductivity type and body regions of the first conductivity type, which are arranged in a manner adjoining the first region and overlap the latter in each case on a side of the first region which faces a first surface of the semiconductor substrate, and having a multiplicity of drift zone regions arranged between the first regions and composed of a semiconductor material of a second conductivity type, which is different than the first conductivity type. The first regions and the drift zone regions are arranged alternately and form a superjunction structure. The semiconductor device further includes a gate electrode formed in a trench in the semiconductor substrate. | 05-21-2015 |
20150145074 | MEMS Device - A MEMS device includes a fixed electrode and a movable electrode arranged isolated and spaced from the fixed electrode by a distance. The movable electrode is suspended against the fixed electrode by one or more spacers including an insulating material, wherein the movable electrode is laterally affixed to the one or more spacers. | 05-28-2015 |
20160052776 | MEMS DEVICE - A MEMS device includes a fixed electrode and a movable electrode arranged isolated and spaced from the fixed electrode by a distance. The movable electrode is suspended against the fixed electrode by one or more spacers including an insulating material, wherein the movable electrode is laterally affixed to the one or more spacers. | 02-25-2016 |
20160060105 | MEMS DEVICE AND METHOD FOR MANUFACTURING A MEMS DEVICE - A method for producing a MEMS device comprises forming a semiconductor layer stack, the semiconductor layer stack comprising at least a first monocrystalline semiconductor layer, a second monocrystalline semiconductor layer and a third monocrystalline semiconductor layer, the second monocrystalline semiconductor layer formed between the first and third monocrystalline semiconductor layers. A semiconductor material of the second monocrystalline semiconductor layer is different from semiconductor materials of the first and third monocrystalline semiconductor layers. After forming the semiconductor layer stack, at least a portion of each of the first and third monocrystalline semiconductor layers is concurrently etched. | 03-03-2016 |
Patent application number | Description | Published |
20080205118 | INTEGRATED CIRCUIT HAVING A RESISTIVE SWITCHING DEVICE - An integrated circuit, a memory cell, memory device and method of operating the memory device is disclosed. In one embodiment, an integrated circuit having a resistively switching memory cell includes a bitline electrode and a second electrode having a lower voltage potential than the bitline electrode; a switching active volume and a selection transistor connected in series between the bitline electrode and the second electrode. The second electrode is connected, via a connection transistor, to a third electrode having the same or a lower voltage potential than the second electrode; wherein the second electrode includes a buried electrode at least partially positioned below the bitline electrode and the third electrode. | 08-28-2008 |
20080217655 | INTEGRATED CIRCUIT WITH BURIED CONTROL LINE STRUCTURES - An integrated circuit with buried control line structures. In one embodiment, the control lines are subdivided into sections, wherein regions free of switching transistors are provided at intervals along the control lines. Connections for feeding the control potentials into the sections of the control lines are provided at least in a subset of the regions free of switching transistors. The isolations lines are connected to one another by an interconnect running transversely with respect to the control lines. | 09-11-2008 |
20080217672 | INTEGRATED CIRCUIT HAVING A MEMORY - An integrated circuit having a memory arrangement including capacitor elements and further capacitor elements is disclosed. One embodiment provides a substrate layer with contact pads and further contact pads; the capacitor elements being disposed in a first level on the substrate layer and connected with the contact pads; the further capacitor elements being disposed in a second level above the first level; contact elements being disposed between the capacitor elements and connected with the further contact pads; the further capacitor elements being disposed above the contact elements and being connected with the contact elements. | 09-11-2008 |
20080253160 | INTEGRATED CIRCUIT HAVING A MEMORY CELL ARRAY AND METHOD OF FORMING AN INTEGRATED CIRCUIT - An integrated circuit having a memory cell array and a method of forming an integrated circuit is disclosed. One embodiment provides bitlines running along a first direction, wordlines running along a second direction substantially perpendicular to the first direction, active areas and bitline contacts. The bitline contacts are arranged in columns extending in the second direction and in rows extending in the first direction. A distance between neighboring bitlines is DL, and a distance between neighboring bitline contacts is DC, DC being measured parallel to the first direction. The following relation holds: 1/2.25≦DL/DC≦1/1.75. | 10-16-2008 |
20090296449 | Integrated Circuit and Method of Operating an Integrated Circuit - According to one embodiment of the present invention, an integrated circuit is provided including a plurality of resistivity changing memory elements and a plurality of memory element select devices, wherein the select devices are floating body select devices. | 12-03-2009 |
20100096669 | MEMORY CELL ARRAY COMPRISING WIGGLED BIT LINES - An integrated circuit including a memory cell array comprises transistors being arranged along parallel active area lines, bitlines, the bitlines being arranged so that an individual one intersects a plurality of the active area lines to form bitline-contacts, respectively, the bitlines being formed as wiggled lines, wordlines being arranged so that an individual one of the wordlines intersects a plurality of the active area lines, and an individual one of the wordlines intersects a plurality of the bitlines, wherein neighboring bitline-contacts, each of which is connected to one of the active area lines, are connected with different bitlines. | 04-22-2010 |
20100097835 | 4 F2 MEMORY CELL ARRAY - An integrated circuit including a memory cell array comprises active area lines, bitlines, the bitlines being arranged so that an individual one intersects a plurality of the active area lines to form bitline-contacts, respectively, the bitlines being arranged at a bitline pitch, wordlines being arranged so that an individual one of the wordlines intersects a plurality of the active area lines, and an individual one of the wordlines intersects a plurality of the bitlines, the wordlines being arranged at a wordline pitch, wherein neighboring bitline-contacts, each of which is connected to one of the active area lines, are connected with different bitlines, and the bitline pitch is different from the wordline pitch. | 04-22-2010 |
20120211837 | SEMICONDUCTOR DEVICE COMPRISING SELF-ALIGNED CONTACT ELEMENTS - When forming sophisticated semiconductor devices, a replacement gate approach may be applied in combination with a self-aligned contact regime by forming the self-aligned contacts prior to replacing the placeholder material of the gate electrode structures. | 08-23-2012 |
20120211844 | Semiconductor Device Comprising Self-Aligned Contact Elements and a Replacement Gate Electrode Structure - When forming sophisticated semiconductor devices including high-k metal gate electrode structures, a raised drain and source configuration may be used for controlling the height upon performing a replacement gate approach, thereby providing superior conditions for forming contact elements and also obtaining a well-controllable reduced gate height. | 08-23-2012 |
20120217612 | VERTICAL FLOATING BODY STORAGE TRANSISTORS FORMED IN BULK DEVICES AND HAVING BURIED SENSE AND WORD LINES - A semiconductor device comprises a memory area including floating body transistors in the form of pillar structures, which are formed in a bulk architecture. The pillar structures may be appropriately addressed on the basis of a buried word line and a buried sense region or sense lines in combination with an appropriate bit line contact regime. | 08-30-2012 |
20120223412 | Semiconductor Device Comprising a Capacitor Formed in the Metallization System Based on Dummy Metal Features - When forming capacitive structures in a metallization system, such as in a dynamic RAM area, placeholder metal regions may be formed together with “regular” metal features, thereby achieving a very efficient overall process flow. At a certain manufacturing stage, the metal of the placeholder metal region may be removed on the basis of a wet chemical etch recipe followed by the deposition of the electrode materials and the dielectric materials for the capacitive structure without unduly affecting other portions of the metallization system. In this manner, very high capacitance values may be realized on the basis of a very efficient overall manufacturing flow. | 09-06-2012 |
20120280296 | Semiconductor Device with DRAM Bit Lines Made From Same Material as Gate Electrodes in Non-Memory Regions of the Device, and Methods of Making Same - Generally, the present disclosure is directed to a semiconductor device with DRAM bit lines made from the same material as the gate electrodes in non-memory regions of the device, and methods of making the same. One illustrative method disclosed herein comprises forming a semiconductor device including a memory array and a logic region. The method further comprises forming a buried word line in the memory array and, after forming the buried word line, performing a first common process operation to form at least a portion of a conductive gate electrode in the logic region and to form at least a portion of a conductive bit line in the memory array. | 11-08-2012 |
20120313187 | Method of Removing Gate Cap Materials While Protecting Active Area - Disclosed herein is a method of forming a semiconductor device. In one example, the method includes forming a gate electrode structure above a semiconducting substrate, wherein the gate electrode structure includes a gate insulation layer, a gate electrode, a first sidewall spacer positioned proximate the gate electrode, and a gate cap layer, and forming an etch stop layer above the gate cap layer and above the substrate proximate the gate electrode structure. The method further includes forming a layer of spacer material above the etch stop layer, and performing at least one first planarization process to remove the portion of said layer of spacer material positioned above the gate electrode, the portion of the etch stop layer positioned above the gate electrode and the gate cap layer. | 12-13-2012 |
20120322225 | Method of Forming Conductive Contacts on a Semiconductor Device with Embedded Memory and the Resulting Device - A method is disclosed that includes forming a conductive logic contact in a logic area of a semiconductor device, forming a bit line contact and a capacitor contact in a memory array of the semiconductor device, and performing at least one first common process to form a first metallization layer comprising a first conductive line in the logic area that is conductively coupled to the conductive logic contact and a bit line in the memory array that is conductively coupled to the bit line contact. The method further includes performing at least one second common process to form a second metallization layer comprising a first conductive structure conductively coupled to the first conductive line in the logic area and a second conductive structure in the memory array that that is conductively coupled to the capacitor contact. | 12-20-2012 |
20130020656 | HIGH PERFORMANCE HKMG STACK FOR GATE FIRST INTEGRATION - Semiconductor devices are formed with a silicide interface between the work function layer and polycrystalline silicon. Embodiments include forming a high-k/metal gate stack by: forming a high-k dielectric layer on a substrate, forming a work function metal layer on the high-k dielectric layer, forming a silicide on the work function metal layer, and forming a poly Si layer on the silicide. Embodiments include forming the silicide by: forming a reactive metal layer in situ on the work function layer, forming an a-Si layer in situ on the entire upper surface of the reactive metal layer, and annealing concurrently with forming the poly Si Layer. | 01-24-2013 |
20130270619 | SEMICONDUCTOR DEVICE COMPRISING FERROELECTRIC ELEMENTS AND FAST HIGH-K METAL GATE TRANSISTORS - Ferroelectric circuit elements, such as field effect transistors or capacitors, may be formed on the basis of hafnium oxide, which may also be used during the fabrication of sophisticated high-k metal gate electrode structures of fast transistors. To this end, the hafnium-based oxide having appropriate thickness and material composition may be patterned at any appropriate manufacturing stage, without unduly affecting the overall process flow for fabricating a sophisticated high-k metal gate electrode structure. | 10-17-2013 |
20140203339 | SEMICONDUCTOR DEVICE COMPRISING SELF-ALIGNED CONTACT ELEMENTS AND A REPLACEMENT GATE ELECTRODE STRUCTURE - A semiconductor device includes a high-k metal gate electrode structure that is positioned above an active region, has a top surface that is positioned at a gate height level, and includes a high-k dielectric material and an electrode metal. Raised drain and source regions are positioned laterally adjacent to the high-k metal gate electrode structure and connect to the active region, and a top surface of each of the raised drain and source regions is positioned at a contact height level that is below the gate height level. An etch stop layer is positioned above the top surface of the raised drain and source regions and a contact element connects to one of the raised drain and source regions, the contact element extending through the etch stop layer and a dielectric material positioned above the high-k metal gate electrode structure and the raised drain and source regions. | 07-24-2014 |
20150228656 | REPLACEMENT GATE COMPATIBLE eDRAM TRANSISTOR WITH RECESSED CHANNEL - An eDRAM is fabricated including high performance logic transistor technology and ultra low leakage DRAM transistor technology. Embodiments include forming a recessed channel in a substrate, forming a first gate oxide to a first thickness lining the channel and a second gate oxide to a second thickness over a portion of an upper surface of the substrate, forming a first polysilicon gate in the recessed channel and overlying the recessed channel, forming a second polysilicon gate on the second gate oxide, forming spacers on opposite sides of each of the first and second polysilicon gates, removing the first and second polysilicon gates forming first and second cavities, forming a high-k dielectric layer on the first and second gate oxides, and forming first and second metal gates in the first and second cavities, respectively. | 08-13-2015 |