Patent application number | Description | Published |
20080296714 | Wafer level package of image sensor and method for manufacturing the same - Provided is a wafer level package of an image sensor capable of simply and easily packaging an image sensor in a packaging process, and a method for manufacturing the same. The wafer level package of an image sensor includes a lower substrate including an image sensor, a conductive pattern coupled to the image sensor, and a plurality of vias coupled to the conductive pattern; a micro lens array film having a plurality of micro lenses corresponding to the image sensor, the micro lenses being formed on the lower substrate; and a sealing line surrounding the image sensor while being spaced apart from the image sensor and being in contact with an upper substrate. The wafer level package may be useful to have an electrical connection structure using vias without any need to a bonding wire, an electrode pad and an electrode lead in the conventional wafer level package since a packaging process is carried out by bonding a wafer for an upper substrate with a plurality of the vias being provided in a wafer for a lower substrate | 12-04-2008 |
20080308950 | Semiconductor package and method for manufacturing thereof - A semiconductor package, which includes: a first substrate, on which a pre-designed pattern is formed; a first chip, mounted by a flip chip method on one side of the first substrate; a first molding, covering the first substrate and the first chip; a first via, which penetrates the first molding, and which is electrically connected with the pattern formed on the first substrate; an interposer, which is placed on the first molding, and on both sides of which a pre-designed pattern is formed respectively; a second via, penetrating the interposer and electrically connecting both sides of the interposer; a second substrate, placed on the interposer with at least one conductive ball positioned in-between, such that the second substrate is electrically connected with the pattern formed on the interposer; and a second chip mounted on the second substrate, can be used to improve heat release and increase the degree of integration. | 12-18-2008 |
20090045441 | CMOS image sensor package - A CMOS image sensor package is disclosed. The CMOS image sensor package includes: a substrate, on which a pre-designed circuit pattern is formed, and in which a cavity is formed; a pixel array sensor, which is electrically connected with the circuit pattern and stacked on one side of the substrate; and a control chip, which is electrically connected with the circuit pattern and held within the cavity. According to certain aspects of the invention, the CMOS image sensor chip can be separated into the pixel array sensor and the control chip, with the control chip and passive components embedded in cavities formed in the substrate, so that the size of the chip mounted on the substrate may be reduced, and consequently the overall size of the CMOS image sensor package may be reduced. | 02-19-2009 |
20090046409 | Capacitor-embedded printed circuit board and manufacturing method thereof - A capacitor-embedded printed circuit board and a method of manufacturing the printed circuit board are disclosed. The capacitor-embedded printed circuit board includes: an insulation layer, a first electrode formed on one side of the insulation layer, a second electrode formed on one side of the first electrode, a dielectric layer formed on one side of the second electrode, and a third electrode formed on one side of the dielectric layer. By forming the electrodes of the capacitor in a dual structure, deviations in contact area may be minimized between the second electrode and the dielectric layer, so that ultimately, errors in capacitance may be reduced. | 02-19-2009 |
20090071705 | Printed circuit board having embedded components and method for manufacturing thereof - A PCB (printed circuit board) having embedded components and a method for manufacturing thereof are disclosed. The PCB may include a dielectric substrate having a cavity formed in one side, a first component inserted in the cavity such that an electrode of the first component faces the one side of the dielectric substrate, a second component mounted on one side of the first component such that an electrode of the second component faces the same direction as the electrode of the first component, a first dielectric layer formed on one side of the dielectric substrate such that the first dielectric layer covers the second component, and a second dielectric layer formed on the other side of the dielectric substrate such that the second dielectric layer covers the first component. In this PCB, multiple components of differing thickness can be mounted, and vias can be formed more easily. | 03-19-2009 |
20090073667 | Semiconductor chip package and printed circuit board - A semiconductor chip package and a printed circuit board having an embedded semiconductor chip package are disclosed. The semiconductor chip package may include a semiconductor chip that has at least one chip pad formed on one side, and a capacitor formed on the other side of the semiconductor chip. | 03-19-2009 |
20090087951 | Method of manufacturing wafer level package - A method of manufacturing a wafer level package is disclosed. The method may include stacking an insulation layer over a wafer substrate; processing a via hole in the insulation layer; forming a seed layer over the insulation layer; forming a plating resist, which is in a corresponding relationship with a redistribution pattern, over the seed layer; forming the redistribution pattern, which includes a terminal for external contact, by electroplating; and coupling a conductive ball to the terminal. As multiple redistribution layers can be formed using inexpensive PCB processes, the manufacturing costs can be reduced, and the stability and efficiency of the process can be increased. | 04-02-2009 |
20090124043 | Method of manufacturing a package board - A method of manufacturing a package board is disclosed. The method is for manufacturing a package board that has a pad electrically connected with a component, and includes: forming an indentation, which is in correspondence with the pad, in one side of a first insulating layer; filling a metal paste in the indentation; mounting the component on the first insulating layer in correspondence with a location of the indentation; and hardening the metal paste. Using this method, damage to the component can be prevented during the forming of vias, as the component is mounted after filling paste in an indentation formed in an insulating layer. | 05-14-2009 |
20090124075 | Method of manufacturing a wafer level package - A method of manufacturing a wafer level package is disclosed, which may include: coating an insulation layer over one side of a semiconductor chip, on one side of which an electrode pad is formed, such that the electrode pad is open; forming a seed layer by depositing a conductive metal onto one side of the semiconductor chip; forming a rewiring pattern that is electrically connected with the electrode pad, by selective electroplating with the seed layer as an electrode; forming a conductive pillar that is electrically connected with the rewiring pattern, by selective electroplating with the seed layer as an electrode; and removing portions of the seed layer open to the exterior. By forming the rewiring pattern and the metal pillar using one seed layer, the manufacturing process can be simplified, whereby defects during the manufacturing process can be reduced and the reliability of the products can be improved. | 05-14-2009 |
20090166859 | Semiconductor device and method of manufacturing the same - Provided is a semiconductor device including a wafer having an electrode pad; an insulating layer that is formed on the wafer and has an exposure hole formed in one side thereof, the exposure layer exposing the electrode pad, and a support post formed in the other side, the support post having a buffer groove; a redistribution layer that is formed on the top surface of the insulating layer and has one end connected to the electrode pad and the other end extending to the support post; an encapsulation layer that is formed on the redistribution layer and the insulating layer and exposes the redistribution layer formed on the support post; and a solder bump that is provided on the exposed portion of the redistribution layer. | 07-02-2009 |
20090166862 | Semiconductor device and method of manufacturing the same - Provided is a semiconductor device including a wafer having an electrode pad; an insulation layer that is formed on the wafer and has an exposure hole exposing the electrode pad; a redistribution layer that is formed on the insulation layer and the exposure hole of the insulation layer and has one end connected to the electrode pad; a conductive post that is formed at the other end of the redistribution layer; an encapsulation layer that is formed on the redistribution layer and the insulation layer such that the upper end portion of the conductive post is exposed; and a solder bump that is formed on the exposed upper portion of the conducive post. | 07-02-2009 |
20090244864 | Substrate for capacitor-embedded printed circuit board, capacitor-embedded printed circuit board and manufacturing method thereof - Disclosed are a substrate for a capacitor-embedded printed circuit board, a capacitor-embedded printed circuit board, and a manufacturing method thereof. The capacitor-embedded printed circuit board can include a core board, an insulation resin layer, which is stacked on the core board, a first electrode and a first circuit pattern, which are buried in the insulation resin layer, a dielectric layer, which is stacked on a surface of the insulation resin layer, a first adhesive resin layer, which is stacked on the dielectric layer, and a second electrode and a second circuit pattern, which are formed on a surface of the first adhesive resin layer to correspond with the first electrode. With the present invention, the manufacturing process can be simplified and the reliability of products can be improved by reducing the variation of the capacitor (C). | 10-01-2009 |
20090253259 | Solder ball attachment jig and method for manufacturing semiconductor device using the same - Disclosed are a solder attachment jig and a method of manufacturing a semiconductor device using the same. The solder ball attachment jig, which arranges a solder ball to be aligned with a conductive post of a semiconductor wafer, can include a body and a receiving hole, which is formed on the body to hold the solder ball. Internal walls of the receiving hole that face each other are symmetrically inclined. Using the solder ball attachment jig in accordance with an embodiment of the present invention, the alignment of the solder ball can be improved while reducing the cost and simplifying the processes. | 10-08-2009 |
20090309216 | WAFER LEVEL PACKAGE AND MANUFACTURING METHOD THEREOF - A wafer level package and a manufacturing method thereof capable of reducing stress between an under bump metal and a bump. The wafer level package includes a substrate provided with a plurality of chip pads on a top surface; a first passivation layer to expose the chip pads; vias connected to the chip pads by passing through the first passivation layer; a metal wiring layer formed on the first passivation layer and connected to the vias; an under bump metal formed on the first passivation layer to be connected to the metal wiring layer and having a buffer pattern separated through a trench on a center; a second passivation layer formed on the first passivation layer to expose the under bump metal; a first bump formed on the buffer pattern; and a second bump filling the trench and formed on the first bump and the under bump metal. | 12-17-2009 |
20100084754 | Semiconductor package - A semiconductor package which includes a first substrate having a pre-designed pattern formed thereon; a first chip mounted by a flip chip method on one side of the first substrate; a support formed to a predetermined thickness on an edge of the first substrate; an interposer having an edge thereof placed on the support, such that the interposer covers the first substrate and forms a cavity between the interposer and the first substrate, and having a pre-designed pattern formed respectively on both sides thereof; a via penetrating the support and the interposer; a second chip mounted on one side of the interposer facing the first substrate; a second substrate placed on the other side of the interposer with at least one conductive ball positioned in-between; and a third chip mounted on the second substrate. | 04-08-2010 |
20100087034 | Method of manufacturing a semicondictor package - A method of manufacturing a semiconductor package which includes mounting a first chip on a first substrate by a flip chip method, the first substrate having a pre-designed pattern formed thereon; forming a cavity by etching a center portion of a metal oxide layer; mounting a second chip inside the cavity; forming at least one via such that the via penetrates an edge of the metal oxide layer; placing the metal oxide layer on the first substrate such that the second chip and the first chip face each other; and placing a second substrate on the metal oxide layer, the second substrate having a third chip mounted thereon. | 04-08-2010 |
20100087035 | Method for manufacturing a semiconductor package - A method of manufacturing a semiconductor package which includes mounting a first chip on a first substrate by a flip chip method, the first substrate having a pre-designed pattern formed thereon; forming at least one bump by performing soldering, on at least one predetermined position electrically connected with the pattern formed on the first substrate; forming a first molding by performing molding, such that the first molding covers the first substrate and the first chip; placing an interposer on the first molding; and placing a second substrate on the interposer, the second substrate having a second chip mounted thereon. | 04-08-2010 |
20100096749 | SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF - Disclosed are a semiconductor package and a manufacturing method thereof. The semiconductor package can include a semiconductor substrate, having one surface on which a conductive pad is formed; an insulating layer, being formed on one surface of the semiconductor substrate; a metal post, penetrating through the conductive pad, the semiconductor substrate, and the insulating layer; and an outer-layer circuit, being electrically connected to the metal post. With the present invention, it can become unnecessary to form an additional via for electrically connecting both surfaces of the semiconductor substrate, thereby simplifying the manufacturing process, reducing the manufacturing cost, and improving the coupling reliability. | 04-22-2010 |
20100102426 | Dual face package and method of manufacturing the same - Disclosed herein is a dual face package and a method of manufacturing the same. The dual face package includes a semiconductor substrate including a through-electrode connected to a die pad disposed on one side of the semiconductor substrate, and a lower redistribution layer disposed on another side thereof and connected to the through-electrode, an insulating layer including a post electrode connected to the through-electrode, and an upper redistribution layer disposed on one side thereof and connected to the post electrode, and an adhesive layer disposed on the one side of the semiconductor substrate so as to attach the insulating layer to the semiconductor substrate such that the through-electrode is connected to the post electrode. The dual face package is produced by a simple process and is applicable to a large diameter wafer level package. | 04-29-2010 |
20100117218 | Stacked wafer level package and method of manufacturing the same - The present invention relates to a stacked wafer level package and a method of manufacturing the same. The stacked wafer level package in accordance with the present invention can improve a misalignment problem generated in a stacking process by performing a semiconductor chip mounting process, a rearrangement wiring layer forming process, the stacking process and so on after previously bonding internal connection means for interconnection between stacked electronic components to a conductive layer for forming a rearrangement wiring layer, thereby improving reliability and yield and reducing manufacturing cost. | 05-13-2010 |
20100133680 | Wafer level package and method of manufacturing the same and method of reusing chip - The present invention relates to a wafer level package and a method of manufacturing the same and a method of reusing a chip and provides a wafer level package including a chip; a removable resin layer formed to surround side surfaces and a lower surface of the chip; a molding material formed on the lower surface of the removable resin layer; a dielectric layer formed over the removable resin layer including the chip and having via holes to expose portions of the chip; redistribution lines formed on the dielectric layer including insides of the via holes to be connected to the chip; and a solder resist layer formed on the dielectric layer to expose portions of the redistribution lines. Also, the present invention provides a method of manufacturing a wafer level package and a method of reusing a chip. | 06-03-2010 |
20100144152 | Method of manufacturing semiconductor package - The present invention relates to a method of manufacturing a semiconductor package capable of simplifying a process and remarkably reducing a production cost by including the steps of: preparing a different bonded panel including at least one metal layer; forming a pad unit electrically connected to the metal layer; mounting a semiconductor chip over the different bonded panel to be electrically connected to the pad unit; sealing the semiconductor chip; forming a rearrangement wiring layer by etching the metal layer; and forming an external connection unit electrically connected to the rearrangement wiring layer. | 06-10-2010 |
20100149770 | Semiconductor stack package - The present invention relates to a semiconductor stack package including: a printed circuit board; a first semiconductor chip mounted on the printed circuit board; a second semiconductor chip mounted on the printed circuit board in parallel with the first semiconductor chip; a first rearrangement wiring layer positioned on the first semiconductor chip; a second rearrangement wiring layer which constitutes one circuit together with the first rearrangement wiring layer and is positioned on the second semiconductor chip; and a third semiconductor chip which is electrically connected to the first and second rearrangement wiring layers and of which both ends are separately positioned on the first and second semiconductor chips. | 06-17-2010 |
20100159646 | Method of manufacturing wafer level package - The present invention relates to a method of manufacturing a wafer level package including the steps of: preparing a substrate wafer including a plurality of pads formed on a bottom surface, a plurality of chips positioned on a top surface, and dicing lines for dividing the chips; forming external connection units on the pads; coating resin on the dicing lines by positioning masks on the substrate wafer to expose only the dicing lines; removing the masks; encapsulating the chips positioned between the resin by coating the chips with encapsulant; removing the resin coated on the dicing lines; and cutting a wafer level package along the dicing lines exposed by removing the resin into units. | 06-24-2010 |
20100193932 | WAFER LEVEL PACKAGE FOR HEAT DISSIPATION AND METHOD OF MANUFACTURING THE SAME - Disclosed herein are a wafer level package for heat dissipation and a method of manufacturing the same. The wafer level package includes a heat dissipation plate including a cavity and a hole, a die including a pad disposed in the cavity of the heat dissipation plate in a face-up manner, a thermal conductive adhesive disposed between the die and an inner wall of the cavity and disposed in the hole, and a redistribution layer connected at one end to the pad and at the other end extended. The wafer level package protects the die from external environments and enables the die to be easily flush with the heat dissipation plate. | 08-05-2010 |
20100242272 | Method of manufacturing printed circuit board - A method of manufacturing a printed circuit board (PCB) having embedded components. The method includes: forming a cavity in one side of a dielectric substrate; inserting a first component in the cavity such that an electrode thereof faces the one side of the dielectric substrate; mounting a second component on one side of the first component such that an electrode thereof faces the same direction as the electrode of the first component; forming a first dielectric layer on one side of the dielectric substrate such that the first dielectric layer covers the second component; and forming a second dielectric layer on the other side of the dielectric substrate such that the second dielectric layer covers the first component. | 09-30-2010 |
20100320624 | DIE PACKAGE INCLUDING ENCAPSULATED DIE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a die package including an encapsulated die, including: a die including pads on one side thereof; an encapsulation layer covering lateral sides of the die; a support layer covering the encapsulation layer and one side of the die; a passivation layer formed on the other side of the die such that the pads are exposed therethrough; and a redistribution layer formed on the passivation layer such that one part thereof is connected with the pad. Here, since one side of the die is supported by the support layer and the encapsulation layer is formed on only the lateral side of the die, the warpage of the die package due to the difference in thermal expansion coefficient can be minimized. | 12-23-2010 |
20100327426 | Semiconductor chip package and method of manufacturing the same - Provided are a semiconductor chip package and a method of manufacturing the same. The semiconductor chip package includes a semiconductor chip including a first face having a chip pad, a second face facing the first face, and a side face connecting the first and second faces, a first lamination layer covering the second face and a portion of the side face, a second lamination layer disposed on a top surface of the first lamination layer and forming a gap having a predetermined distance from the side face, and a redistribution pattern disposed on the first face and electrically connected to the chip pad. The semiconductor package and the method of manufacturing the same achieve a high process yield and reliability. | 12-30-2010 |
20110042799 | DIE PACKAGE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein are a die package and a method of manufacturing the die package. A solder layer is formed on a lower surface of a die. The die is self-aligned and attached to a support plate using surface tension between the solder layer and a metal layer of the support plate, thus reducing attachment lead time of the die. | 02-24-2011 |
20110045668 | Method of manufacturing wafer level device package - There is provided a method of manufacturing a wafer level device package, the method including: forming a conductive pad on at least one area of a substrate; forming a first insulation layer on the substrate, the first insulation layer having an opening allowing the conductive pad to be exposed; forming a wiring layer connected to the conductive pad on the first insulation layer; forming a conductive diffusion barrier layer on the wiring layer to seal the wiring layer; forming a second insulation layer on the diffusion barrier layer, the second insulation layer having a contact hole allowing a part of diffusion barrier layer to be exposed; and forming a bump pad in the contact hole. This method allows for a reduction in processing time and costs by substituting a simple electroless plating process for a complicated photolithography process in the formation of the bump pad and the diffusion barrier layer. | 02-24-2011 |
20110048778 | Circuit board, semiconductor package and method of manufacturing the same - A circuit board includes a board part including a pattern portion on one surface thereof, the pattern portion being electrically connected to a semiconductor chip, and an under-fill layer disposed on the board part and exposing the pattern portion to the outside, the under-fill layer flowing to cover the pattern portion by heat generated in mounting the semiconductor chip. | 03-03-2011 |
20110061911 | Interposer and method for manufacturing the same - An interposer includes: an insulation plate where a via is formed, the insulation plate including a resin or a ceramic; a first upper redistribution layer electrically connected to the via along a circuit pattern designed on the top surface of the insulation plate; a first upper protection layer laminated to expose a portion of the first upper redistribution layer and protecting the first upper redistribution layer; a second upper redistribution layer electrically connected to the first upper redistribution layer and laminated along a designed circuit pattern designed; a second upper protection layer laminated to expose a portion of the second upper redistribution layer and protecting the second upper redistribution layer; and an under bump metallization (UBM) formed at the exposed portion of the second upper redistribution layer. | 03-17-2011 |
20110062533 | Device package substrate and method of manufacturing the same - A device package substrate includes: a substrate having a cavity formed on a top surface thereof, the cavity having a chip mounting region; a first interconnection layer formed to extend to the inside of the cavity; a second interconnection layer formed to be spaced apart from the first interconnection layer; a chip positioned in the chip mounting region so as to be connected to the first and second interconnection layers; an insulating layer formed to cover the first and second interconnection layers and the chip and having a contact hole exposing a part of the second interconnection layer; and a bump pad formed in the contact hole so as to be connected to external elements. | 03-17-2011 |
20110108993 | Semiconductor package and manufacturing method thereof - There is provided a semiconductor package including: a circuit board having a receiving space formed therein; a semiconductor chip inserted into the receiving space of the circuit board; and an electrode pattern portion having a pattern shape on one surface of the semiconductor chip, and directly contacting a via portion of the circuit board so as to be electrically connected thereto. | 05-12-2011 |
20110129994 | Method of manufacturing a dual face package - A method of manufacturing a dual face package, including: preparing an upper substrate composed of an insulating layer including a post via-hole; forming a filled electrode in a semiconductor substrate, the filled electrode being connected to a die pad; applying an adhesive layer on one side of the semiconductor substrate including the filled electrode, and attaching the upper substrate to the semiconductor substrate; cutting another side of the semiconductor substrate in a thickness direction, thus making the filled electrode into a through-electrode; and forming a post electrode in the post via-hole, forming an upper redistribution layer connected to the post electrode of the semiconductor substrate, and forming a lower redistribution layer connected to the through-electrode on the other side of the semiconductor substrate. | 06-02-2011 |
20110156241 | PACKAGE SUBSTRATE AND METHOD OF FABRICATING THE SAME - Disclosed herein are a package substrate and a method of fabricating the same. The package substrate includes a base part that includes a chip, a mold part surrounding the chip, and a connection unit formed inside the mold part to connect the chip to a terminal part formed on the outer surface of the mold part, and a buildup layer that is formed on one surface of the base part on which the terminal part is formed, including the side surfaces of the base part, but includes a circuit layer connected to the terminal part, thereby making it possible to minimize stress applied to chips during a buildup process and easily replace malfunctioning chips. | 06-30-2011 |
20110176285 | Interconnection structure, interposer, semiconductor package, and method of manufacturing interconnection structure - There is provided an interconnection structure. An interconnection structure according to an aspect of the invention may include: a plurality of side portions provided on one surface of a substrate part and a plurality of cavities located between the side portions and located further inward than the side portions; and electrode pattern portions provided on surfaces of the side portions and the cavities. | 07-21-2011 |
20110198749 | Semiconductor chip package and method of manufacturing the same - Provided are a semiconductor chip package and a method of manufacturing the same. The semiconductor chip package includes a semiconductor chip comprising a chip pad, and a rerouting layer disposed on the semiconductor chip and including a metal interconnection electrically connected to the chip pad and a partial oxidation region formed by the oxidation of metal and insulating the metal interconnection. | 08-18-2011 |
20110201156 | Method of manufacturing wafer level package including coating resin over the dicing lines - A method of manufacturing a wafer level package including: preparing a substrate wafer including a plurality of pads formed on a bottom surface, a plurality of chips positioned on a top surface, and dicing lines for dividing the chips; forming external connection units on the pads; coating resin on the dicing lines by positioning masks on the substrate wafer to expose only the dicing lines; removing the masks; encapsulating the chips positioned between the resin by coating the chips with encapsulant and cutting a wafer level package along the dicing lines coated with the resin into units. | 08-18-2011 |
20110248408 | Package substrate and fabricating method thereof - There are provided a package substrate and a method fabricating thereof. The package substrate includes: a wafer having a cavity formed in an upper surface thereof, the cavity including a chip mounting region; a first wiring layer and a second wiring layer formed to be spaced apart from the first wiring layer, which are formed to be extended in the cavity; a chip positioned in the chip mounting region to be connected to the first wiring layer and the second wiring layer; a through-hole penetrating through the wafer and a via filled in the through-hole; and at least one electronic device connected to the via. Accordingly, a package substrate capable of having a passive device having a predetermined capacity embedded therein, while reducing a pattern size and increasing a component mounting density, and a method fabricating thereof may be provided. | 10-13-2011 |
20110269413 | Circuit board and method for manufacturing the same - There are provided a circuit board and a method for manufacturing the same. The circuit board according to the present invention includes: a first wiring pattern that is formed on one surface of the board; a second wiring pattern that is formed on the other surface of the board; an RF transmitter that is formed on one surface of the board and is connected to the first wiring pattern; and an RF receiver that is formed on the other surface of the board to be paired with the RF transmitter and is connected to the second wiring pattern, wherein the first wiring pattern and the second wiring pattern are electrically connected to each other by wireless communication from the RF transmitter to the RF receiver. | 11-03-2011 |
20110273266 | Resistor having parallel structure and method of fabricating the same - There are provided a resistor and a method of fabricating the same. More particularly, there are provided a resistor having a parallel structure capable of easily implementing a resistance value when forming a resistor directly on a wafer during a wafer process, and a method of fabricating the same. | 11-10-2011 |
20110298102 | SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A semiconductor package and a method of manufacturing the semiconductor package are disclosed. A semiconductor package in accordance with an embodiment of the present invention includes a substrate, which is formed with a ground circuit and mounted with a semiconductor chip on one surface, a conductive ground layer, which is formed on the other surface of the substrate and connected with the ground circuit, a molding, which seals up the ground layer and the substrate having the semiconductor chip mounted thereon, and a conductive shield, which covers the molding and is connected with the ground layer. With a semiconductor package in accordance with an embodiment of the present invention, grounding for shielding is possible even in an entirely molded structure, and a double shielding structure to improve the shielding property. | 12-08-2011 |
20110309501 | SEMICONDUCTOR PACKAGE MODULE AND ELECTRIC CIRCUIT ASSEMBLY WITH THE SAME - Disclosed herein is a semiconductor package module. The semiconductor package module includes a circuit substrate having an external connection pattern; electronic components mounted on the circuit substrate; a molding structure having a structure surrounding the circuit substrate so as to seal the electronic components from the external environment; and an external connection structure of which one portion is connected to the external connection pattern and the other portion is exposed to the outside of the molding structure. | 12-22-2011 |
20120012378 | PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME - Disclosed is a printed circuit board, including a base member, an insulating layer formed on each of both surfaces of the base member so that the surfaces of the base member are flattened, a circuit layer formed on the insulating layer, and a via for connecting the circuit layer formed on one surface of the base member with the circuit layer formed on the other surface of the base member. A method of manufacturing the printed circuit board is also provided. | 01-19-2012 |
20120018897 | SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a semiconductor module, including: a substrate including wiring patterns formed on both sides thereof; a first device mounted on the substrate; a first molding layer made of a molding material, surrounding the first device and including via holes formed therein to interconnect with the wiring pattern formed on one side of the substrate; and a second device mounted on the first molding layer and electrically connected with the wiring pattern formed on one side of the substrate through the via holes formed in the first molding layer. | 01-26-2012 |
20120067636 | INTERPOSER-EMBEDDED PRINTED CIRCUIT BOARD - Disclosed herein is an interposer-embedded printed circuit board, including: a substrate including a cavity formed in one side thereof and having a predetermined height in a thickness direction of the substrate; an interposer disposed in the cavity and including a wiring region and an insulating region; and a circuit layer formed in the substrate and including a connection pattern connected with one side of the wiring region. The interposer-embedded printed circuit board is advantageous in that an interposer is embedded in a substrate, so that the thickness of a semiconductor package can be reduced, thereby keeping up with the trend of slimming the semiconductor package. | 03-22-2012 |
20120073861 | PRINTED CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF - A printed circuit board and a manufacturing method of the printed circuit board are disclosed. The printed circuit board includes: a first insulation layer having a first pattern formed thereon; a first trench caved in one surface of the first insulation layer along at least a portion of the first pattern; and a second insulation layer stacked on one surface of the first insulation layer so as to cover the first pattern. The first trench is filled by the second insulation layer. | 03-29-2012 |
20120073870 | PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME - Disclosed is a printed circuit board, including a base member, an insulating layer formed on each of both surfaces of the base member so that the surfaces of the base member are flattened, a circuit layer formed on the insulating layer, and a via for connecting the circuit layer formed on one surface of the base member with the circuit layer formed on the other surface of the base member. A method of manufacturing the printed circuit board is also provided. | 03-29-2012 |
20120084977 | METHOD OF MANUFACTURING BLOCK MODULE - Disclosed herein is a method of manufacturing a block module including: mounting an electronic part on a base substrate on which a ground terminal is formed; forming a lead frame to extend to the outside of the base substrate from the ground terminal; connecting a flexible printed circuit to a circuit layer on the base substrate; forming a mold to surround the base substrate; cutting the lead frame and exposing the cut surface of the lead frame to the outside of the mold; and forming a metal coating layer connected to the lead frame on the mold, whereby the metal coating layer is formed to surround the mold to interrupt the electromagnetic waves and the metal coating layer is connected to the ground terminal by the lead frame to make the process simple. | 04-12-2012 |
20120129297 | METHOD OF MANUFACTURING WAFER LEVEL PACKAGE - A method of manufacturing a wafer level package including: separating chips by dicing a wafer; forming a removable resin layer in a space between the separated chips and at upper parts thereof; separating the chips by dicing the removable resin layer; mounting the chips separated in a state of being surrounded by the removable resin layer, on a carrier plate; forming a molding material on the carrier plate to cover the removable resin layer; separating the carrier plate from the chips; forming a dielectric layer having redistribution lines connected to the chips, on the chips exposed by separating the carrier plate; and forming a solder resist layer on the dielectric layer to expose portions of the redistribution lines. | 05-24-2012 |
20120152886 | METHOD OF MANUFACTURING SUBSTRATE FOR CAPACITOR-EMBEDDED PRINTED CIRCUIT BOARD AND CAPACITOR-EMBEDDED PRINTED CIRCUIT BOARD - A method of manufacturing a capacitor-embedded printed circuit board, the method including providing a substrate on which a first metal layer, a dielectric layer and an adhesive resin layer are stacked on the order thereof; etching a part of the first metal layer to form a first electrode and a first circuit pattern; compressing a surface of the substrate, on which the first electrode is formed, onto a core board by interposing an insulation resin layer; forming a second electrode and a second circuit pattern on the adhesive resin layer; stacking an insulation board on the substrate such that the second electrode and the second circuit pattern are covered; and forming a third circuit pattern on the insulation board. | 06-21-2012 |
20120161323 | SUBSTRATE FOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein are a substrate for a package and a method for manufacturing the same. The substrate for the package according to the present invention includes: a base substrate; a photosensitive insulating layer formed on one surface of the base substrate and having a roughness formed on a surface thereof; and a seed layer formed on one surface of the photosensitive insulating layer. | 06-28-2012 |
20120164825 | SEMICONDUCTOR PACKAGE WITH A METAL POST AND MANUFACTURING METHOD THEREOF - Disclosed are a semiconductor package and a manufacturing method thereof. The semiconductor package can include a semiconductor substrate, having one surface on which a conductive pad is formed; an insulating layer, being formed on one surface of the semiconductor substrate; a metal post, penetrating through the conductive pad, the semiconductor substrate, and the insulating layer; and an outer-layer circuit, being electrically connected to the metal post. With the present invention, it can become unnecessary to form an additional via for electrically connecting both surfaces of the semiconductor substrate, thereby simplifying the manufacturing process, reducing the manufacturing cost, and improving the coupling reliability. | 06-28-2012 |
20120261816 | DEVICE PACKAGE SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A device package substrate includes: a substrate having a cavity formed on a top surface thereof, the cavity having a chip mounting region; a first interconnection layer formed to extend to the inside of the cavity; a second interconnection layer formed to be spaced apart from the first interconnection layer; a chip positioned in the chip mounting region so as to be connected to the first and second interconnection layers; an insulating layer formed to cover the first and second interconnection layers and the chip and having a contact hole exposing a part of the second interconnection layer; and a bump pad formed in the contact hole so as to be connected to external elements. | 10-18-2012 |
20120295404 | METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE - A method of manufacturing a semiconductor package, the method including: forming an insulating layer on a board; forming an electrode pattern portion by redistribution plating in order to make a circuit connection on the insulating layer; manufacturing a semiconductor chip by forming a protecting portion on the electrode pattern portion such that a portion of the electrode pattern portion is exposed; and mounting the semiconductor chip on a receiving space of a circuit board and electrically connecting the semiconductor chip to the circuit board. | 11-22-2012 |
20130005089 | Wafer Level Package For Heat Dissipation And Method Of Manufacturing The Same - Disclosed herein are a wafer level package for heat dissipation and a method of manufacturing the same. The wafer level package includes a heat dissipation plate including a cavity and a hole, a die including a pad disposed in the cavity of the heat dissipation plate in a face-up manner, a thermal conductive adhesive disposed between the die and an inner wall of the cavity and disposed in the hole, and a redistribution layer connected at one end to the pad and at the other end extended. The wafer level package protects the die from external environments and enables the die to be easily flush with the heat dissipation plate. | 01-03-2013 |
20130029031 | METHOD FOR MANUFACTURING INTERPOSER - A method for manufacturing an interposer includes forming a via hole in an insulation plate including a resin or a ceramic; simultaneously forming resists for a first upper redistribution layer on the top surface of the insulation plate, and a resistor for a lower redistribution layer on the bottom surface of the insulation plate; plating copper to fill the via hole and simultaneously forming the first upper redistribution layer and the lower redistribution layer along a designed circuit pattern; and forming a first upper protection layer and a lower protection layer to expose a portion of the first upper redistribution layer and a portion of the lower redistribution layer. | 01-31-2013 |
20130056141 | DIE PACKAGE INCLUDING ENCAPSULATED DIE AND METHOD OF MANUFACTURING THE SAME - Disclosed herein is a die package including an encapsulated die, including: a die including pads on one side thereof; an encapsulation layer covering lateral sides of the die; a support layer covering the encapsulation layer and one side of the die; a passivation layer formed on the other side of the die such that the pads are exposed therethrough; and a redistribution layer formed on the passivation layer such that one part thereof is connected with the pad. Here, since one side of the die is supported by the support layer and the encapsulation layer is formed on only the lateral side of the die, the warpage of the die package due to the difference in thermal expansion coefficient can be minimized | 03-07-2013 |
20130081868 | PRINTED CIRCUIT BOARD - Disclosed herein is a printed circuit board, including: a dielectric substrate having a ground surface; a plurality of pads formed on the dielectric substrate; a transmission line transmitting a signal between the plurality of pads; and slots formed in partial regions of the ground surface correspondingly to the pads, thereby to improve signal transmitting characteristics and allow high-density wiring and thin thickness. | 04-04-2013 |
20130106528 | ASYMMETRICAL MULTILAYER SUBSTRATE, RF MODULE, AND METHOD FOR MANUFACTURING ASYMMETRICAL MULTILAYER SUBSTRATE | 05-02-2013 |
20130149437 | METHOD FOR MANUFACTURING PRINTED CIRCUIT BOARD - Disclosed herein is a method for manufacturing a printed circuit board. | 06-13-2013 |
20130153275 | PRINTED CIRCUIT BOARD AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein are a printed circuit board and a method for manufacturing the same. According to a preferred embodiment of the present invention, the printed circuit board includes: a base substrate; circuit patterns formed in a circuit region on the base substrate; dummy patterns formed in a dummy region on the base substrate; and an insulating layer formed above the circuit patterns and the dummy patterns by a slit die coating method. | 06-20-2013 |
20130162382 | CHIP INDUCTOR AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a chip inductor including: a metal-polymer composite in which metal particles and polymer are mixed; a wiring pattern provided inside the metal-polymer composite to form a coil; an external electrode provided in a portion of an outer peripheral surface of the metal-polymer composite; and an insulating portion provided between the metal-polymer composite and the wiring pattern and between the metal-polymer composite and the external electrode, and a method for manufacturing the same. | 06-27-2013 |
20130168143 | CIRCUIT BOARD - Disclosed herein is a circuit board including: an insulating material; a build-up layer formed on one surface of the insulating material, and including at least one circuit layer and at least one insulating layer; and a metal layer formed on the other surface of the insulating material and electrically disconnected from the circuit layer. | 07-04-2013 |
20130169382 | COMMON MODE FILTER AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein are a common mode filter and a method for manufacturing the same. The common mode filter includes a first insulator sheet; a first circuit layer having a first-layered first coil and a first-layered second coil alternately and separately arranged; a second insulator sheet laminated on the first circuit layer; and a second circuit layer having a second-layered first coil and a second-layered second coil alternately and separately arranged, the second-layered first coil being connected to the first-layered first coil and the second-layered second coil being connected to the first-layered second coil through the plurality of penetration holes. | 07-04-2013 |
20140051212 | METHOD OF FABRICATING A PACKAGE SUBSTRATE - A method of fabricating a package substrate, includes forming a cavity in at least one region of an upper surface of a wafer, the cavity including a chip mounting region, forming a through-hole penetrating through the wafer and a via filling the through-hole, forming a first wiring layer and a second wiring layer spaced apart from the first wiring layer, which are extended into the cavity, and mounting a chip in the cavity to be connected to the first wiring layer and the second wiring layer. | 02-20-2014 |
20140251657 | PRINTED CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME - Embodiments of the invention provide a printed circuit board, including a base member, an insulating layer formed on each of both surfaces of the base member so that the surfaces of the base member are flattened, a circuit layer formed on the insulating layer, and a via for connecting the circuit layer formed on one surface of the base member with the circuit layer formed on the other surface of the base member. A method of manufacturing the printed circuit board is also provided. | 09-11-2014 |