Patent application number | Description | Published |
20080277456 | SYSTEM AND A METHOD FOR CONTROLLING FLOW OF SOLDER - An assembly including a solder wettable surface is provided. The assembly also includes a metal mask configured to restrict solder from flowing outside the solder wettable surface. | 11-13-2008 |
20080296708 | Integrated sensor arrays and method for making and using such arrays - The present invention relates to a method for making an integrated sensor comprising providing a sensor array fabricated on a top surface of a bulk silicon wafer having a top surface and a bottom surface, and comprising a plurality of sensors fabricated on the top surface of the bulk silicon wafer. The method further comprises coupling an SOI wafer to the top surface of the bulk silicon wafer, thinning the back surface of the bulk silicon wafer, coupling a plurality of integrated circuit die to the back surface of the bulk silicon wafer, and removing the SOI wafer from the top surface of the bulk silicon wafer. | 12-04-2008 |
20090028491 | INTERCONNECT STRUCTURE - An interconnect structure includes an insulative web having a first surface and a second surface; a logic device secured to the second surface of the insulative web; a frame panel assembly including a frame base having a first surface and a second surface, a first frame insulative layer disposed between the frame base first surface and the insulative web second surface, an aperture extending through the frame base and first frame insulative layer, wherein at least a portion of the logic device is disposed within the aperture, and a first frame connector disposed between a first electrically conductive layer located on the frame base first surface, and a second electrically conductive layer located on a surface of the first frame insulative layer; a device connector disposed between an I/O contact on a surface of the logic device and a third electrical conductor located on a surface of the insulative web; and an insulative layer connector that is disposed between the third electrical conductor located on a surface of the insulative web and the second electrically conductive layer located on a surface of the first frame insulative layer. | 01-29-2009 |
20090148967 | METHODS OF MAKING AND USING INTEGRATED AND TESTABLE SENSOR ARRAY - A method for making a testable sensor assembly is provided. The method includes forming a first sensor array on a first substrate having a first side and a second side, wherein the first sensor array is formed on the first side of the first substrate, coupling a first semiconductor wafer having a first side and a second side to the first sensor array, wherein the first side of the first semiconductor wafer is coupled to the first sensor array, thinning one of the second side of the first substrate or the second side of the first semiconductor wafer, and testing the first sensor array to identify operational and non-operational units in the testable sensor assembly before integration of the sensor assembly with interface electronics. | 06-11-2009 |
20090291296 | Component protection for advanced packaging applications - A method of protecting sensitive components prior to, during or subsequent to advanced die packaging processing includes applying a metal stack layer such as titanium/copper (Ti/Cu) onto the front surface of a die assembly such that the die assembly front surface is covered with the metal stack layer. A layer of titanium/copper/titanium (Ti/Cu/Ti) or a solder alloy is also applied to the back surface of the die assembly such that the back surface of the die assembly is covered with the Ti/Cu/Ti layer or solder alloy. The front surface metal stack layer and the back surface Ti/Cu/Ti layer or solder alloy prevent degradation of die metallization prior to, during or subsequent to the advanced die packaging processing. | 11-26-2009 |
20090309241 | ULTRA THIN DIE ELECTRONIC PACKAGE - A method for forming an ultra thin die electronic package is provided. The method includes disposing a first polymer film on a first substrate. The method also includes applying a first adhesive layer to the first polymer film on the first substrate. The method further includes disposing at least one die on the first adhesive layer on the first substrate. The method also includes disposing a second polymer film on at least one additional substrate. The method further includes applying a second adhesive layer to the second polymer film on the at least one additional substrate. The method further includes attaching the first substrate and the at least one additional substrate via the first adhesive layer and the second adhesive layer such that the at least one die is interspersed between. The method also includes forming multiple vias on at least one of a top side, and at least one of a bottom side of the first and the at least one additional substrate, wherein the multiple vias are attached to the die. The method further includes forming an electrical interconnection between the first substrate, the at least one additional substrate and a die pad of the at least one die. | 12-17-2009 |
20100328896 | ARTICLE INCLUDING THERMAL INTERFACE ELEMENT AND METHOD OF PREPARATION - An article and method of forming the article is disclosed. The article includes a heat source, a heat-sink, and a thermal interface element having a plurality of freestanding nanosprings, a top layer, and a bottom layer. The nanosprings, top layer, and the bottom layers of the article include at least one inorganic material. The article can be prepared using a number of methods including the methods such as GLAD and electrochemical deposition. | 12-30-2010 |
20110069816 | APPARATUS FOR REDUCING SCATTERED X-RAY DETECTION AND METHOD OF SAME - A method, system, and apparatus including an x-ray detector unit that includes an anti-scatter grid free of at least one of a top cover and a bottom cover, a flat panel x-ray detector having an x-ray conversion layer, and an integrated anti-scatter grid assembly configured to provide structural support to the anti-scatter grid and to provide mechanical protection to the flat panel x-ray detector. The anti-scatter grid is configured to absorb a plurality of scattered x-rays impinging on the anti-scatter grid while substantially allowing un-scattered x-rays to pass through the anti-scatter grid. The x-ray conversion layer is configured to convert an x-ray into visible light or an electronic signal. The flat panel x-ray detector is fixed relative to the anti-scatter grid such that the anti-scatter grid remains stationary relative to the flat panel x-ray detector during operation of the x-ray detector. | 03-24-2011 |
20110139495 | CIRCUIT BOARD INCLUDING MASK FOR CONTROLLING FLOW OF SOLDER - A circuit board includes a solder wettable surface and a metal mask configured to restrict solder from flowing outside the solder wettable surface of the circuit board. | 06-16-2011 |
20110211795 | HERMETICALLY SEALED FIBER SENSING CABLE - In one aspect, the present invention provides a hermetically sealed fiber sensing cable comprising: a core fiber comprising at least one Bragg grating region, an outer surface and a length; a fiber cladding in contact with the core fiber along the entire length of the core fiber, the fiber cladding having an outer surface and a length; a carbon layer disposed upon the outer surface of the fiber cladding along the entire length of the fiber cladding, the carbon layer comprising diamond-like carbon; a hydrogen ion absorption layer in contact with the carbon layer, the hydrogen ion absorption layer being disposed on the outer surface of the carbon layer; and an outer sleeve. Also provided in another aspect of the present invention, is a component for a hermetically sealed fiber sensing cable. | 09-01-2011 |
20110299821 | Interconnect structure - An interconnect structure includes an insulative web having a first surface and a second surface; a logic device secured to the second surface of the insulative web; a frame panel assembly including a frame base having a first surface and a second surface, a first frame insulative layer disposed between the frame base first surface and the insulative web second surface, an aperture extending through the frame base and first frame insulative layer, wherein at least a portion of the logic device is disposed within the aperture, and a first frame connector disposed between a first electrically conductive layer located on the frame base first surface, and a second electrically conductive layer located on a surface of the first frame insulative layer; a device connector disposed between an I/O contact on a surface of the logic device and a third electrical conductor located on a surface of the insulative web; and an insulative layer connector that is disposed between the third electrical conductor located on a surface of the insulative web and the second electrically conductive layer located on a surface of the first frame insulative layer. | 12-08-2011 |
20110316167 | ELECTRICAL INTERCONNECT FOR AN INTEGRATED CIRCUIT PACKAGE AND METHOD OF MAKING SAME - An interconnect assembly for an embedded chip package includes a dielectric layer, first metal layer comprising upper contact pads, second metal layer comprising lower contact pads, and metalized connections formed through the dielectric layer and in contact with the upper and lower contact pads to form electrical connections therebetween. A first surface of the upper contact pads is affixed to a top surface of the dielectric layer and a first surface of the lower contact pads is affixed to a bottom surface of the dielectric layer. An input/output (I/O) of a first side of the interconnect assembly is formed on a surface of the lower contact pads that is opposite the first surface of the lower contact pads, and an I/O of a second side of the interconnect assembly is formed on a surface of the upper contact pads that is opposite the first surface of the upper contact pads. | 12-29-2011 |
20110317819 | ANTI-SCATTER X-RAY GRID DEVICE AND METHOD OF MAKING SAME - A method of making an anti-scatter X-ray grid device, and the X-ray grid device made therefrom, includes providing a substrate made of a material substantially non-absorbent of X-rays that includes channels therein; applying a layer, also of a substantially non-absorbent of X-rays material, onto a sidewall(s) of the channels, wherein the layer comprises a second material; and then applying a material substantially absorbent of X-rays into a portion of the channels, so as to define a plurality of X-ray absorbing elements. The present invention has been described in terms of specific embodiment(s), and it is recognized that equivalents, alternatives, and modifications, aside from those expressly stated, are possible and within the scope of the appending claims. | 12-29-2011 |
20120009733 | POWER SEMICONDUCTOR MODULE AND FABRICATION METHOD - A power semiconductor module includes: an interconnect layer including an electrical conductor patterned on a dielectric layer, the electrical conductor including a power coupling portion having a thickness sufficient to carry power currents and a control coupling portion having a thickness thinner than that of the power coupling portion; and a semiconductor power device physically coupled to the interconnect layer and electrically coupled to the power coupling portion of the electrical conductor. | 01-12-2012 |
20120018857 | SYSTEM AND METHOD OF CHIP PACKAGE BUILD-UP - A system and method for chip package fabrication is disclosed. The chip package includes a base re-distribution layer having an opening formed therein, an adhesive layer having a window formed therein free of adhesive material, and a die affixed to the base re-distribution layer by way of the adhesive layer, the die being aligned with the window such that only a perimeter of the die contacts the adhesive layer. A shield element is positioned between the base re-distribution layer and adhesive layer that is generally aligned with the opening formed in the base re-distribution layer and the window of the adhesive layer such that only a perimeter of the shield element is attached to the adhesive layer. The shield element is separated from the die by an air gap and is configured to be selectively removable from the adhesive layer so as to expose the front surface of the die. | 01-26-2012 |
20120261165 | INTERCONNECT DEVICE AND METHOD OF FABRICATING SAME - An interconnect device and a method for fabricating same. An embodiment of the invention includes sequential steps of providing a flexible substrate, forming vias through the flexible substrate, applying a conductive seed layer including first and second portions, applying conductive materials including first and second portions, copper plating the substrate, and then removing the second portions of the conductive seed layer and the conductive materials. | 10-18-2012 |
20130108019 | DETECTOR MODULES FOR IMAGING SYSTEMS AND METHODS OF MANUFACTURING | 05-02-2013 |
20130257224 | ULTRASOUND ACOUSTIC ASSEMBLIES AND METHODS OF MANUFACTURE - An ultrasound acoustic assembly includes a number of ultrasound acoustic arrays, each array comprising an acoustic stack comprising a piezoelectric layer assembled with at least one acoustic impedance dematching layer and with a support layer. The acoustic stack defines a number of dicing kerfs and a number of acoustic elements, such that the dicing kerfs are formed between neighboring ones of the acoustic elements. The dicing kerfs extend through the piezoelectric layer and through the acoustic impedance dematching layer(s) but extend only partially through the support layer. The ultrasound acoustic assembly further includes a number of application specific integrated circuit (ASIC) die. Each ultrasound acoustic array is coupled to a respective ASIC die to form a respective acoustic-electric transducer module. Methods of manufacture are also provided. | 10-03-2013 |
20140110866 | SYSTEM AND METHOD OF CHIP PACKAGE BUILD-UP - A system and method for chip package fabrication is disclosed. The chip package includes a base re-distribution layer having an opening formed therein, an adhesive layer having a window formed therein free of adhesive material, and a die affixed to the base re-distribution layer by way of the adhesive layer, the die being aligned with the window such that only a perimeter of the die contacts the adhesive layer. A shield element is positioned between the base re-distribution layer and adhesive layer that is generally aligned with the opening formed in the base re-distribution layer and the window of the adhesive layer such that only a perimeter of the shield element is attached to the adhesive layer. The shield element is separated from the die by an air gap and is configured to be selectively removable from the adhesive layer so as to expose the front surface of the die. | 04-24-2014 |
20140159213 | ELECTRICAL INTERCONNECT FOR AN INTEGRATED CIRCUIT PACKAGE AND METHOD OF MAKING SAME - An interconnect assembly for an embedded chip package includes a dielectric layer, first metal layer comprising upper contact pads, second metal layer comprising lower contact pads, and metalized connections formed through the dielectric layer and in contact with the upper and lower contact pads to form electrical connections therebetween. A first surface of the upper contact pads is affixed to a top surface of the dielectric layer and a first surface of the lower contact pads is affixed to a bottom surface of the dielectric layer. An input/output (I/O) of a first side of the interconnect assembly is formed on a surface of the lower contact pads that is opposite the first surface of the lower contact pads, and an I/O of a second side of the interconnect assembly is formed on a surface of the upper contact pads that is opposite the first surface of the upper contact pads. | 06-12-2014 |