Patent application number | Description | Published |
20080237717 | Fully Depleted SOI Multiple Threshold Voltage Application - An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A semiconductor layer overlies the buried dielectric. | 10-02-2008 |
20090078924 | Phase Change Memory with Various Grain Sizes - A memory device includes a phase change element, which further includes a first phase change layer having a first grain size; and a second phase change layer over the first phase change layer. The first and the second phase change layers are depth-wise regions of the phase change element. The second phase change layer has a second average grain size different from the first average grain size. | 03-26-2009 |
20090108249 | Phase Change Memory with Diodes Embedded in Substrate - An integrated circuit structure includes a semiconductor substrate; a diode; and a phase change element over and electrically connected to the diode. The diode includes a first doped semiconductor region of a first conductivity type, wherein the first doped semiconductor region is embedded in the semiconductor substrate; and a second doped semiconductor region over and adjoining the first doped semiconductor region, wherein the second doped semiconductor region is of a second conductivity type opposite the first conductivity type. | 04-30-2009 |
20090203202 | Strained Gate Electrodes in Semiconductor Devices - Embodiments of the invention provide a semiconductor device and a method of manufacture. MOS devices along with their polycrystalline or amorphous gate electrodes are fabricated such that the intrinsic stress within the gate electrode creates a stress in the channel region between the MOS source/drain regions. Embodiments include forming an NMOS device and a PMOS device after having converted a portion of the intermediate NMOS gate electrode layer to an amorphous layer and then recrystallizing it before patterning to form the electrode. The average grain size in the NMOS recrystallized gate electrode is smaller than that in the PMOS recrystallized gate electrode. In another embodiment, the NMOS device comprises an amorphous gate electrode. | 08-13-2009 |
20100140580 | Phase Change Memory - A phase change memory is provided. The method includes forming contact plugs in a first dielectric layer. A second dielectric layer is formed overlying the first dielectric layer and a trench formed therein exposing portions of the contact plugs. A metal layer is formed over surfaces of the trench. One or more heaters are formed from the metal layer such that each heater is formed along one or more sidewalls of the trench, wherein the portion of the heater along the sidewalls does not include a corner region of adjacent sidewalls. The trench is filled with a third dielectric layer, and a fourth dielectric layer is formed over the third dielectric layer. Trenches are formed in the fourth dielectric layer and filled with a phase change material. An electrode is formed over the phase change material. | 06-10-2010 |
20100176424 | Doping of Semiconductor Fin Devices - A semiconductor structure includes of a plurality of semiconductor fins overlying an insulator layer, a gate dielectric overlying a portion of said semiconductor fin, and a gate electrode overlying the gate dielectric. Each of the semiconductor fins has a top surface, a first sidewall surface, and a second sidewall surface. Dopant ions are implanted at a first angle (e.g., greater than about 7°) with respect to the normal of the top surface of the semiconductor fin to dope the first sidewall surface and the top surface. Further dopant ions are implanted with respect to the normal of the top surface of the semiconductor fin to dope the second sidewall surface and the top surface. | 07-15-2010 |
20110092041 | Phase Change Memory with Diodes Embedded in Substrate - An integrated circuit structure includes a semiconductor substrate; a diode; and a phase change element over and electrically connected to the diode. The diode includes a first doped semiconductor region of a first conductivity type, wherein the first doped semiconductor region is embedded in the semiconductor substrate; and a second doped semiconductor region over and adjoining the first doped semiconductor region, wherein the second doped semiconductor region is of a second conductivity type opposite the first conductivity type. | 04-21-2011 |
20110140066 | Phase Change Memory with Various Grain Sizes - A memory device includes a phase change element, which further includes a first phase change layer having a first grain size; and a second phase change layer over the first phase change layer. The first and the second phase change layers are depth-wise regions of the phase change element. The second phase change layer has a second average grain size different from the first average grain size. | 06-16-2011 |
20110212579 | Fully Depleted SOI Multiple Threshold Voltage Application - An integrated circuit comprises a substrate and a buried dielectric formed in the substrate. The buried dielectric has a first thickness in a first region, a second buried dielectric thickness in a second region, and a step between the first and second regions. A semiconductor layer overlies the buried dielectric. | 09-01-2011 |
20110298049 | CMOS Device with Raised Source and Drain Regions - A semiconductor structure includes a semiconductor substrate comprising a PMOS region and an NMOS region; a PMOS device in the PMOS region; and an NMOS device in the NMOS region. The PMOS device includes a first gate stack on the semiconductor substrate; a first offset spacer on a sidewall of the first gate stack; a stressor in the semiconductor substrate and adjacent to the first offset spacer; and a first raised source/drain extension region on the stressor and adjoining the first offset spacer, wherein the first raised source/drain extension region has a higher p-type dopant concentration than the stressor. The NMOS device in the NMOS region includes a second gate stack on the semiconductor substrate; a second offset spacer on a sidewall of the second gate stack; a second raised source/drain extension region on the semiconductor substrate and adjoining the second offset spacer; and a deep source/drain region adjoining the second raised source/drain extension region, wherein the deep source/drain region is free from stressors formed in the semiconductor substrate. | 12-08-2011 |
20140110656 | Phase Change Memory with Various Grain Sizes - A memory device includes a phase change element, which further includes a first phase change layer having a first grain size; and a second phase change layer over the first phase change layer. The first and the second phase change layers are depth-wise regions of the phase change element. The second phase change layer has a second average grain size different from the first average grain size. | 04-24-2014 |
Patent application number | Description | Published |
20090230375 | Phase Change Memory Device - A semiconductor device is provided which includes a substrate having a dielectric layer formed thereon, a heating element formed in the dielectric layer, a phase change element formed on the heating element, and a conductive element formed on the phase change element. The phase change element includes a substantially amorphous background and an active region, the active region capable of changing phase between amorphous and crystalline. | 09-17-2009 |
20100233437 | LITHOGRAPHIC MACHINE PLATFORM AND APPLICATIONS THEREOF - A lithographic machine platform and applications thereof is disclosed. The lithographic machine platform comprises: an electron beam or an ion beam generator generating an electron beam or an ion beam; a substrate supporting platform supporting a substrate; and a precursory gas injector injecting a precursory gas above the substrate. The present invention uses the electron beam or the ion beam to induce the precursory gas to react with the electron beam or the ion beam, and then the precursory gas is deposited on the substrate. The present invention not only fabricates a patterned layer on the substrate in a single step but also achieves a high lithographic resolution and avoids remains of contaminations by using the properties of the electron beam or the ion beam and the precursory gas. | 09-16-2010 |
20130084530 | METHOD FOR FABRICATING PATTERNED LAYER - A method for fabricating a patterned layer is disclosed. Firstly, a semiconductor substrate is provided. Then, a precursory gas on the semiconductor substrate is formed. Finally, a patterned layer on the semiconductor substrate is deposited by reacting the precursory gas with at least one electron beam or at least one ion beam. The present invention not only fabricates a patterned layer on the substrate in a single step but also achieves a high lithographic resolution and avoids remains of contaminations by using the properties of the electron beam or the ion beam and the precursory gas. | 04-04-2013 |
20140083855 | BIO-CHIP AND METHOD FOR SEPARATING AND CONCENTRATING PARTICLES USING THE SAME - A bio-chip adapted for separating and concentrating particles in a solution includes a chip body defining a receiving space therein for receiving the solution, an inner electrode disposed in the receiving space, an outer electrode unit disposed in the receiving space of the chip body and including a first outer electrode that is spaced apart from and surrounds the inner electrode, and a second outer electrode that is spaced apart from and surrounds the first outer electrode, and a power source electrically connected to the inner electrode, the first outer electrode, and the second outer electrode. A method for using the bio-chip to separating and concentrating the particles in the solution is also disclosed in the present invention. | 03-27-2014 |
20150145068 | STRUCTURE OF FinFETs - The present invention relates to a method for fabricating FinFETs and the structure thereof. The present invention uses an additional mask to define regions forming semiconductor fins having high semiconductor-fin height. By making use of multiple etching processes of the insulating layer, structures with differences in the height of semiconductor fins are achieved. The method can be combined with current process for semiconductor-based FinFETs for overcoming effectively the problem of electron-channel-width quantization effect as well as improving the performance of FinFETs. | 05-28-2015 |
Patent application number | Description | Published |
20080285328 | Phase Change Memory - A phase change memory is provided. The method includes forming contact plugs in a first dielectric layer. A second dielectric layer is formed overlying the first dielectric layer and a trench formed therein exposing portions of the contact plugs. A metal layer is formed over surfaces of the trench. One or more heaters are formed from the metal layer such that each heater is formed along one or more sidewalls and a portion of the bottom of the trench, wherein the portion of the heater along the sidewalls does not include a corner region of adjacent sidewalls. The trench is filled with a third dielectric layer, and a fourth dielectric layer is formed over the third dielectric layer. Trenches are formed in the fourth dielectric layer and filled with a phase change material. An electrode is formed over the phase change material. | 11-20-2008 |
20090039332 | RESISTIVE NON-VOLATILE MEMORY DEVICE - The present disclosure provides a memory cell. The memory cell includes a first electrode, a variable resistive material layer coupled to the first electrode, a metal oxide layer coupled the variable resistive material layer; and a second electrode coupled to the metal oxide layer. In an embodiment, the metal oxide layer provides a constant resistance. | 02-12-2009 |
20090087945 | Phase change memory cell with roundless micro-trenches - A method for constructing a phase change memory device includes forming a first dielectric layer on a substrate; forming a first conductive component in the first dielectric layer; forming a second dielectric layer over the first conductive component in the first dielectric layer; forming a conductive crown in the second dielectric layer, the conductive crown being in contact and alignment with the conductive component; depositing a third dielectric layer in the conductive crown; and forming a trench filled with chalcogenic materials having an amorphous phase and a crystalline phase programmable by controlling a temperature thereof to represent logic states, wherein the trench extends across the conductive crown, such that the trench is free from a rounded end portion caused by lithography during fabrication of the phase change memory device. | 04-02-2009 |
20100200923 | MULTIPLE-GATE TRANSISTOR STRUCTURE AND METHOD FOR FABRICATING - A multiple-gate transistor structure which includes a substrate, source and drain islands formed in a portion of the substrate, a fin formed of a semi-conducting material that has a top surface and two sidewall surfaces, a gate dielectric layer overlying the fin, and a gate electrode wrapping around the fin on the top surface and the two sidewall surfaces separating source and drain islands. In an alternate embodiment, a substrate that has a depression of an undercut or a notch in a top surface of the substrate is utilized. | 08-12-2010 |
20120178210 | METHOD OF FABRICATING A RESISTIVE NON-VOLATILE MEMORY DEVICE - A method of fabricating a memory cell includes forming a bottom electrode on a substrate, a variable resistive material layer on the bottom electrode, and a top electrode on the variable resistive material layer. A first metal oxide layer interposes the top electrode and the variable resistive material layer. In an embodiment, the first metal oxide layer is a self-formed layer provided by the oxidation of a portion of the top electrode. In an embodiment, a second metal oxide layer is provided interposing the first metal oxide layer and the variable resistive material layer. The second metal oxide may be a self-formed layer formed by the reduction of the variable resistive material layer. | 07-12-2012 |
Patent application number | Description | Published |
20080296702 | Integrated circuit structures with multiple FinFETs - A semiconductor structure includes a semiconductor substrate; and a first Fin field-effect transistor (FinFET) and a second FinFET at a surface of the semiconductor substrate. The first FinFET includes a first fin; and a first gate electrode over a top surface and sidewalls of the first fin. The second FinFET includes a second fin spaced apart from the first fin by a fin space; and a second gate electrode over a top surface and sidewalls of the second fin. The second gate electrode is electrically disconnected from the first gate electrode. The first and the second gate electrodes have a gate height greater than about one half of the fin space. | 12-04-2008 |
20090014836 | Memory Array with a Selector Connected to Multiple Resistive Cells - An array includes a transistor comprising a first terminal, a second terminal and a third terminal; a first contact plug connected to the first terminal of the transistor; a second contact plug connected to the first terminal of the transistor; a first resistive memory cell having a first end and a second end, wherein the first end is connected to the first contact plug; and a second resistive memory cell having a third end and a fourth end, wherein the third end is connected to the second contact plug. | 01-15-2009 |
20100117045 | Memory Array with a Selector Connected to Multiple Resistive Cells - An array includes a transistor comprising a first terminal, a second terminal and a third terminal; a first contact plug connected to the first terminal of the transistor; a second contact plug connected to the first terminal of the transistor; a first resistive memory cell having a first end and a second end, wherein the first end is connected to the first contact plug; and a second resistive memory cell having a third end and a fourth end, wherein the third end is connected to the second contact plug. | 05-13-2010 |
20140008726 | SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME - A semiconductor structure fabricating method includes the following steps. Firstly, a silicon substrate is provided. The silicon substrate has a first surface and a second surface. In addition, a first semiconductor structure is formed on the first surface of the silicon substrate. Then, the second surface of the silicon substrate is textured as a rough surface. Then, a first electrode layer is formed on the rough surface. | 01-09-2014 |
20140008799 | METHOD FOR FABRICATING METAL LINE AND DEVICE WITH METAL LINE - A metal line fabricating method includes the following steps. Firstly, a substrate is provided. Then, a first barrier layer is formed over the substrate. A first dielectric layer is formed over the first barrier layer. An opening is formed in the first dielectric layer, wherein the opening runs through the first dielectric layer, so that the first barrier layer is exposed to the opening. A metal deposition process is performed to form a metal line over the exposed first barrier layer at a bottom of the opening. The first dielectric layer and the first barrier layer underlying the first dielectric layer are removed, but the metal line and the first barrier layer underlying the metal line are remained. Afterwards, a second dielectric layer is formed over the substrate which is provided with the metal line and the first barrier layer. | 01-09-2014 |