Patent application number | Description | Published |
20080296660 | LOW RESISTIVITY CONDUCTIVE STRUCTURES, DEVICES AND SYSTEMS INCLUDING SAME, AND METHODS FORMING SAME - A conductive structure and method for making same is disclosed and includes a first nucleation layer formed by performing a cyclic deposition process on a substrate, a second nucleation layer formed on the first nucleation layer by a CVD process, and a bulk metal layer formed on the second nucleation layer. | 12-04-2008 |
20090026618 | Semiconductor device including interlayer interconnecting structures and methods of forming the same - In a method of forming a semiconductor device, and a semiconductor device formed according to the method, an insulating layer is provided on an underlying contact region of the semiconductor device. An opening is formed in the insulating layer to expose the underlying contact region. A seed layer is provided on sidewalls and a bottom of the opening, the seed layer comprising cobalt. A barrier layer of conductive material is provided in a lower portion of the opening, the seed layer being exposed on sidewalls of an upper portion of the opening. A metal layer is provided on the barrier layer in the opening to form an interlayer contact, the metal layer contacting the seed layer at the sidewalls of the upper portion of the opening. | 01-29-2009 |
20100227473 | Methods of Forming Metal Patterns in Openings in Semiconductor Devices - A method of forming a semiconductor device is disclosed. A dielectric layer having a opening therein is formed on a semiconductor substrate. An inner surface of the opening is treated by plasma. A barrier metal layer is formed on the plasma-treated inner surface of the opening. A seed layer is formed on the barrier metal layer. A metal bulk layer is formed on the seed layer. High quality semiconductor devices can be fabricated by using these methods, which may stably fill the opening formed in the dielectric layer. | 09-09-2010 |
20100230824 | Metal Interconnect of Semiconductor Device - Provided are a metal interconnect of a semiconductor device and a method of fabricating the metal interconnect. The metal interconnect includes a metal line having a first end and a second end disposed on an opposite side to the first end, a via electrically connected to the metal line, and a non-active segment extending from the first end and including a void. Tensile stress is decreased to prevent a void from occurring under the via. Accordingly, line breakage due to electromigration is substantially prevented, thus improving electrical characteristics of the device. | 09-16-2010 |
20110195569 | Semiconductor Device and Method for Forming the Same - Methods of forming field effect transistors include forming a metal alloy gate electrode (e.g., aluminum alloy) containing about 0.5 to about 1.0 atomic percent silicon, on a substrate, and electroless plating an electrically conductive gate protection layer directly on at least a portion of an upper surface of the metal alloy gate electrode. A gate dielectric layer may be formed on the substrate. This gate dielectric layer may have a dielectric constant greater than a dielectric constant of silicon dioxide. The forming of the metal alloy gate electrode may include forming a metal alloy gate electrode directly on an upper surface of the gate dielectric layer. | 08-11-2011 |
20120039564 | Photoelectric Integrated Circuit Devices And Methods Of Forming The Same - A photoelectric integrated circuit device may include a substrate including an electronic device region and an on die optical input/output device region, the substrate having a trench in the on die optical input/output device region; a lower clad layer provided in the trench, the lower clad layer having an upper surface lower than a surface of the substrate; a core provided on the lower clad layer; an insulating pattern provided on the core; an optical detection pattern provided on the insulating pattern, the optical detection pattern having at least a portion provided in the trench; and at least one transistor provided on the substrate of the electronic device region. | 02-16-2012 |
20120119376 | SEMICONDUCTOR CHIPS AND METHODS OF FORMING THE SAME - Provided are a semiconductor chip and a method of manufacturing the same. The semiconductor chip includes a substrate having a first side and a second side facing each other, and a through electrode being disposed in a hole penetrating the substrate, wherein an opening surrounded by the through electrode is disposed in the hole, wherein the opening comprises a first end adjacent to the first side of the substrate and a second end adjacent to the second side of the substrate | 05-17-2012 |
20120164826 | Methods of Forming Metal Patterns in Openings in Semiconductor Devices - A method of forming a semiconductor device is disclosed. A dielectric layer having a opening therein is formed on a semiconductor substrate. An inner surface of the opening is treated by plasma. A barrier metal layer is formed on the plasma-treated inner surface of the opening. A seed layer is formed on the barrier metal layer. A metal bulk layer is formed on the seed layer. High quality semiconductor devices can be fabricated by using these methods, which may stably fill the opening formed in the dielectric layer. | 06-28-2012 |
20120292746 | SEMICONDUCTOR DEVICES INCLUDING STRESS RELIEF STRUCTURES - A microelectronic device includes a substrate having at least one microelectronic component on a surface thereof, a conductive via electrode extending through the substrate, and a stress relief structure including a gap region therein extending into the surface of the substrate between the via electrode and the microelectronic component. The stress relief structure is spaced apart from the conductive via such that a portion of the substrate extends therebetween. Related devices and fabrication methods are also discussed. | 11-22-2012 |
20120292782 | MICROELECTRONIC DEVICES HAVING CONDUCTIVE THROUGH VIA ELECTRODES INSULATED BY GAP REGIONS - A microelectronic device includes a substrate having a trench extending therethrough between an active surface thereof and an inactive surface thereof opposite the active surface, a conductive via electrode extending through the substrate between sidewalls of the trench, and an insulating layer extending along the inactive surface of the substrate outside the trench and extending at least partially into the trench. The insulating layer defines a gap region in the trench that separates the substrate and the via electrode. Related devices and methods of fabrication are also discussed. | 11-22-2012 |
20130020719 | MICROELECTRONIC DEVICES INCLUDING THROUGH SILICON VIA STRUCTURES HAVING POROUS LAYERS - A microelectronic device includes a substrate including a via hole extending therethrough, a porous layer on sidewalls of the via hole, and a conductive via electrode extending through the via hole between the sidewalls thereof. The porous layer includes a plurality of pores therein that reduce a dielectric constant of the porous layer. Related fabrication methods are also discussed. | 01-24-2013 |
20130127019 | SEMICONDUCTOR DEVICES INCLUDING THROUGH SILICON VIA ELECTRODES AND METHODS OF FABRICATING THE SAME - A semiconductor device may include a semiconductor substrate, a through via electrode, and a buffer. The through via electrode may extend through a thickness of the semiconductor substrate with the through via electrode surrounding an inner portion of the semiconductor substrate so that the inner portion of the semiconductor substrate may thus be isolated from the outer portion of the semiconductor substrate. The buffer may be in the inner portion of the semiconductor substrate with the through via electrode surrounding and spaced apart from the buffer. Related methods are also discussed. | 05-23-2013 |
20130134603 | Semiconductor Devices Including Protected Barrier Layers - Provided are semiconductor devices and methods of manufacturing the same. the device may include a semiconductor substrate, a first conductive pattern provided in the semiconductor substrate to have a first width at a surface level of the semiconductor substrate, a barrier pattern covering the first conductive pattern and having a second width substantially greater than the first width, a second conductive pattern partially covering the barrier pattern and having a third width substantially smaller than the second width, and an insulating pattern disposed on a sidewall of the second conductive pattern. The second width may be substantially equal to or less than to a sum of the third width and a width of the insulating pattern. | 05-30-2013 |
20130175693 | SEMICONDUCTOR DEVICES - A semiconductor device includes a substrate, at least one transistor integrated with the substrate, an interlayer insulating layer on the substrate, a conductive line extending within the interlayer insulating layer and electrically connected to the transistor, and at least one capping layer containing carbon in an amount of about 2 to about 7.5 atomic percent. The capping layer may cover the interlayer insulating layer in which the conductive line extends. | 07-11-2013 |
20130200526 | SEMICONDUCTOR DEVICES HAVING THROUGH ELECTRODES AND METHODS FOR FABRICATING THE SAME - Provided are semiconductor devices with a through electrode and methods of fabricating the same. The methods may include forming a via hole at least partially penetrating a substrate, the via hole having an entrance provided on a top surface of the substrate, forming a via-insulating layer to cover conformally an inner surface of the via hole, forming a buffer layer on the via-insulating layer to cover conformally the via hole provided with the via-insulating layer, the buffer layer being formed of a material whose shrinkability is superior to the via-insulating layer, forming a through electrode to fill the via hole provided with the buffer layer, and recessing a bottom surface of the substrate to expose the through electrode. | 08-08-2013 |
20130207242 | Semiconductor Devices Having Through-Vias and Methods for Fabricating the Same - Semiconductor devices having through-vias and methods for fabricating the same are described. The method may include forming a hole opened toward a top surface of a substrate and partially penetrating the substrate, forming a sacrificial layer partially filling the hole, forming a through-via in the hole partially filled with the sacrificial layer, forming a via-insulating layer between the through-via and the substrate, and exposing the through-via through a bottom surface of the substrate. Forming the sacrificial layer may include forming an insulating flowable layer on the substrate, and constricting the insulating flowable layer to form a solidified flowable layer. | 08-15-2013 |
20130210222 | SEMICONDUCTOR DEVICES HAVING CONDUCTIVE VIA STRUCTURES AND METHODS FOR FABRICATING THE SAME - In one embodiment, the method includes forming a conductive via structure in a base layer. The base layer has a first surface and a second surface, and the second surface is opposite the first surface. The method further includes removing the second surface of the base layer to expose the conductive via structure such that the conductive via structure protrudes from the second surface, and forming a first lower insulating layer over the second surface such that an end surface of the conductive via structure remains exposed by the first lower insulating layer. | 08-15-2013 |
20130344695 | SEMICONDUCTOR CHIPS AND METHODS OF FORMING THE SAME - Provided are a semiconductor chip and a method of manufacturing the same. The semiconductor chip includes a substrate having a first side and a second side facing each other, and a through electrode being disposed in a hole penetrating the substrate, wherein an opening surrounded by the through electrode is disposed in the hole, wherein the opening comprises a first end adjacent to the first side of the substrate and a second end adjacent to the second side of the substrate | 12-26-2013 |
20140035144 | Semiconductor Devices Having Through Electrodes and Methods of Fabricating the Same - Provided are semiconductor devices having through electrodes and methods of fabricating the same. The method includes providing a substrate including top and bottom surfaces facing each other, forming a hole and a gap extending from the top surface of the substrate toward the bottom surface of the substrate, the gap surrounding the hole and being shallower than the hole, filling the hole with an insulating material, forming a metal interconnection line on the top surface of the substrate on the insulating material, recessing the bottom surface of the substrate to expose the insulating material, removing the insulating material to expose the metal interconnection line via the hole, filling the hole with a conductive material to form a through electrode connected to the metal interconnection line, recessing the bottom surface of the substrate again to expose the gap, and forming a lower insulating layer on the bottom surface of the substrate. | 02-06-2014 |
20140042633 | SEMICONDUCTOR DEVICES INCLUDING A NON-PLANAR CONDUCTIVE PATTERN, AND METHODS OF FORMING SEMICONDUCTOR DEVICES INCLUDING A NON-PLANAR CONDUCTIVE PATTERN - Semiconductor devices are provided. The semiconductor devices may include a non-planar conductive pattern. The non-planar conductive pattern may be on an insulating layer and may contact a connection terminal at a plurality of different heights. Related methods of forming semiconductor devices are also provided. | 02-13-2014 |
20140110894 | Wafer Carrier Having Cavity - A wafer carrier includes a base having a cavity provided at the center of the base and an outer sidewall extending along and away from an edge of the base to define the cavity. The cavity is configured to be filled with an adhesive layer. The wafer carrier is configured to be bonded to a wafer with an adhesive layer in the cavity of base such that the outer sidewall faces and is in contact with an edge of the wafer and the cavity faces a center of the wafer. | 04-24-2014 |
20140162449 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - Semiconductor devices, and methods of fabricating a semiconductor device, include forming a via hole through a first surface of a substrate, the via hole being spaced apart from a second surface facing the first surface, forming a first conductive pattern in the via hole, forming an insulating pad layer on the first surface of the substrate, the insulating pad having an opening exposing the first conductive pattern, performing a thermal treatment on the first conductive pattern to form a protrusion protruding from a top surface of the first conductive pattern toward the opening, and then, forming a second conductive pattern in the opening. | 06-12-2014 |
20140179103 | SEMICONDUCTOR DEVICES HAVING THROUGH-VIAS AND METHODS FOR FABRICATING THE SAME - A conductive via of a semiconductor device is provided extending in a vertical direction through a substrate, a first end of the conductive via extending through a first surface of the substrate, so that the first end protrudes in the vertical direction relative to the first surface of the substrate. An insulating layer is provided on the first end of the conductive via and on the first surface of the substrate. An upper portion of a mask layer pattern is removed so that a capping portion of the insulating layer that is on the first end of the conductive via is exposed. A portion of the insulating layer at a side of, and spaced apart from, the conductive via, is removed, to form a recess in the insulating layer. The capping portion of the insulating layer on the first end of the conductive via is simultaneously removed. | 06-26-2014 |
20140235052 | Methods for Fabricating Semiconductor Devices Having Through Electrodes - Methods for fabricating semiconductor devices having through electrodes are provided. The method may comprise forming a via hole which opens towards an upper surface of a substrate and disconnects with a lower surface of the substrate; forming a via isolation layer which extends along an inner surface of the via hole and covers the upper surface of the substrate; forming a seed layer on the via isolation layer which extends along the via isolation layer; annealing the seed layer in-situ after forming the seed layer; forming a conductive layer, filling the via hole, by an electroplating using the seed layer; and planarizing the upper surface of the substrate to form a through electrode surrounded by the via isolation layer in the via hole. | 08-21-2014 |
20140312456 | SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME - A semiconductor device can include wiring lines on a substrate and an interlayer insulating structure, between ones of the wiring lines. The wiring lines can include a pore-containing layer that includes a plurality of pores extending away from a surface of the substrate, wherein ones of the pores have respective volumes that increase with a distance from the substrate until reaching an air gap layer above the pore-containing layer and beneath uppermost surfaces of the wiring lines. | 10-23-2014 |