Patent application number | Description | Published |
20080296636 | Devices and integrated circuits including lateral floating capacitively coupled structures - According to the present invention, semiconductor device breakdown voltage can be increased by embedding field shaping regions within a drift region of the semiconductor device. A controllable current path extends between two device terminals on the top surface of a planar substrate, and the controllable current path includes the drift region. Each field shaping region includes two or more electrically conductive regions that are electrically insulated from each other, and which are capacitively coupled to each other to form a voltage divider dividing a potential between the first and second terminals. One or more of the electrically conductive regions are isolated from any external electrical contact. Such field shaping regions can provide enhanced electric field uniformity in current-carrying parts of the drift region, thereby increasing device breakdown voltage. Further aspects of the invention relate to device integration, efficient fabrication of field shaping regions and device isolation features using the same mask for both, and improved device structures. | 12-04-2008 |
20090027822 | Transient blocking unit having a fab-adjustable threshold current - A transient blocking unit (TBU) is a transistor circuit that is normally on, but rapidly and automatically switches to a high-resistance current blocking state when a current threshold is exceeded, thereby protecting a series connected load from over-voltage or over-current conditions. Process variation of transistor threshold voltage and on-resistance can cause undesirable variation of the TBU threshold current and/or of TBU resistance. Control of TBU threshold current and/or resistance is improved by providing for trimming the TBU during its fabrication to provide a one-time adjustment of the threshold current or resistance. Such trimming can be done with a resistive trimming circuit placed in series with the on-resistance of the relevant TBU transistor. Alternatively, a segmented TBU transistor having an on-resistance that is adjustable by way of wire bonding during fabrication can be employed. | 01-29-2009 |
20090206913 | Edge Termination with Improved Breakdown Voltage - A MOSFET switch which has a low surface electric field at an edge termination area, and also has increased breakdown voltage. The MOSFET switch has a new edge termination structure employing an N-P-N sandwich structure. The MOSFET switch also has a polysilicon field plate configuration operative to enhance any spreading of any depletion layer located at an edge of a main PN junction of the N-P-N sandwich structure. | 08-20-2009 |
20090206924 | Semiconductor Device Structures and Related Processes - Improved highly reliable power RFP structures and fabrication and operation processes. The structure includes plurality of localized dopant concentrated zones beneath the trenches of RFPs, either floating or extending and merging with the body layer of the MOSFET or connecting with the source layer through a region of vertical doped region. This local dopant zone decreases the minority carrier injection efficiency of the body diode of the device and alters the electric field distribution during the body diode reverse recovery. | 08-20-2009 |
20090294892 | Edge Termination for Semiconductor Devices - A high-voltage termination structure includes a peripheral voltage-spreading network. One or more trench structures are connected at least partly in series between first and second power supply voltages. The trench structures include first and second current-limiting structures connected in series with a semiconductor material, and also includes permanent charge in a trench-wall dielectric. The current-limiting structures in the trench structures are jointly connected in a series-parallel ladder configuration. The current-limiting structures, in combination with the semiconductor material, provide a voltage distribution between the core portion and the edge portion. | 12-03-2009 |
20090309156 | Super Self-Aligned Trench MOSFET Devices, Methods, and Systems - A manufacturing process and design structure for a super self-aligned trench power MOSFET. A plurality of super self-aligned trenches of different depths are formed into the body layer and epitaxial layers, preferably by using a multilayer stack of dielectric material etched to form spacers. Respective trenches contain gate conductors, body-contact conductors, and preferably a third trench containing a recessed field plate. This results in a MOSFET structure having high cell density and low gate charges and gate-drain charges. | 12-17-2009 |
20100013552 | MOSFET Switch with Embedded Electrostatic Charge - A vertical device structure includes a volume of semiconductor material, laterally adjoining a trench having insulating material on sidewalls thereof. A gate electrode within the trench is capacitively coupled through the insulating material to a first portion of the semiconducting material. Some portions of the insulating material contain fixed electrostatic charge in a density high enough to invert a second portion of the semiconductor material when no voltage is applied. The inverted portions can be used as induced source or drain extensions, to assure that parasitic are reduced without increasing on-resistance. | 01-21-2010 |
20100025726 | Lateral Devices Containing Permanent Charge - A lateral device includes a gate region connected to a drain region by a drift layer. An insulation region adjoins the drift layer between the gate region and the drain region. Permanent charges are embedded in the insulation region, sufficient to cause inversion in the insulation region. | 02-04-2010 |
20100025763 | Semiconductor on Insulator Devices Containing Permanent Charge - A lateral SOI device may include a semiconductor channel region connected to a drain region by a drift region. An insulation region on the drift layer is positioned between the channel region and the drain region. Permanent charges may be embedded in the insulation region sufficient to cause inversion in the insulation region. The semiconductor layer also overlies a global insulation layer, and permanent charges are preferably embedded in at least selected areas of this insulation layer too. | 02-04-2010 |
20100219462 | MOS-Gated Power Devices, Methods, and Integrated Circuits - MOS-gated devices, related methods, and systems for vertical power and RF devices including an insulated trench and a gate electrode. A body region is positioned so that a voltage bias on the gate electrode will cause an inversion layer in the body region. Permanent electrostatic charges are included in said insulation material. A conductive shield layer is positioned above the insulated trench, to reduce parasitic capacitances. | 09-02-2010 |
20100219468 | POWER DEVICE STRUCTURES AND METHODS - Vertical power devices which include an insulated trench containing insulating material and a gate electrode, and related methods. A body region is positioned so that a voltage bias on the gate electrode will cause an inversion layer in the body region. A layer of permanent charge, at or near the sidewall of the trench, provides charge balancing for the space charge in the depleted semiconductor material during the OFF state. A conductive shield layer is positioned below the gate electrode in the insulating material, and reduces capacitive coupling between the gate and the lower part of the trench. This reduces switching losses. In other embodiments, a planar gate electrode controls horizontal carrier injection into the vertical conduction pathway along the trench, while a shield plate lies over the trench itself to reduce capacitive coupling. | 09-02-2010 |
20100308400 | Semiconductor Power Switches Having Trench Gates - A method of fabricating a trench device includes forming a first trench and forming a hardmask layer on sidewalls of the trench. A second trench may be etched narrower than the first trench, into the bottom of the first trench. A dielectric material may be grown to substantially fill the second trench, using a reaction process to which the hardmask material is substantially inert. The growing action also grows tapered portions of the dielectric material upwardly under part of the hardmask. A conductive layer may be formed over said dielectric material. The dielectric material in the second trench, in combination with the tapered portions which extend upward from the dielectric material may provide smooth gradation of voltage differences within the semiconductor material. The gradation may be caused by potential differences between the gate and various portions of the semiconductor material. | 12-09-2010 |
20100327344 | Power Semiconductor Devices and Methods - The present inventors have realized that manufacturability plays into optimization of power semiconductor devices in some surprising new ways. If the process window is too narrow, the maximum breakdown voltage will not be achieved due to doping variations and the like normally seen in device fabrication. Thus, among other teachings, the present application describes some ways to improve the process margin, for a given breakdown voltage specification, by actually reducing the maximum breakdown voltage. In one class of embodiments, this is done by introducing a vertical gradation in the density of fixed electrostatic charge, or in the background doping of the drift region, or both. Several techniques are disclosed for achieving this. | 12-30-2010 |
20110006361 | Integrated Power Supplies and Combined High-Side Plus Low-Side Switches - The present application discloses new approaches to integrated power. Two new classes of structures each provide an integrated phase leg, in a process which can easily be integrated with low-voltage and/or peripheral circuits: in one class of disclosed structures, a lateral PMOS device is combined with an NMOS device which has predominantly vertical current flow. In another class of embodiments, a predominantly vertical n-channel device is used for the low-side switch, in combination with a lateral n-channel device. In either case, the common output node is preferably brought out at a backside contact. This device structure is advantageously used to construct complete power supply and/or voltage conversions circuits on a single chip (perhaps connected to external passive reactances). | 01-13-2011 |
20110039384 | Power MOSFET With Recessed Field Plate - A trench MOSFET contains a recessed field plate (RFP) trench adjacent the gate trench. The RFP trench contains an RFP electrode insulated from the die by a dielectric layer along the walls of the RFP trench. The gate trench has a thick bottom oxide layer, and the gate and RFP trenches are preferably formed in the same processing step and are of substantially the same depth. When the MOSFET operates in the third quadrant (with the source/body-to-drain junction forward-biased), the combined effect of the RFP and gate electrodes significantly reduces in the minority carrier diffusion current and reverse-recovery charge. The RFP electrode also functions as a recessed field plates to reduce the electric field in the channel regions when the MOSFET source/body to-drain junction reverse-biased. | 02-17-2011 |
20110079843 | POWER SEMICONDUCTOR DEVICES, METHODS, AND STRUCTURES WITH Embedded Dielectric Layers Containing Permanent Charges - Power devices using refilled trenches with permanent charge at or near their sidewalls. These trenches extend vertically into a drift region. | 04-07-2011 |
20110169103 | DEVICES, COMPONENTS AND METHODS COMBINING TRENCH FIELD PLATES WITH IMMOBILE ELECTROSTATIC CHARGE - N-channel power semiconductor devices in which an insulated field plate is coupled to the drift region, and immobile electrostatic charge is also present at the interface between the drift region and the insulation around the field plate. The electrostatic charge permits OFF-state voltage drop to occur near the source region, in addition to the voltage drop which occurs near the drain region (due to the presence of the field plate). | 07-14-2011 |
20110193131 | Devices, Structures, and Methods Using Self-Aligned Resistive Source Extensions - Devices, structures, and related methods for IGBTs and the like which include a self-aligned series resistance at the source-body junction to avoid latchup. The series resistance is achieved by using a charged dielectric, and/or by using a dielectric which provides a source of dopant atoms of the same conductivity type as the source region, at a sidewall adjacent to the source region. | 08-11-2011 |
20110220998 | Devices Containing Permanent Charge - An edge termination structure includes a final dielectric trench containing permanent charge. The final dielectric trench is surrounded by first conductivity type semiconductor material (doped by lateral outdiffusion from the trenches), which in turn is laterally surrounded by second conductivity type semiconductor material. | 09-15-2011 |
20110254088 | Power MOSFET With Embedded Recessed Field Plate and Methods of Fabrication - Semiconductor power devices, and related methods, wherein a recessed contact makes lateral ohmic contact to the source diffusion, but is insulated from the underlying recessed field plate (RFP). Such an insulated RFP is here referred to as an embedded recessed field plate (ERFP). | 10-20-2011 |
20110298043 | Semiconductor Device Structures and Related Processes - Improved highly reliable power RFP structures and fabrication and operation processes. The structure includes plurality of localized dopant concentrated zones beneath the trenches of RFPs, either floating or extending and merging with the body layer of the MOSFET or connecting with the source layer through a region of vertical doped region. This local dopant zone decreases the minority carrier injection efficiency of the body diode of the device and alters the electric field distribution during the body diode reverse recovery. | 12-08-2011 |
20120032258 | Semiconductor Device Structures and Related Processes - Improved highly reliable power RFP structures and fabrication and operation processes. The structure includes plurality of localized dopant concentrated zones beneath the trenches of RFPs, either floating or extending and merging with the body layer of the MOSFET or connecting with the source layer through a region of vertical doped region. This local dopant zone decreases the minority carrier injection efficiency of the body diode of the device and alters the electric field distribution during the body diode reverse recovery. | 02-09-2012 |
20120043602 | Power MOSFET and Its Edge Termination - Improved MOSFET structures and processes, where multiple polysilicon embedded regions are introduced into the n+ source contact area. A top poly Field Plate is used to shield the electric field from penetrating into the channel, so that a very short channel can be used without jeopardizing the device drain-source leakage current. A bottom poly Field Plate is used to modulate the electric field distribution in the drift region such that a more uniform field distribution can be obtained. | 02-23-2012 |
20120098055 | Power Semiconductor Devices, Structures, and Related Methods - Power semiconductor devices, and related methods, where majority carrier flow is divided into paralleled flows through two drift regions of opposite conductivity types. | 04-26-2012 |
20120146140 | HIGH-VOLTAGE SEMICONDUCTOR DEVICE WITH LATERAL SERIES CAPACITIVE STRUCTURE - A semiconductor device includes a semiconductor substrate, a source region extending along a top surface of the semiconductor substrate, a drain region extending along the top surface of the semiconductor substrate, and a field shaping region disposed within the semiconductor substrate between the source region and the drain region. A cross-section of the semiconductor substrate extending from the source region to the drain region through the field shaping region includes an insulating region. The semiconductor device also includes an active region disposed within the semiconductor substrate between the source region and the drain region. The active region is disposed adjacent to the field shaping region in a direction perpendicular to the cross-section of the semiconductor substrate extending from the source region to the drain region through the field shaping region. | 06-14-2012 |
20120161226 | Semiconductor Device - A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor layer of the second conductivity type is characterized by a first thickness. The semiconductor device includes a set of trenches having a predetermined depth and extending into the semiconductor layer of the second conductivity type, thereby defining interfacial regions disposed between the semiconductor layer of the second conductivity type and each of the trenches. The trenches comprises a distal portion consisting essentially of a dielectric material disposed therein and a proximal portion comprising the dielectric material and a gate material disposed interior to the dielectric material in the proximal portion of the trench. The semiconductor device further includes a source region coupled to the semiconductor layer of the second conductivity type. | 06-28-2012 |
20120187473 | Edge Termination With Improved Breakdown Voltage - A MOSFET switch which has a low surface electric field at an edge termination area, and also has increased breakdown voltage. The MOSFET switch has a new edge termination structure employing an N-P-N sandwich structure. The MOSFET switch also has a polysilicon field plate configuration operative to enhance any spreading of any depletion layer located at an edge of a main PN junction of the N-P-N sandwich structure. | 07-26-2012 |
20120261746 | Double-Trench Vertical Devices and Methods with Self-Alignment Between Gate and Body Contact - Methods and resulting device structures for power trench transistor fabrication, wherein a reachup pillar from the field plate trench is left in place to define the location of a self-aligned contact to the field plate. | 10-18-2012 |
20120319199 | Trench Gated Power Device With Multiple Trench Width and its Fabrication Process - Power devices, and related process, where both gate and field plate trenches have multiple stepped widths, using self-aligned process steps. | 12-20-2012 |
20130164895 | Trench-Gated Power Devices with Two Types of Trenches and Reliable Polycidation - Methods and systems for power semiconductor devices and structures with silicide cladding on both gates and field plates. Sidewall spacers, e.g. of silicon nitride, avoid lateral shorts or leakage between the gate silicide and the source region. A source metallization makes lateral contact to the shallow n++ source, and also makes contact to the field plate silicide and the p+ body contact region. | 06-27-2013 |
20130168762 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer of a first conductivity type having a first surface and a second surface, a source region disposed on the first surface, a gate region disposed on the first surface adjacent the source region, and a drain region disposed on the first surface. The semiconductor device also includes a pair of charge control trenches disposed between the gate region and the drain region. Each of the pair of charge control trenches is characterized by a width and includes a first dielectric material disposed therein and a second material disposed internal to the first dielectric material. Additionally, a concentration of doping impurities present in the semiconductor layer of the first conductivity type and a distance between the pair of charge control trenches define an electrical characteristic of the semiconductor device that is independent of the width of each of the pair of charge control trenches. | 07-04-2013 |
20130267080 | METHOD OF MANUFACTURE FOR A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes providing a semiconductor layer of a first conductivity type and forming a semiconductor layer of a second conductivity type thereon. The method also includes forming an insulator layer on the semiconductor layer of the second conductivity type, etching a trench into at least the semiconductor layer of the second conductivity type, and forming a thermal oxide layer in the trench and on the semiconductor layer of the second conductivity type. The method further includes implanting ions into the thermal oxide layer, forming a second insulator layer, removing the second insulator layer from a portion of the trench, and forming an oxide layer in the trench and on the epitaxial layer. Moreover, the method includes forming a material in the trench, forming a second gate oxide layer over the material, and patterning the second gate oxide layer. | 10-10-2013 |
20130299899 | Power Semiconductor Devices and Methods - The present inventors have realized that manufacturability plays into optimization of power semiconductor devices in some surprising new ways. If the process window is too narrow, the maximum breakdown voltage will not be achieved due to doping variations and the like normally seen in device fabrication. Thus, among other teachings, the present application describes some ways to improve the process margin, for a given breakdown voltage specification, by actually reducing the maximum breakdown voltage. In one class of embodiments, this is done by introducing a vertical gradation in the density of fixed electrostatic charge, or in the background doping of the drift region, or both. Several techniques are disclosed for achieving this. | 11-14-2013 |
20140021536 | LATERAL DEVICES CONTAINING PERMANENT CHARGE - A lateral device includes a gate region connected to a drain region by a drift layer. An insulation region adjoins the drift layer between the gate region and the drain region. Permanent charges are embedded in the insulation region, sufficient to cause inversion in the insulation region. | 01-23-2014 |
20140042525 | LATERAL TRANSISTORS AND METHODS WITH LOW-VOLTAGE-DROP SHUNT TO BODY DIODE - Methods and systems for power semiconductor devices integrating multiple quasi-vertical transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior. | 02-13-2014 |
20140042535 | TRENCH TRANSISTORS AND METHODS WITH LOW-VOLTAGE-DROP SHUNT TO BODY DIODE - Methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior. | 02-13-2014 |
20140054684 | Power Semiconductor Devices, Structures, and Related Methods - Power semiconductor devices, and related methods, where majority carrier flow is divided into paralleled flows through two drift regions of opposite conductivity types. | 02-27-2014 |
20140054686 | DEVICES, COMPONENTS AND METHODS COMBINING TRENCH FIELD PLATES WITH IMMOBILE ELECTROSTATIC CHARGE - N-channel power semiconductor devices in which an insulated field plate is coupled to the drift region, and immobile electrostatic charge is also present at the interface between the drift region and the insulation around the field plate. The electrostatic charge permits OFF-state voltage drop to occur near the source region, in addition to the voltage drop which occurs near the drain region (due to the presence of the field plate). | 02-27-2014 |
20140054741 | POWER SEMICONDUCTOR DEVICES, METHODS, AND STRUCTURES WITH EMBEDDED DIELECTRIC LAYERS CONTAINING PERMANENT CHARGES - Power devices using refilled trenches with permanent charge at or near their sidewalls. These trenches extend vertically into a drift region. | 02-27-2014 |
20140070308 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor layer of the second conductivity type is characterized by a first thickness. The semiconductor device includes a set of trenches having a predetermined depth and extending into the semiconductor layer of the second conductivity type, thereby defining interfacial regions disposed between the semiconductor layer of the second conductivity type and each of the trenches. The trenches comprises a distal portion consisting essentially of a dielectric material disposed therein and a proximal portion comprising the dielectric material and a gate material disposed interior to the dielectric material in the proximal portion of the trench. The semiconductor device further includes a source region coupled to the semiconductor layer of the second conductivity type. | 03-13-2014 |
20140117367 | DEVICES, STRUCTURES, AND METHODS USING SELF-ALIGNED RESISTIVE SOURCE EXTENSIONS - Devices, structures, and related methods for IGBTs and the like which include a self-aligned series resistance at the source-body junction to avoid latchup. The series resistance is achieved by using a charged dielectric, and/or by using a dielectric which provides a source of dopant atoms of the same conductivity type as the source region, at a sidewall adjacent to the source region. | 05-01-2014 |
20140117439 | MOS-Gated Power Devices, Methods, and Integrated Circuits - MOS-gated devices, related methods, and systems for vertical power and RF devices including an insulated trench and a gate electrode. A body region is positioned so that a voltage bias on the gate electrode will cause an inversion layer in the body region. Permanent electrostatic charges are included in said insulation material. A conductive shield layer is positioned above the insulated trench, to reduce parasitic capacitances. | 05-01-2014 |
20140117441 | POWER DEVICE STRUCTURES AND METHODS - Vertical power devices which include an insulated trench containing insulating material and a gate electrode, and related methods. A body region is positioned so that a voltage bias on the gate electrode will cause an inversion layer in the body region. A layer of permanent charge, at or near the sidewall of the trench, provides charge balancing for the space charge in the depleted semiconductor material during the OFF state. A conductive shield layer is positioned below the gate electrode in the insulating material, and reduces capacitive coupling between the gate and the lower part of the trench. This reduces switching losses. In other embodiments, a planar gate electrode controls horizontal carrier injection into the vertical conduction pathway along the trench, while a shield plate lies over the trench itself to reduce capacitive coupling. | 05-01-2014 |
20140183625 | Semiconductor Device - A semiconductor device includes a semiconductor layer of a first conductivity type having a first surface and a second surface, a source region disposed on the first surface, a gate region disposed on the first surface adjacent the source region, and a drain region disposed on the first surface. The semiconductor device also includes a pair of charge control trenches disposed between the gate region and the drain region. Each of the pair of charge control trenches is characterized by a width and includes a first dielectric material disposed therein and a second material disposed internal to the first dielectric material. Additionally, a concentration of doping impurities present in the semiconductor layer of the first conductivity type and a distance between the pair of charge control trenches define an electrical characteristic of the semiconductor device that is independent of the width of each of the pair of charge control trenches. | 07-03-2014 |
20140199814 | METHOD OF MANUFACTURE FOR A SEMICONDUCTOR DEVICE - A method of manufacturing a semiconductor device includes providing a semiconductor layer of a first conductivity type and forming a semiconductor layer of a second conductivity type thereon. The method also includes forming an insulator layer on the semiconductor layer of the second conductivity type, etching a trench into at least the semiconductor layer of the second conductivity type, and forming a thermal oxide layer in the trench and on the semiconductor layer of the second conductivity type. The method further includes implanting ions into the thermal oxide layer, forming a second insulator layer, removing the second insulator layer from a portion of the trench, and forming an oxide layer in the trench and on the epitaxial layer. Moreover, the method includes forming a material in the trench, forming a second gate oxide layer over the material, and patterning the second gate oxide layer. | 07-17-2014 |
20140203354 | SEMICONDUCTOR DEVICE - A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor device also includes a body layer extending a first predetermined distance into the semiconductor layer of the second conductivity type and a pair of trenches extending a second predetermined distance into the semiconductor layer of the second conductivity type. Each of the pair of trenches consists essentially of a dielectric material disposed therein and a concentration of doping impurities present in the semiconductor layer of the second conductivity type and a distance between the pair of trenches define an electrical characteristic of the semiconductor device. The semiconductor device further includes a control gate coupled to the semiconductor layer of the second conductivity type and a source region coupled to the semiconductor layer of the second conductivity type. | 07-24-2014 |
20140239386 | Trench Gated Power Device With Multiple Trench Width and its Fabrication Process - Power devices, and related process, where both gate and field plate trenches have multiple stepped widths, using self-aligned process steps. | 08-28-2014 |
20140239390 | LATERAL DEVICES CONTAINING PERMANENT CHARGE - A lateral device includes a gate region connected to a drain region by a drift layer. An insulation region adjoins the drift layer between the gate region and the drain region. Permanent charges are embedded in the insulation region, sufficient to cause inversion in the insulation region. | 08-28-2014 |
20140252463 | SCHOTTKY AND MOSFET+SCHOTTKY STRUCTURES, DEVICES, AND METHODS - Power devices which include trench Schottky barrier diodes and also (preferably) trench-gate transistors. Isolation trenches flank both the gate regions and the diode mesas, and have an additional diffusion below the bottom of the isolation trenches. The additional diffusion helps to reduce the electric field (and leakage), when the device is in the OFF state, at both the Schottky barrier and at the body diode. | 09-11-2014 |
20150076593 | POWER DEVICES, STRUCTURES, COMPONENTS, AND METHODS USING LATERAL DRIFT, FIXED NET CHARGE, AND SHIELD - Lateral power devices where immobile electrostatic charge is emplaced in dielectric material adjoining the drift region. A shield gate is interposed between the gate electrode and the drain, to reduce the Miller charge. In some embodiments the gate electrode is a trench gate, and in such cases the shield electrode too is preferably vertically extended. | 03-19-2015 |