Patent application number | Description | Published |
20090088208 | APPARATUS HAVING MOBILE TERMINAL AS INPUT/OUTPUT DEVICE OF COMPUTER AND RELATED SYSTEM AND METHOD - A system having a mobile terminal used as an input/output device of a computer is disclosed. The system may comprise a mobile terminal side audio input/output unit, a mobile terminal side sending/receiving unit, a computer side sending/receiving unit and a computer side virtual audio driving unit, wherein, the mobile terminal side audio input unit is adapted to collect audio data; the mobile terminal side audio output unit is adapted to play the audio data; the computer side virtual audio driving unit is adapted to have the mobile terminal used as the input/output device of the computer. A mobile terminal, a computer, and a method for the system are also disclosed. It is possible to, with an existing mobile terminal, directly have the mobile terminal virtualized as the input/output device of the computer by using the system of the present invention and the mobile terminal, the computer and the method thereof, so that users may use the mobile terminal to initiate and receive VoIP calls. | 04-02-2009 |
20130132816 | METHOD AND APPARATUS FOR FILE PROCESSING - The embodiments of the present invention provide a method and an apparatus for file processing. The method for file processing includes: obtaining a file; parsing the file to obtain a first character contained in the file; matching the first character with a preconfigured matching character library; obtaining an annotation corresponding to the first character when the first character satisfies a predetermined condition; and displaying the first character and the annotation. With the embodiments of the present invention, automatic annotation can be provided for a particular character in a file, such that the user's reading experience can be improved. | 05-23-2013 |
20130275588 | METHODS, DEVICES, AND SYSTEMS FOR ALLOCATING IP ADDRESS - The embodiments of the present disclosure provide a method, a device and a network system for allocating an IP address. The allocating method comprises: allocating a first IP address to a first server; allocating a second IP address to a client connected to the first server; monitoring the client allocated with the second IP address; allocating a third IP address to the first server when a monitoring result indicates that an IP address conflict exists between the first IP address and a current IP address of a second server; wherein the second server is connected to the client allocated with the second IP address. The method may reallocate the IP address automatically when a subnet conflict occurs. | 10-17-2013 |
20140092079 | THIN FILM TRANSISTOR ARRAY SUBSTATE AND LIQUID CRYSTAL DISPLAY APPARATUS THEREOF - The present disclosure provides a Thin Film Transistor Array Substrate and a Liquid Crystal Display apparatus thereof, and relates to the technical field of liquid crystal displaying. The Thin Film Transistor Array Substrate of the present disclosure includes a plurality of gate lines and a plurality of data lines, wherein regions surrounded by the gate lines and the data lines are pixel regions, and wherein a high level common voltage line being used when signal on the data line is at a low level and a low level common voltage lines being used when signal on the data line is at a high level are also arranged in parallel to the gate lines in each of the pixel regions. With the Thin Film Transistor Array Substrate of the present disclosure, the Greenish phenomenon in the existing liquid crystal display apparatus may be effectively solved. | 04-03-2014 |
20140104322 | Method and Device for Adjusting a Display Picture - The present invention discloses a method and a device for adjusting a display picture to solve a problem in the prior art that when Greenish phenomenon of a liquid crystal display screen is alleviated, aperture ratio of the display panel is decreased so that power consumption of the screen is increased. The method for adjusting the display picture includes the steps of: receiving a first clock signal for controlling a data line voltage signal for a pixel of the first color in the display picture and receiving a second clock signal for controlling data line voltage signals for pixels of the other colors; and making a pulse width at high level of the first clock signal smaller than a high level pulse width of the second clock signal, wherein the first color is closer to green than other colors. | 04-17-2014 |
20140125909 | PIXEL UNIT, ARRAY SUBSTRATE, LIQUID CRYSTAL PANEL AND METHOD FOR MANUFACTURING THE ARRAY SUBSTRATE - Embodiments of the present invention disclose a pixel unit, an array substrate, a liquid crystal panel, a display device and a manufacturing method thereof. The pixel unit comprises a thin film transistor, a pixel electrode and a common electrode, the thin film transistor comprising a gate electrode, a gate insulating layer provided on the gate electrode, an active layer provided on the gate insulating layer, a source electrode and a drain electrode provided on the active layer, and a passivation layer provided on the source electrode and the drain electrode; wherein the common electrode is provided directly on the passivation layer; and the pixel electrode is provided under the passivation layer and is connected to the drain electrode of the thin film transistor. For the array substrate, the liquid crystal panel, the display device and the manufacturing method thereof, it is possible to increase view angles, lower power consumption, and increase aperture ratio, thereby improving display quality. | 05-08-2014 |
20140132905 | ARRAY SUBSTRATE AND MANUFACTURE METHOD OF THE SAME, LIQUID CRYSTAL DISPLAY PANEL, AND DISPLAY DEVICE - The present invention relates to an array substrate and a manufacture method of the same, a liquid crystal display panel, and a display device, which are relative to a liquid crystal display field. Further, source electrodes and drain electrodes of the array substrate are arranged on different layers. In the manufacture method of the array substrate, the source electrodes and the drain electrodes are formed on different layers by two patterning processes. According to the technical scheme of the present invention, a length of a channel between the source electrodes and the drain electrodes can be decreased as much as possible, thereby increasing a start current I | 05-15-2014 |
20140175446 | ARRAY SUBSTRATE, METHOD FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE - An array substrate includes a GOA circuit area and a display area, the GOA circuit area includes a TFT area and a lead-wire area, the display area includes a data line and a gate line. The GOA circuit area is provided with at least one first via and at least one second via, a data-line metal layer is disposed at the bottom of the at least one first via, and a gate-line metal layer is disposed at the bottom of the at least one second via. The GOA circuit area further includes a first electrode and a second electrode, the data-line metal layer is electrically connected to one electrode through the at least one first via, the gate-line metal layer is electrically connected to the other electrode through the at least one second via, such that a capacitor is formed between the first electrode and the second electrode. | 06-26-2014 |
20140175448 | ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE - An array substrate, a manufacturing method thereof and a display device are provided. As for the method of manufacturing the array substrate, the common electrode and the pixel electrode are formed by a single process simultaneously. | 06-26-2014 |
20140191937 | THIN FILM TRANSISTOR THRESHOLD VOLTAGE OFFSET COMPENSATION CIRCUIT, GOA CIRCUIT, AND DISPLAY - An output thin film transistor threshold voltage offset compensation circuit, a GOA circuit, and a display. The circuit includes: a first capacitor, comprising a first electrode and a second electrode, the first electrode being connected to the gate of an output thin film transistor and receiving a charge signal, the second electrode being connected to the drain of the output thin film transistor, the first capacitor being used for, under the action of the charge signal, making the first electrode and the second electrode have a same voltage, so that a voltage difference between the drain and the source of the output thin film transistor is equal to a threshold voltage thereof; a first switch unit, connected to the drain and the source of the output thin film transistor, and opening under the action of a first clock signal, so that a voltage difference between the gate and the source of the output thin film transistor is equal to the threshold voltage thereof. | 07-10-2014 |
20140301109 | LIGHT GUIDE PLATE, BACK LIGHT MODULE AND DISPLAY APPARATUS - A light guide plate comprises a transparent light guide plate body; and a plurality of reflection sheets disposed inside the light guide plate body adjacent to a bottom surface of the light guide plate body, wherein a surface of the reflection sheet away from the bottom surface is configured as a reflection surface, regions of the light guide plate body except the reflection sheets are configured as light transmission regions, and the light transmission regions and the reflection sheets are alternately arranged. Since the reflection sheets are provided inside the light guide plate body, the reflection sheet reflects the light which is directed from the one surface and passes through the display panel, and prevents the light, which is directed from the other surface of the display apparatus, from passing through the display panel and interfering with the normal display of the one surface. In this way, the display apparatus can achieve the double-surface display. | 10-09-2014 |
20140354915 | NARROW FRAME LIQUID CRYSTAL DISPLAY AND METHOD FOR PRODUCING THE SAME, LARGE SCREEN LIQUID CRYSTAL DISPLAY APPARATUS - A narrow frame liquid crystal display, comprising: an array substrate comprising a first mounting area and a second mounting area; a color film substrate mounted on the first mounting area; a first chip bonded onto the second mounting area of the array substrate; a first flexible circuit board bonded onto the second mounting area of the array substrate; a first lead configured to electrically connect the first chip and the first flexible circuit board; and a second lead configured to electrically connect a display region of the array substrate and the first chip. The first chip, the first lead and the first flexible circuit board are sequentially arranged on the second mounting area in a first direction away from the color film substrate. A distance between the first chip and the first flexible circuit board is set to be less than 10 mm. The size of the area for mounting the chip can be reduced, and the frame of the liquid crystal display can become narrower. The present invention further provides a method of producing narrow frame liquid crystal displays. | 12-04-2014 |
20150042574 | INPUT DEVICE, TOUCH SCREEN, AND USER DEVICE - In an embodiment of the present invention, there provides an input device, a touch screen, and a user device, in order to increase the sensitivity of signal detection. The present invention relates to the field of signal detection. The input device comprises: a detection unit, a controller, and at least two sensors, wherein the detection unit corresponds to the at least two sensors, the at least two sensors are connected to the controller, and the at least two sensors correspond to at least two input types of the input device. The detection unit is configured to detect an input signal. The sensors are configured to determine the corresponding input type of the input signal after receiving the input signal detected by the detection unit. The controller is configured to control connections and disconnections between the at least two sensors and the detection unit. The embodiment of the present invention is used for signal detection. | 02-12-2015 |
Patent application number | Description | Published |
20120026968 | METHOD AND APPARATUS FOR TRIGGERING SCHEDULING INFORMATION REPORT IN MULTI-CARRIER SYSTEM - The present invention provides methods and apparatus for triggering a SI report in a multi-carrier system, and the method includes: in a multi-carrier system, configuring a timer in UE corresponding to each carrier assigned to the UE, when a state of one of the carriers meets a preconfigured condition, starting or restarting the timer corresponding to the carrier, if the timer expires, triggering a SI report; or configuring a timer in UE corresponding to all carriers, when a state of one of the carriers meets a preconfigured condition, starting or restarting the second timer, if the second timer expires, triggering a SI report. The present invention provides technical solutions for triggering the SI report according to states of the carriers when there are multiple different carrier states, and thus the SI report is triggered in the multi-carrier system. | 02-02-2012 |
20120063425 | Method and Apparatus for Uplink Synchronization Control - The present invention discloses a method for uplink synchronization control, wherein network side and a user equipment (UE) maintain a timing alignment timer (TAT) for the UE, and maintain an uplink transmission timing adjustment amount for uplink component carriers, and the method includes following steps: the network side measuring uplink component carriers of the UE, and obtaining an uplink transmission TA amount of the uplink component carriers; and before the TAT expires, the network side transmitting to the UE an adjustment command comprising information of the uplink transmission TA amount for at least one of the uplink component carriers of the UE. Also disclosed in the embodiments of the present invention are a method for uplink synchronization control at the UE side, and a base station and a UE for implementing the above methods. The solution of the present invention enables accurate adjustment of the uplink synchronization for each component carrier in a carrier aggregation mechanism. | 03-15-2012 |
20120142361 | Method, Device and System for Reconfiguring Aggregation Cell - The present invention provides a method for reconfiguring an aggregated cell, which includes that: a network side device judges whether the aggregated cell of a user equipment (UE) needs to be changed in the cell set in which the carriers can be aggregated; when the judgment result is that the change is needed, the network side device transmits a radio resource control (RRC) connection reconfiguration message to the UE, and the RRC connection reconfiguration message carries the change information of the aggregated cell of the UE; the UE receives the RRC connection reconfiguration message, and reconfigures the aggregated cell according to the RRC connection reconfiguration message. In the present invention, for the LTE-A system, when the aggregated cell of UE which supports the carrier aggregation changes within the same cell set in which the carriers can be aggregated, the aggregated cell of the UE can be reconfigured; and the same access stratum (AS) key is used to perform the security processing procedure for the data, which enables the uninterrupted transmission for the data. | 06-07-2012 |
20120188975 | METHOD AND DEVICE FOR DETERMINING CARRIER SCHEDULING MODE - A method for indicating and determining a carrier scheduling mode in a Long Term Evolution-Advanced (LTE-A) system is disclosed in the present invention. The method is that: a network device determines whether a component carrier adopts a cross-carrier scheduling mode to perform resource scheduling, and transmits first indication information that indicating whether the component carrier adopts the cross-carrier scheduling mode to perform the resource scheduling to a User Equipment (UE), so as to indicate the UE to determine whether adopting the cross-carrier scheduling mode to perform the resource scheduling on a component carrier supported by the UE itself according to the received first indication information. By adopting the present solution, the UE supporting multi-carriers in the LTE-A system is able to determine which mode one certain component carrier or several certain component carriers adopt to perform the resource scheduling, thereby performing data reception/transmission correctly. | 07-26-2012 |
20120213151 | METHOD, SYSTEM AND DEVICE FOR TRANSMITTING RANDOM ACCESS PREAMBLE - A method, a system and a device for sending a random access preamble are provided. The method includes: a base station determines an uplink component carrier to be utilized by a terminal for sending a random access preamble, and sends identification information of the uplink component carrier to the terminal ( | 08-23-2012 |
20120218987 | METHOD, SYSTEM AND DEVICE FOR UPLINK SYNCHRONIZATION - A method for uplink synchronization in a multi-carrier system includes the following steps: a base station selects one or more first component carriers, which do not establish the uplink synchronization with the base station, from multiple component carriers supported by a terminal; then the base station obtains Timing Advance (TA) needed by the terminal to perform the uplink transmission on the first component carriers, and sends the TA information to the terminal; the terminal performs the uplink transmission on said first component carriers according to said TA. The application of the present invention enables the establishment of uplink synchronization between the base station and the user equipment in multi-carrier system. | 08-30-2012 |
20120218988 | METHOD, APPARATUS AND SYSTEM FOR UPLINK SYNCHRONIZATION - A method, an apparatus and a system for uplink synchronization are disclosed by the embodiment of the invention. The method includes the following steps: a network equipment configures multi-carrier operation mode for a user equipment and obtains the timing advance TA group message corresponding to each of component carrier CC of the user equipment; the network equipment maintains the TA timer of each TA group according to the TA group information to be uplink synchronized with the user equipment. The embodiment of the invention provides the establishment and maintenance mechanism for uplink synchronization in the case that the timing advance of each component carrier CC is different in the multi-carrier system. | 08-30-2012 |
20120327877 | DATA TRANSMISSION METHOD, SYSTEM AND DEVICE IN MULTI-CARRIER SYSTEM - A data transmission method, system and device in multi-carrier system, which relate to wireless communication field, are provided for solving the problem, that is, when the scheduling methods for same time unit in the network side of multi-carrier system include Semi-Persistent Scheduling (SPS) and dynamic scheduling at the same time, how the terminal transmits data in said time unit. Before transmitting the uplink data by using the time unit, the terminal determines that the network side schedules the terminal to implement SPS uplink transmission and dynamic scheduling uplink transmission in the time unit by using the uplink component carrier and the number of uplink component carriers which can be used to implement uplink transmission by the terminal is more than one; the terminal selects parts or all of multiple available uplink component carriers, and implements SPS uplink transmission and/or dynamic scheduling uplink transmission in the time unit by using the selected uplink component carriers. | 12-27-2012 |
20130021917 | METHOD AND DEVICE FOR CONTROLLING TIMER ON BUFFER STATUS REPORT - A method for controlling a timer on buffer status report (BSR) is provided in the present invention, and the method is applied to implement the control of the timer on BSR the system to which Carrier Aggregation technology is applied. Said method includes: starting a retransmission BSR timer (retxBSR-Timer) and a BSR periodic reporting timer (periodicBSR-Timer) when a sub frame has a component carrier which has a BSR to be transmitted; restarting the retxBSR-Timer when a sub frame has a component carrier which has new data transmission resources; and restarting the periodicBSR-Timer when a sub frame has a component carrier which has a long BSR or a short BSR to be transmitted. A device for implementing said method is also provided in the present invention. | 01-24-2013 |
20130182658 | PHR PROCESSING METHOD AND DEVICE IN CARRIER AGGREGATION SYSTEM - The present invention discloses a PHR processing method and device in carrier aggregation system, and the method comprises the following steps: user equipment (UE) acquires pathloss change corresponding to uplink carrier in activation state at present; said user equipment judges whether PHR is triggered according to said pathloss change; if it is triggered, said user equipment shall acquire the power headroom (PH) information to be reported and report said PH information. In embodiments of the present invention, UE can trigger PHR according to pathloss change on uplink carrier in activation state at present in carrier aggregation system. | 07-18-2013 |
20130188570 | METHOD AND APPARATUS FOR REPORTING POWER HEADROOM IN CARRIER AGGREGATION SCENARIO - Disclosed are a method and an apparatus for reporting power headroom in a carrier aggregation context. By applying the technical solutions of the embodiments of the present invention, PHR MAC CE and a corresponding MAC sub-header are determined according to the number of uplink component carriers needing to report power headroom and a type of the power headroom to be reported, and indication information such as length information of the PHR MAC CE, type information of the power headroom, and information about whether the power headroom is virtual power headroom is carried therein, so that a base station can precisely obtain the power headroom of each uplink component carrier. In this way, the problem that the PHR MAC CE format in the current LTE Rel-8/9 is not applicable to an LTE-A system is solved. | 07-25-2013 |
20130250902 | RANDOM ACCESS METHOD AND APPARATUS - The invention discloses a random access method and apparatus so as to perform random access for a User Equipment (UE) with a plurality of aggregated cells in a carrier aggregation-enabled LTE-A system. The method includes: determining a secondary cell configured for a UE and obtaining random access related parameter preset for the secondary cell; and sending the random access related parameter to the UE to instruct the UE to initiate random access procedure over the secondary cell corresponding to the random access related parameter. The inventive method achieves the purpose of enabling the UE to be synchronized with the network side by performing random access over a specified cell, having the UE maintain uplink synchronization with the network side in the configured secondary cell and ensuring the overall performance of the system. | 09-26-2013 |
20130279377 | METHOD AND DEVICE FOR DATA TRANSMISSION BASED ON CARRIER AGGREGATION (CA) TECHNOLOGY - The present invention discloses a method and device for data transmission based on carrier aggregation (CA) technology. The method and device are used for ensuring that user equipments can work normally, when the multiple cells aggregated from the user equipments supporting CA technology have different time division duplex (TDD) uplink/downlink (UL/DL) configurations. The method includes: a base station configures at least two time division duplex uplink/downlink carrier TDD UL/DL configuration collections for the user equipments, wherein each TDD UL/DL configuration collection includes at least one cell; the base station respectively configures one cell in each TDD UL/DL configuration collection to be an especial cell (Ecell). | 10-24-2013 |
20130322305 | METHOD, SYSTEM, AND DEVICE FOR WORKING ON TDD CELL - Embodiments of the present application relate to the technical field of radio communication, and particularly to a method, system, and device for working on a TDD cell for enabling a UE to work on an asymmetric TDD cell. According to the embodiments of the present application, the method comprises: A network side device determining uplink parameter information of the asymmetric TDD cell; and the network side device putting the uplink parameter information into system information and sending the system information to a terminal to instruct the terminal to work on the corresponding asymmetric TDD cell according to the system information. In the embodiments of the present application, the uplink parameter information is added to the system information so that the terminal can work on the asymmetric TDD cell according to the system information, thereby improving the efficiency of the terminal. | 12-05-2013 |
20130336228 | METHOD, SYSTEM, AND DEVICE FOR POWER HEADROOM REPORTING AND SUB-FRAME SCHEDULING - Embodiments of the invention relate to the field of wireless communications and particularly to a method of and apparatus for power headroom reporting so as to address such a problem in the prior art that PH information is reported for only an uplink subframe and the existing PHR mechanism discourages subsequent scheduling in the case that there are different TDD UL/DL configurations for a plurality of configured and active cells aggregated for a user equipment. A method of power headroom reporting according to an embodiment of the invention includes: determining PH information of each of configured and active cells at a current instant if PH information is required to be reported, wherein the configured and active cells include a cell which is configured with a downlink subframe at the current instant; and reporting the determined PH information. Since a power headroom is reported by obtaining PH information of a configured and active cell which is currently a downlink subframe according to a virtual transmission format, the PH information facilitates subsequent scheduling by an eNB. | 12-19-2013 |
20140016555 | METHOD AND DEVICE FOR REPORTING CONFIGURABLE MAXIMUM TRANSMISSION POWER OF UE CARRIER - Disclosed are a method and device for reporting, in a carrier aggregation scenario, the configurable maximum transmission power of a UE carrier. Application of the technical solution as put forth in embodiments of the present invention enables a base station to accurately ascertain the A-MPR/MPR of a UE in a situation in which various resources are being allocated by including the configurable maximum transmission power of a UE carrier in a PHR MA CCE, and thereby more accurately perform UE scheduling | 01-16-2014 |
20140022975 | METHOD AND APPARATUS FOR TRANSMITTING DOWNLINK DATA - The present invention provides a method and an apparatus for transmitting downlink data, where unused MBSFN subframes are used for scheduling and transmitting downlink unicast data to specified terminal devices adopting a pre-defined transmission mode. Therefore, PDSCH transmission is implemented in MBSFN while the power consumption of terminal devices is kept at the same level as in the conventional art because there is no addition and modification to the higher layer signaling procedures. | 01-23-2014 |
20140044074 | RANDOM ACCESS METHOD AND APPARATUS BASED ON MULTIPLE UPLINK TIMING ADVANCES - Disclosed are a random access method and apparatus based on multiple uplink timing advances. The method includes: when acquiring that a user equipment has multiple uplink timing advances, initiating, by a network side, for the user equipment a random access on a designated carrier of a secondary cell. According to the examples, random access in the SCell can be realized in scenarios that multi-TA is maintained. | 02-13-2014 |
20140219170 | METHOD AND DEVICE FOR REPORTING CAPABILITY OF UE - A method and device for reporting a capability of UE. A UE receives a capability querying message from a base station, and sends a capability reporting message to the base station. The capability reporting message contains multi-TA capability information of the UE through at least one of an explicit mode and an implicit mode. | 08-07-2014 |
20140233535 | UPLINK TRANSMISSION METHOD AND APPARATUS IN CARRIER AGGREGATION SYSTEM - The invention discloses an uplink transmission method and apparatus in a carrier aggregation system and relates to the field of radio communications so as to address the issue of how to perform uplink transmission in a secondary cell when a base station configures a user equipment additionally with the secondary cell. In the invention, a user equipment selects, under a preset reference carrier selection rule, one of downlink carriers corresponding to cells having already eatablished downlink synchronization with a base station as a timing reference downlink carrier used by a secondary cell after the base station configures the user equipment additionally with the secondary cell; and the user equipment performs uplink transmission in the secondary cell according to downlink timing of the timing reference downlink carrier. With the invention, a timing reference downlink carrier used by an additionally configured secondary cell in uplink transmission can be determined and uplink transmission can be further preformed over the timing reference downlink carrier. | 08-21-2014 |
20140307593 | METHOD AND DEVICE FOR DATA TRANSMISSION - Disclosed are a method and device for data transmission, for improving a data transmission processing solution when a plurality of aggregated cells of user equipment have different TDD UL/DL configurations. The method includes: when the time division duplex up/downlink configurations of a plurality of aggregated cells of user equipment (UE) and only bidirectional data transmission is allowed in an up/downlink collision subframe, the UE determining the allowed data transmission direction of the up/downlink collision subframe, wherein in the time division duplex up/downlink configurations of the plurality of aggregated cells of UE, the data transmission directions of the same up/downlink collision subframe are different; the UE respectively determining available subframes for use in the uplink data transmission direction and available subframes for use in the downlink data transmission direction in each aggregated cell thereof, wherein in the available subframes counted in a data transmission direction opposite to the allowed data transmission direction, the up/downlink collision subframe is not included therein; and the UE performing data transmission in the available subframes. | 10-16-2014 |
Patent application number | Description | Published |
20100281359 | METHOD, APPARATUS AND SYSTEM FOR PROCESSING GRAPHIC OBJECTS - The present application discloses a method, apparatus and system for processing graphic objects in a flow diagram. Said method comprises obtaining a flow diagram and execution stage information generated when executing said flow diagram; obtaining a layout policy, wherein said layout policy at least designates the conditions for determining a primary path in the flow diagram using the execution stage information; determining the primary path using the execution stage information based on the layout policy; and displaying prominently said primary path during displaying said flow diagram. Owing to the present invention, the elements, such as a primary path, in a diagram in which a user takes interest can be found by the user easily to facilitate the user to understand the diagram. Furthermore, the diagram automatically arranged using the present invention is usually clear enough so that it is almost not required to be manually adjusted by the user. | 11-04-2010 |
20110214076 | METHOD AND APPARATUS FOR OPTIMIZING GENERATION OF USER INTERFACE - An apparatus and method which enable re-developers to perform complicated user interface development in a simple manner by setting extensible elements and loading thereto add-on application programs. In the apparatus and method of the invention, one or more extensible elements are set in a host user interface application. Then, one or more add-on user interface applications are loaded to one or more of the set extensible elements. The apparatus and method according to the invention can adjust the user interface dynamically, in real-time and finely without the need to close and reboot the application program. The apparatus and method of the invention do not limit the development language | 09-01-2011 |
20110320276 | SYSTEM AND METHOD FOR ONLINE MEDIA RECOMMENDATIONS BASED ON USAGE ANALYSIS - An online recommendation system, method and computer program product for recommending on-line item(s) including a recommended a usage for the on-line item(s). The recommendation method includes capturing, for one or more users at a respective client device, usage characteristics of each users' navigation to and use of one or more items, from among a plurality of items of an item set, on-line, via a respective user interface; obtaining corresponding profile information for each respective user, the profile information including user attributes; storing the usage characteristics and corresponding profile information of each of one or more users; and, for a current user navigating online to the set of items: deriving an item usage recommendation for the current online user based on items of the item set navigated to and used by other online users having similar profiles; and, recommending for the current user, via that current user's user interface, an on-line item and its suggested usage from among the set of items. | 12-29-2011 |
20120216267 | User Initiated and Controlled Identity Federation Establishment and Revocation Mechanism - A method for single sign-on with established federation includes triggering a single sign-on operation from a first service to a second service, retrieving, by the first service, an associated federation key and pseudo identification for a user agent, generating, by the first service, a token signed with a federation key for the user agent based on the pseudo identification, redirecting, by the first service, the user agent to the second service, wherein the user agent transfers the token to the second service, verifying, by the second service, the token and determining an associated identification in the second service, and returning, by the second service, a resource to the user agent. | 08-23-2012 |
20120303692 | FEDERATION OF MASTER DATA MANAGEMENT SYSTEMS - Federating master data management systems may include a network-aware adapter configured with a host master data management node. The network-aware adapter may establish one or more links with other master data management systems to allow the system to work together and leverage each other's data. | 11-29-2012 |
20130151945 | Processing Published and Subscribed Events - A method and system for processing published and subscribed events. The method includes the steps of: parsing definitions of published events and subscribed events in widget definition files in a webpage, generating a set of published events and a set of subscribed events, respectively, based on the definitions of the published events and the subscribed events, and generating a definition file of a hidden widget based on the set of published events and the set of subscribed evens, where at least one step is carried out on a computer device. | 06-13-2013 |
20130311890 | ENABLING TRANSFER OF WIDGETS ACROSS CONTAINERS AT RUNTIME - A method and system for enabling transfer of widgets across containers at runtime. According to embodiments of the present invention, a user is allowed to transfer a widget across containers at runtime, for example, moving a widget that has been deployed and operated in one widget container to another, even though the destination widget container originally does not support the widget. Specifically, the widget being transferred can keep consistency in terms of data and state before and after the transfer. Furthermore, the user can implement the cross-container transfer of widgets at runtime by, for example, convenient interaction means like a drag-and-drop operation. In this way, the user can operate and interact with Web applications in a more convenient and flexible way. | 11-21-2013 |
20140018048 | COORDINATING DATA SHARING AMONG APPLICATIONS IN MOBILE DEVICES - Coordinating data sharing among applications in mobile devices, in one aspect, may include a shared data manager application on a mobile device that manages data trade requirements of a plurality of mobile applications, and permission grants or denials to reads and writes of data managed by the shared data manager and used by the plurality of mobile applications. | 01-16-2014 |
20140020043 | AUTOMATING AND/OR RECOMMENDING DATA SHARING COORDINATION AMONG APPLICATIONS IN MOBILE DEVICES - Coordinating data sharing among applications in mobile devices, in one aspect, may include a shared data manager application on a mobile device that manages data trade requirements automatically of a plurality of mobile applications, and permission grants or denials to reads and writes of data managed by the shared data manager and used by the plurality of mobile applications. | 01-16-2014 |
Patent application number | Description | Published |
20080292005 | Enhancement layer switching for scalable video coding - An exemplary system includes a data encoder generating a base layer bitstream encoded at a base bit-rate, and a plurality of enhancement layer bitstreams encoded at different enhancement layer bit-rates, and a bitstream selection module selecting one of the enhancement layer bitstreams every video frame based on available channel bandwidth. A method includes transmitting a first enhancement layer bitstream encoded at a first bit-rate, detecting a transition in network bandwidth through a switching bit-rate, and transmitting a second enhancement layer bitstream encoded at a second bit-rate based on the transition in network bandwidth. | 11-27-2008 |
20080310506 | Joint Spatio-Temporal Prediction for Video Coding - Systems and methods are described for joint spatio-temporal prediction (JSTP) during video coding. A given block of pixels is simultaneously predicted via inter frame prediction and intra frame prediction. The joint spatio-temporal prediction provides a new JSTP coding mode besides inter and intra modes in coding schemata such as the H.264/AVC video coding standard. In one implementation, subband decomposition obtains a high-pass component of inter frame prediction of a block and a low-pass component of intra frame prediction of the same block. The high-pass component of the inter prediction and the low-pass component of the intra prediction are combined to produce the joint spatio-temporal prediction. In one implementation, a difference between the original block and the JSTP prediction is coded in a bitstream to represent the block. | 12-18-2008 |
20100020882 | Barbell Lifting for Wavelet Coding - A method for encoding motion-compensated video data includes generating, for a current frame, a high-pass wavelet coefficient based on a function of pixels in a temporally adjacent frame. The operations are repeated for multiple pixels in an array of pixels in the current frame to form an array of high-pass wavelet coefficients. A low-pass wavelet coefficient is generated based on a function of the high-pass wavelet coefficients. A system for coding video data includes a temporal wavelet decomposition module decomposing a pixel into a high-pass coefficient by performing a discrete wavelet transform on the pixel, a function of pixels in a previous frame, and/or a function of pixels in a subsequent frame. The system includes a motion estimation module generating motion vectors associated with the pixels in the previous frame and in the subsequent frame. | 01-28-2010 |
20120076414 | External Image Based Summarization Techniques - Techniques involve visually summarizing documents (e.g., search results, a collection of documents, etc.) using images which are visually representative of the documents for which the images represent. The images representing the documents may be external images obtained from sources other than the documents. The external images may be obtained from the sources other than the documents by performing a separate image based search using key phrases from the documents rather than extracting the images directly from within the documents themselves. Alternatively, an algorithm may be used to determine an image type, which may be chosen from a selection of external images, thumbnail images, or internal imaged taken directly from the collection of documents, that is suited to represent each document in the collection of documents. A snippet of the documents may be displayed along with the images which visually represent each of the documents. | 03-29-2012 |
20120189056 | Video Coding Redundancy Reduction - Embodiments for reducing redundancy in video coding are disclosed. In accordance with at least one embodiment, video content is represented as a tree structure in which the nodes of the tree structure are associated with attributes of the video content. An encoder analyzes the nodes to determine whether there is redundancy associated with a last node of a divided node. In another embodiment, bidirectional prediction video coding techniques are applied to the video content. The encoder analyzes two lists of reference frames to determine whether a third mode of bidirectional prediction is redundant to a second mode of bidirectional prediction. The efficiency of video coding is improved by refraining from sending data symbols to the decoder in the event that the video coding techniques contain redundancy. | 07-26-2012 |
20120287999 | SYNTAX ELEMENT PREDICTION IN ERROR CORRECTION - Architecture that improves error robustness in video coding and decoding. In particular, this can apply to motion vector prediction (MVP) such as a temporal MVP (TMVP). Flags can be used to indicate the use or non-use of a feature, such as to indicate whether the current slice uses or does not use TMVP, and to indicate in the slice header whether list prediction is allowed or not allowed. A flag can be signaled in sequence parameter set (SPS) or picture parameter set (PPS) as a way to enable an entire sequence to use or not use TMVP. TVMP can also be used to copy all the reference motion information to the current block. To address possible error problems, the full index of the TMVP can be recorded, and temporal information decoding refresh (TIDR) can be inserted into slices periodically. | 11-15-2012 |
20130051452 | VIDEO ENCODING ENHANCEMENTS - Techniques for implementing video encoding enhancements may increase video encoding efficiency. One of the techniques may involve the use of an exception value and a maximum index value in inter-prediction coding lookup table to enhance the combined coding of an inter-prediction direction and a reference frame index for a coding unit. Another of the techniques may include adaptively ordering the encoding of a split flag value and a skip flag value for a coding unit. An additional technique may include providing a uniform approach to adaptively combined code the coded block flag (CBF) values for transform or coding units of images that are used with the Residue Quad-tree (RQT) information to represent residue information. | 02-28-2013 |
20130170549 | MERGE MODE FOR MOTION INFORMATION PREDICTION - Disclosed herein are representative embodiments of processing digital image data. In one exemplary embodiment disclosed herein, for a current block of a first frame of digital image data, a list of motion vector prediction information for the current block is populated with candidate motion vector prediction data that includes default motion vector prediction data. In another exemplary embodiment disclosed herein, at least a portion of a coded video bitstream is received and a merge flag for a current block in a current frame is decoded. After the merge flag is decoded, at least one merge candidate for the current block is determined. | 07-04-2013 |
20130170550 | REPRESENTATIVE MOTION INFORMATION FOR TEMPORAL MOTION PREDICTION IN VIDEO ENCODING AND DECODING - Disclosed herein are representative embodiments of generating representative motion information that can be used during processing of a video frame. In one exemplary embodiment disclosed herein, a reference frame comprising a group of blocks is processed, and motion information for the group of blocks is compressed at least by buffering representative motion-vector information and representative reference-frame index information for the group of blocks. The representative reference-frame index information comprises reference-frame index information of a representative block of the group of blocks, and the representative reference-frame index information represents reference-frame index information for the group of blocks during processing of a current frame. | 07-04-2013 |
20130170556 | VARIABLE LENGTH CODING AND DECODING USING COUNTERS - Disclosed herein are representative embodiments for performing entropy coding or decoding using a counter-based scheme. In one exemplary embodiment disclosed herein, a first codeword is received from compressed digital media data. The first codeword is decoded into a first digital media data value by referencing a codeword table that associates the first codeword with the first digital media data value and a second codeword with a second digital media data value. A counter for counting occurrences of the first digital media data value is incremented. The value of the first counter is compared with the value of a second counter that counts occurrences of a second digital media data value. If the value of the first counter and the value of the second counter are equal (or greater than or equal), the codeword table is updated to swap codewords between the first and second digital media values. | 07-04-2013 |
20130343462 | Coded-Block-Flag Coding and Derivation - Techniques for coding and deriving (e.g., determining) one or more coded-block-flags associated with video content are described herein. A coded-block-flag of a last node may be determined when coded-block-flags of preceding nodes are determined to be a particular value and when a predetermined condition is satisfied. In some instances, the predetermined condition may be satisfied when log | 12-26-2013 |
20140056347 | Non-Transform Coding - Techniques for selectively transforming one or more coding units when coding video content are described herein. The techniques may include determining whether or not to transform a particular coding unit. The determination may be based on a difference in pixel values of the particular coding unit and/or one or more predefined rate-distortion constraints. When it is determined to not perform a transform, the particular coding unit may be coded without transforming the particular coding unit. | 02-27-2014 |
20140105274 | Video Coding Redundancy Reduction - Embodiments for reducing redundancy in video coding are disclosed. In accordance with at least one embodiment, video content is represented as a tree structure in which the nodes of the tree structure are associated with attributes of the video content. An encoder analyzes the nodes to determine whether there is redundancy associated with a last node of a divided node. In another embodiment, bidirectional prediction video coding techniques are applied to the video content. The encoder analyzes two lists of reference frames to determine whether a third mode of bidirectional prediction is redundant to a second mode of bidirectional prediction. The efficiency of video coding is improved by refraining from sending data symbols to the decoder in the event that the video coding techniques contain redundancy. | 04-17-2014 |
20140204088 | SURFACE CODEC USING REPROJECTION ONTO DEPTH MAPS - A surface reprojection codec and method for surface compression using non-redundant surface projection onto depth maps. A multiple depth map encoder takes a two-dimensional (2D) surface that is a representation of a three-dimensional (3D) object and divides it into a plurality of surface patches. Each of these surface patches is projected onto a depth map from a set of depth maps. This generates a set of converted depth maps. This set of converted depth maps then are encoded using standard encoding techniques. The encoded version of the 3D object may be stored, transmitted over a network, or both. A multiple depth map decoder decodes the set of converted depth maps to obtain the surface patches. These surface patches and connectivity information can be used to regenerate the 2D surface. The 2D surface in turn can be used to reconstruct the 3D object. | 07-24-2014 |
Patent application number | Description | Published |
20110159656 | METHOD FOR MANUFACTURING A MOSFET WITH A SURROUNDING GATE OF BULK SI - A method for manufacturing a bulk Si nanometer surrounding-gate MOSFET based on a quasi-planar process, including: local oxidation isolation or shallow trench isolation; depositing buffer SiO | 06-30-2011 |
20110200947 | PATTERNING METHOD - A method of patterning a dielectric layer with a Zep 520 positive EB photoresist as a mask, comprising the steps of depositing an α-Si film on the dielectric layer; providing a layer of Zep 520 positive EB photoresist having high-resolution patterns therein by electron beam direct writing; etching the α-Si film by chlorine-based plasma with the layer of Zep 520 positive EB photoresist as a mask, so as to transfer the high-resolution patterns of the Zep 520 positive EB photoresist to the underlying α-Si film; removing the Zep 520 positive EB photoresist; etching the dielectric layer by fluorine-based plasma with the α-Si film having high-fidelity patterns as a hard mask, so as to provide patterns of recesses; and removing the α-Si film by wet etching or dry etching. The inventive method is completely compatible with and easily incorporated into the conventional CMOS processes, with high reliability and resolution for providing nanoscale fine patterns of recesses. It solves the above-mentioned problem in the fabrication of novel structure of CMOS device. | 08-18-2011 |
20110237048 | METHOD FOR MANUFACTURING A FULL SILICIDATION METAL GATE - The present application discloses a method for manufacturing a full silicidation metal gate, comprises the steps of forming locally oxidized isolation or shallow trench isolation, performing prior-implantation oxidation and then doping | 09-29-2011 |
20110256701 | METHOD FOR TUNING THE WORK FUNCTION OF A METAL GATE OF THE PMOS DEVICE - The present application discloses a method for tuning the work function of a metal gate of the PMOS device, comprising the steps of depositing a layer of metal nitride or a metal on a layer of high-k gate dielectric by physical vapor deposition (PVD), as a metal gate; doping the metal gate with dopants such as Al, Pt, Ru, Ga, Ir by ion implantation; and driving the doped metal ions to the interface between the high-k gate dielectric and interfacial SiO | 10-20-2011 |
20110256704 | METHOD FOR MANUFACTURING A METAL GATE ELECTRODE/HIGH K DIELECTRIC GATE STACK - A method of manufacturing a metal gate/high K dielectric gate stack includes the steps of: forming an interfacial layer of SiON or SiO | 10-20-2011 |
20110263114 | METHOD FOR ETCHING MO-BASED METAL GATE STACK WITH ALUMINIUM NITRIDE BARRIER - The present application discloses a method for etching a Mo-based metal gate stack with an aluminum nitride barrier, comprising the steps of forming a SiO | 10-27-2011 |
20110287620 | METHOD OF ADJUSTING METAL GATE WORK FUNCTION OF NMOS DEVICE - The present invention provides a method of adjusting a metal gate work function of an NMOS device, comprising: depositing a layer of metal nitride film or metal film on a high K dielectric as a metal gate electrode by a physical vapor deposition process; implanting elements such as Tb, Er, Yb or Sr into the metal gate electrode by an ion implantation process; performing a high temperature annealing so that the doped metal ions are driven to and accumulate on the interface between the metal gate electrode and the high K gate dielectric, or form dipoles by an interface reaction on the interface between the high K gate dielectric and SiO | 11-24-2011 |
20120003827 | METHOD FOR MANUFACTURING METAL GATE STACK STRUCTURE IN GATE-FIRST PROCESS - A method for manufacturing a metal gate stack structure in gate-first process comprises the following steps after making conventional LOCOS and STI isolations: growing an untra-thin interface layer of oxide or oxynitride on a semiconductor substrate by rapid thermal oxidation or chemical process; depositing a high dielectric constant (K) gate dielectric on the untra-thin interface oxide layer and then performing rapid thermal annealing; depositing a TiN metal gate; depositing a barrier layer of AlN or TaN; depositing a poly-silicon film and a hard mask, and performing photo-lithography and the etching of the hard mask; after photo-resist removing, etching the poly-silicon film/metal gate/high-K gate dielectric sequentially to form the metal gate stack structure. The manufacturing method of the present invention is suitable for integration of high-K dielectric/metal gate in nano-scale CMOS devices, and removes obstacles of implementing high-K/metal gate integration. | 01-05-2012 |
20120094447 | METHOD FOR INTEGRATION OF DUAL METAL GATES AND DUAL HIGH-K DIELECTRICS IN CMOS DEVICES - The present invention provides a method for integrating the dual metal gates and the dual gate dielectrics into a CMOS device, comprising: growing an ultra-thin interfacial oxide layer or oxynitride layer by rapid thermal oxidation; forming a high-k gate dielectric layer on the ultra-thin interfacial oxide layer by physical vapor deposition; performing a rapid thermal annealing after the deposition of the high-k; depositing a metal nitride gate by physical vapor deposition; doping the metal nitride gate by ion implantation with P-type dopants for a PMOS device, and with N-type dopants for an NMOS device, with a photoresist layer as a mask; depositing a polysilicon layer and a hard mask by a low pressure CVD process, and then performing photolithography process and etching the hard mask; removing the photoresist, and then etching the polysilicon layer/the metal gate/the high-k dielectric layer sequentially to provide a metal gate stack; forming a first spacer, and performing ion implantation with a low energy and a large angle for source/drain extensions; forming a second spacer, and performing ion implantation for source/drain regions; performing a thermal annealing so as to adjust of the metal gate work functions for the NMOS and PMOS devices, respectively, in the course when the dopants in the source/drain regions are activated. | 04-19-2012 |
20120115087 | METHOD FOR IMPROVING ELECTRON-BEAM - A method for improving the efficiency of the electron-beam exposure is provided, comprising: step 1) coating a positive photoresist on a wafer to be processed, and performing a pre-baking; step 2) separating pattern data, optically exposing a group of relatively large patterns, and then performing a post-baking; step 3) developing the positive photoresist; step 4) performing a plasma fluorination; step 5) performing a baking to solidify the photoresist; step 6) coating a negative electron-beam resist and performing a pre-baking; step 7) electron-beam exposing a group of fine patterns; step 8) performing a post-baking; and step 9) developing the negative electron-beam resist, so that the fabrication of the patterns is finished. According to the invention, it is possible to save 30-60% of the exposure time. Thus, the exposure efficiency is significantly improved, and the cost is greatly reduced. Further, the method is totally compatible with the CMOS processes, without the need of any special equipments. | 05-10-2012 |
20120115321 | METHOD FOR REMOVING POLYMER AFTER ETCHING GATE STACK STRUCTURE OF HIGH-K GATE DIELECTRIC/METAL GATE - The present invention provides a method for removing polymer after etching a gate stack structure of high-K gate dielectric/metal gate. The method mainly comprises the following steps: 1): forming a gate stack structure of interface SiO | 05-10-2012 |
20120139054 | Device Having Adjustable Channel Stress and Method Thereof - The present invention relates to a device having adjustable channel stress and method thereof. There is provided an MOS device ( | 06-07-2012 |
20120149162 | METHOD FOR MANUFACTURING SUSPENDED FIN AND GATE-ALL-AROUND FIELD EFFECT TRANSISTOR - The present application discloses a method for manufacturing a gate-all-around field effect transistor, comprising the steps of forming a suspended fin in a semiconductor substrate; forming a gate stack around the fin; and forming source/drain regions in the fin on both sides of the gate stack, wherein an isolation dielectric layer is formed in a portion of the semiconductor substrate which is adjacent to bottom of both the fin and the gate stack. The present invention relates to a method for manufacturing a gate-all-around device on a bulk silicon substrate, which suppress a self-heating effect and a floating-body effect of the SOI substrate, and lower a manufacture cost. The inventive method is a conventional top-down process with respect to a reference plane, which can be implemented as a simple manufacture process, and is easy to be integrated into and compatible with a planar CMOS process. The inventive method suppresses a short channel effect and promotes miniaturization of MOSFETs. | 06-14-2012 |
20120164808 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device includes the steps of: forming a first gate stack on a semiconductor substrate, the first gate stack includes a first gate conductor and a first gate dielectric between the first gate conductor and the semiconductor substrate; forming source/drain regions on the semiconductor substrate; forming a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack; performing a first RIE on the multilayer structure; performing a second RIE on the multilayer structure; selectively etching the first gate stack with respect to the insulating layer, in which the first gate conductor is removed and an opening is formed in the insulating layer; and forming a second gate conductor in the opening. | 06-28-2012 |
20120164838 | METHOD FOR PLANARIZING INTERLAYER DIELECTRIC LAYER - The present application discloses provides a method for planarizing an interlayer dielectric layer, comprising the steps of: providing a multilayer structure including at least one sacrificial layer and at least one insulating layer under the sacrificial layer on the semiconductor substrate and the first gate stack, performing a first RIE on the multilayer structure, in which a reaction chamber pressure is controlled in such a manner that an etching rate of the portion of the at least one sacrificial layer at a center of a wafer is higher than that at an edge of the wafer, so as to obtain a concave etching profile; performing a second RIE on the multilayer structure to completely remove the sacrificial layer and a part of the insulating layer, so as to obtain the insulating layer having a planar surface which serves as an interlayer dielectric layer. The planarization process can replace a CMP process for providing an interlayer dielectric layer having a planar surface, which achieves a relative larger available area of the wafer. | 06-28-2012 |
20120181634 | Method of Introducing Strain Into Channel and Device Manufactured by Using the Method - The present invention relates to a method of introducing strain into a channel and a device manufactured by using the method, the method comprising: providing a semiconductor substrate; forming a channel in the semiconductor substrate; forming a first gate dielectric layer on the channel; forming a polysilicon gate layer on the first gate dielectric layer; doping or implanting a first element into the polysilicon gate layer; removing a part of the first gate dielectric layer and polysilicon gate layer to thereby form a first gate structure; forming a source/drain extension region in the channel; forming spacers on both sides of the first gate structure; forming a source/drain in the channel; and performing annealing such that lattice change occurs in the polysilicon that is doped or implanted with the first element in the high-temperature crystallization process, thereby producing a first strain in the polysilicon gate layer, and introducing the first strain through the gate dielectric layer to the channel. This method has greater process flexibility and simple process complexity with no additional process cost. | 07-19-2012 |
20120220093 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE - The present application discloses a method for manufacturing a semiconductor device, comprising: forming a local buried isolation dielectric layer in a semiconductor substrate; forming a fin in the semiconductor substrate and on top of the local buried isolation dielectric layer; forming a gate stack structure on a top surface and side surfaces of the fin; forming source/drain structures in portions of the fin which are on opposite sides of the gate stack structure; and performing metallization. A conventional quasi-planar top-down process is utilized in the present invention to achieve a good compatibility with the CMOS planar processes, easy integration, and suppression of short channel effects, which promotes the development of MOSFETs having reduced sizes. | 08-30-2012 |
20120261763 | Semiconductor Structure and Method for Manufacturing the Same - The present invention relates to a semiconductor and a method for manufacturing the same. The semiconductor structure comprises an NMOS device comprising a first gate structure and a PMOS device comprising a second gate structure; a first stress liner, at least formed on both sides of the first gate structure of said NMOS device; a second stress liner, at least formed on both sides of the second gate structure of said PMOS device; wherein said first stress liner is a spin-on glass (SOG) film with tensile stress, said second stress liner is formed of a material that can introduce compressive stress into the channel of the PMOS device. The present invention can reduce the difficulty of the process of manufacturing dual stress liner using the same material, e.g. nitride, and can reduce influence of nitride having a high dielectric constant upon the device interconnect delay while still maintaining the tensile strain advantage. | 10-18-2012 |
20120282748 | Method for manufacturing stack structure of PMOS device and adjusting gate work function - The present disclosure provides a method for manufacturing a gate stack structure and adjusting a gate work function for a PMOS device, comprising: growing an ultra-thin interface oxide layer or oxynitride layer on a semiconductor substrate by rapid thermal oxidation or chemical method after conventional LOCOS or STI dielectric isolation is completed; depositing high-K gate dielectric and performing rapid thermal annealing; depositing a composite metal gate; depositing a barrier metal layer; depositing a polysilicon film and a hard mask and then performing photolithography and etching the hard mask; removing photoresist and etching the polysilicon film, the barrier metal layer, the metal gate, the high-K gate dielectric, and the interface oxide layer in sequence to form a gate stack structure of polysilicon film/barrier metal layer/metal gate/high-K gate dielectric; forming spacers, source/drain implantation in a conventional manner and performing rapid thermal annealing, whereby while source/drain dopants are activated, adjusting of metal gate effective work function of the PMOS device is achieved. | 11-08-2012 |
20120329218 | METHOD FOR MANUFACTURING SEMICONDUCTOR FIELD EFFECT TRANSISTOR - The present disclosure provides a method for manufacturing a semiconductor field effect transistor, comprising: forming a semiconductor substrate having a local Silicon-on-Insulator (SOI) structure, which comprises a local buried isolation dielectric layer; forming a fin on a silicon substrate above the local buried isolation dielectric layer; forming a gate stack structure on a top and on side faces of the fin; forming source/drain structures in the fin at both sides of the gate stack structure; and metallizing. The present disclosure uses a conventional top-to-bottom process based on quasi-plane, which has a good compatibility with CMOS planar processes. Also, the method can suppress short channel effects and help to reduce the dimensions of MOSFETs. | 12-27-2012 |
20130005097 | METHOD FOR INTEGRATING REPLACEMENT GATE IN SEMICONDUCTOR DEVICE - A method for integrating a replacement gate in a semiconductor device is disclosed. The method may comprise: forming a well region on a semiconductor substrate, and defining a N-type device region and/or a P-type device region; forming a sacrificial gate stack or sacrificial gate stacks respectively on the N-type device region and/or the P-type device region, the sacrificial gate stack or each of the sacrificial gate stacks comprising a sacrificial gate dielectric layer and a sacrificial gate electrode layer, wherein the sacrificial gate dielectric layer is disposed on the semiconductor substrate, and the sacrificial gate electrode layer is disposed on the sacrificial gate dielectric layer; forming a spacer or spacers surrounding the sacrificial gate stack or the respective sacrificial gate stacks; forming source/drain regions on both sides of the sacrificial gate stack or the respective sacrificial gate stacks and embedded into the semiconductor substrate; forming a SiO | 01-03-2013 |
20130005127 | METHOD FOR MANUFACTURING MULTIGATE DEVICE - A method for manufacturing a multigate device is provided, comprising: providing a semiconductor substrate; etching the semiconductor substrate to form a protruding fin; etching the semiconductor substrate at the bottom of the fin so as to form a gap between the fin and the semiconductor substrate; forming a dielectric layer which covers the semiconductor substrate and the fin and fills the gap; and etching the dielectric layer so as to expose the top and a portion of sidewalls of the fin. The present invention can realize isolation between fins with a simple process, which costs relatively low and is suitable for massive industrial application. | 01-03-2013 |
20130011986 | Method for Manufacturing Full Silicide Metal Gate Bulk Silicon Multi-Gate Fin Field Effect Transistors - The present application discloses a method for manufacturing a full silicide metal gate bulk silicon multi-gate fin field effect transistor, which comprises the steps of: forming at least one fin on the semiconductor substrate; forming a gate stack structure on top and side surfaces of the fin; forming a source/drain extension area in the fin on both sides of the gate stack structure; forming a source/drain area on both sides of the source/drain extension area; forming silicide on the source/drain area; forming a full silicide metal gate electrode; and forming contact and implementing metalization. The present invention eliminates the self-heating effect and the floating body effect of SOI devices, then has a much lower cost, overcomes such defects as the polysilicon gate depletion effect, Boron penetration effect, and large series resistance of polysilicon gate electrodes, and has good compatibility with the planar COMS technology, thus it can be easily integrated. | 01-10-2013 |
20130026496 | Semiconductor Device and Manufacturing Method Thereof - A method for manufacturing a semiconductor device, comprising forming a tunneling dielectric layer, a storage dielectric layer, a gate dielectric layer and a gate layer sequentially on a semiconductor substrate of a first semiconductor material; patterning the tunneling dielectric layer, the storage dielectric layer, the gate dielectric layer and the gate layer to form a gate stack; forming a groove in the semiconductor substrate on the sides of the gate stack; filling the groove with a second semiconductor material different from the first semiconductor material, meanwhile, the entire device is covered by the dielectric layer. The surface energy level in the channel is made to change by the stress generated by the second semiconductor material and the covering dielectric layer, thereby increasing tunneling current and improving the storage efficiency of the device. | 01-31-2013 |
20130078773 | Method for manufacturing CMOS FET - A method for manufacturing a CMOS FET comprises forming a first interfacial SiO | 03-28-2013 |
20130082362 | Semiconductor Device and Manufacturing Method thereof - A semiconductor device and its manufacturing method, wherein the NMOS device is covered by a layer of silicon nitride film having a high ultraviolet light absorption coefficient through PECVD, said silicon nitride film can well absorb ultraviolet light when being subject to the stimulated laser surface anneal so as to achieve a good dehydrogenization effect, and after dehydrogenization, the silicon nitride film will have a high tensile stress; since the silicon nitride film has a high ultraviolet light absorption coefficient, there is no need to heat the substrate, thus avoiding the adverse influences to the device caused by heating the substrate to dehydrogenize, and maintaining the heat budget brought about by the PECVD process. | 04-04-2013 |
20130099328 | P-TYPE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME - The present application provides a p-type semiconductor device and a method for manufacturing the same. The structure of the device comprises: a semiconductor substrate; a channel region positioned in the semiconductor substrate; a gate stack which is positioned on the channel region comprising a gate dielectric layer and a gate electrode, wherein the gate dielectric layer is positioned on the channel region and the gate electrode is positioned on the gate dielectric layer; and source/drain regions positioned at the two sides of the channel region and embedded into the semiconductor substrate; wherein the element Al is distributed in at least one of the upper surface, the bottom surface of the gate dielectric layer and the bottom surface of the gate electrode. The embodiments of the present invention are applicable for manufacturing MOSFET. | 04-25-2013 |
20130105906 | CMOS Device Having Dual Metal Gates and Method of Manufacturing the Same | 05-02-2013 |
20130105907 | MOS DEVICE AND METHOD OF MANUFACTURING THE SAME | 05-02-2013 |
20130130448 | METHOD FOR FORMING AND CONTROLLING MOLECULAR LEVEL SiO2 INTERFACE LAYER - The present disclosure provides a method for forming and controlling a molecular level SiO | 05-23-2013 |
20130134515 | Semiconductor Field-Effect Transistor Structure and Method for Manufacturing the Same - The present application discloses a semiconductor Field-Effect Transistor (FET) structure and a method for manufacturing the same, wherein the method comprises: forming a semiconductor substrate comprising an SOI structure having a body-contact hole; forming a fin on the SOI structure of the semiconductor substrate; forming a gate stack structure on top and side faces of the fin; forming source/drain structures in the fin on both sides of the gate stack structure; and performing metallization. The present invention makes use of traditional quasi-planar based top-down processes, thus the manufacturing process thereof becomes simple to implement; the present invention exhibits good compatibility with CMOS planar process and can be easily integrated; the present invention also is favorable for suppressing short channel effects desirably, and boosts MOSFETs to develop towards a trend of downscaling size. | 05-30-2013 |
20130134516 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present application discloses a semiconductor device structure and a method for manufacturing the same, wherein the method comprises: forming a semiconductor substrate comprising a local SOI structure having a local buried isolation dielectric layer; forming a fin on the silicon substrate on top of the local buried isolation dielectric layer; forming a gate stack structure on the top and side faces of the fin; forming source/drain structures in the fin on both sides of the gate stack structure; and performing metallization. The present invention makes use of traditional quasi-planar based top-down processes, thus the manufacturing process thereof is simple to implement; the present invention exhibits good compatibility with CMOS planar process and can be easily integrated, therefore, short channel effects are suppressed desirably, and MOSFETs are boosted to develop towards a trend of downscaling size. | 05-30-2013 |
20130137264 | SEMICONDUCTOR DEVICE MANUFACTURING METHOD - A semiconductor device manufacturing method, comprising: providing a semiconductor substrate, on which a gate conductor layer as well as a source region and a drain region positioned on both sides of the gate conductor layer are provided, forming an etch stop layer on the semiconductor substrate, forming an LTO layer on the etch stop layer, chemical mechanical polishing the LTO layer, forming an SOG layer on the polished LTO layer, the etch stop layer, LTO layer and SOG layer forming a front metal insulating layer, back etching the SOG layer and etch stop layer of the front metal insulating layer to expose the gate conductor layer, and removing the gate conductor layer. | 05-30-2013 |
20130240996 | Semiconductor Device and Method of Manufacturing the Same - The present invention discloses a semiconductor device, comprising a substrate, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each gate stack structure, a plurality of source and drain regions in the substrate on both sides of each gate spacer structure, the plurality of gate spacer structures comprising a plurality of first gate stack structures and a plurality of second gate stack structures, wherein each of the first gate stack structures comprises a first gate insulating layer, a first work function metal layer, a second work function metal diffusion blocking layer, and a gate filling layer, the work function is close to the valence band (conduction band) edge; each of the second gate stack structures comprises a second gate insulating layer, a modified first work function metal layer, a second work function metal layer, and a gate filling layer, characterized in that the second work function metal layer comprises implanted work function-regulating doped ions, which are simultaneously diffused to the first work function layer below to regulate the threshold such that the work function of the gate is close to the valence band (conduction band) edge and is opposite the original first work function, to thereby regulate the work function accurately. | 09-19-2013 |
20130241004 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention discloses a semiconductor device, comprising substrates, a plurality of gate stack structures on the substrate, a plurality of gate spacer structures on both sides of each gate stack structure, a plurality of source and drain regions in the substrate on both sides of each gate spacer structure, the plurality of gate spacer structures comprising a plurality of first gate stack structures and a plurality of second gate stack structures, wherein each of the first gate stack structures comprises a first gate insulating layer, a first work function metal layer, a second work function metal diffusion blocking layer, and a gate filling layer; Each of the second gate stack structures comprises a second gate insulating layer, a first work function metal layer, a second work function metal layer, and a gate filling layer, characterized in that the first work function metal layer has a first stress, and the gate filling layer has a second stress. Two metal gate layers of different types and/or intensity of stress are formed, respectively, thus different stresses are applied to the channel regions of different MOSFETs effectively and accurately, the device carrier mobility is enhanced simply and efficiently, and the device performance is also enhanced. | 09-19-2013 |
20130249012 | CMOS Device and Method for Manufacturing the Same - This invention discloses a CMOS device, which includes: a first MOSFET; a second MOSFET different from the type of the first MOSFET; a first stressed layer covering the first MOSFET and having a first stress; and a second stressed layer covering the second MOSFET, wherein the second stressed layer is doped with ions, and thus has a second stress different from the first stress. This invention's CMOS device and method for manufacturing the same make use of a partitioned ion implantation method to realize a dual stress liner, without the need of removing the tensile stressed layer on the PMOS region or the compressive stressed layer on the NMOS region by photolithography/etching, thus simplifying the process and reducing the cost, and at the same time, preventing the stress in the liner on the NMOS region or PMOS region from the damage that might be caused by the thermal process of the deposition process. | 09-26-2013 |
20130256808 | Semiconductor Device and Method of Manufacturing the Same - The present invention discloses a semiconductor device, comprising a first MOSFET; a second MOSFET; a first stress liner covering the first MOSFET and having a first stress; a second stress liner covering the second MOSFET and having a second stress; wherein the second stress liner and/or the first stress liner comprise(s) a metal oxide. In accordance with the high-stress CMOS and method of manufacturing the same of the present invention, a stress layer comprising a metal oxide is formed selectively on PMOS and NMOS respectively by using a CMOS compatible process, whereby carrier mobility of the channel region is effectively enhanced and the performance of the device is improved. | 10-03-2013 |
20130285127 | semiconductor structure and method of manufacturing the same - The present application discloses a method for manufacturing a semiconductor structure, comprises the following steps: providing a substrate and forming a gate stack on the substrate; forming an offset spacer surround the gate stack and a dummy spacer surround the offset spacer; forming the S/D region on both sides of the dummy spacer; removing the dummy spacer and portions of the offset spacer on the surface of the substrate; forming a doped spacer on the sidewall of the offset spacer; forming the S/D extension region by allowing the dopants in doped spacer into the substrate; removing the doped spacer. Accordingly, the present application also discloses a semiconductor structure. In the present disclosure the S/D extension region with high doping concentration and shallow junction depth is formed by the formation of a heavily doped doped spacer, which can be removed in the subsequent procedures, in order to efficiently improve the performance of the semiconductor structure. | 10-31-2013 |
20140027783 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention discloses a semiconductor device, comprising a plurality of fins located on a substrate and extending along a first direction; a plurality of gate stack structures extending along a second direction and across each of the fins; a plurality of stress layers located in the fins on both sides of the gate stack structures and having a plurality of source and drain regions therein; a plurality of channel regions located between the plurality of source and drain regions along a first direction; characterized in that the plurality of gate stack structures enclose the plurality of channel regions. In accordance with the semiconductor device and the method of manufacturing the same of the present invention, an all-around nanowire metal multi-gate is formed in self-alignment by punching through and etching the fins at which the channel regions are located using a combination of the hard mask and the dummy gate, thus the device performance is enhanced. | 01-30-2014 |
20140154853 | METHOD FOR MANUFACTURING N-TYPE MOSFET - The present disclosure discloses a method for manufacturing an N-type MOSFET, comprising: forming a part of the MOSFET on a semiconductor substrate, the part of the MOSFET comprising source/drain regions in the semiconductor substrate, a replacement gate stack between the source/drain regions above the semiconductor substrate, and a gate spacer surrounding the replacement gate stack; removing the replacement gate stack of the MOSFET to form a gate opening exposing a surface of the semiconductor substrate; forming an interface oxide layer on the exposed surface of the semiconductor; forming a high-K gate dielectric layer on the interface oxide layer in the gate opening; forming a first metal gate layer on the high-K gate dielectric layer; implanting dopant ions into the first metal gate layer; and performing annealing to cause the dopant ions to diffuse and accumulate at an upper interface between the high-K gate dielectric layer and the first metal gate layer and a lower interface between the high-K gate dielectric layer and the interface oxide layer, and also to generate electric dipoles by interfacial reaction at the lower interface between the high-K gate dielectric layer and the interface oxide layer. | 06-05-2014 |
20140191335 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME - The present invention discloses a semiconductor device, comprising a plurality of fins located on a substrate and extending along a first direction; a plurality of gate stack structures extending along a second direction and across each of the fins; a plurality of stress layers located in the fins on both sides of the gate stack structures and having a plurality of source and drain regions therein; a plurality of channel regions located in the fins below the gate stack structures; characterized in that the stress layers have connected parts in the fins and that the channel regions enclose the connected parts. | 07-10-2014 |
20140231923 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present invention provides a semiconductor structure, comprising: a substrate; a gate stack located on the substrate and comprising at least a gate dielectric layer and a gate electrode layer; source/drain regions, located in the substrate on both sides of the gate stack; an STI structure, located in the substrate on both sides of the source/drain regions, wherein the cross-section of the STI structure is trapezoidal, Sigma-shaped or inverted trapezoidal depending on the type of the semiconductor structure. Correspondingly, the present invention further to provides a method of manufacturing the semiconductor structure. In the present invention, STI structures having different shapes can be combined with different stress fillers to apply tensile stress or compressive stress laterally to the channel, which will produce a positive impact on the electron mobility of NMOS and the hole mobility of PMOS and increase the channel current of the device, thereby effectively improving the performance of the semiconductor structure. | 08-21-2014 |
20150041925 | P TYPE MOSFET AND METHOD FOR MANUFACTURING THE SAME - Provided are P type MOSFETs and methods for manufacturing the same. The method may include forming source/drain regions in a semiconductor substrate; forming an interfacial oxide layer on the semiconductor substrate; forming a high K gate dielectric layer on the interfacial oxide layer; forming a first metal gate layer on the high K gate dielectric layer; implanting dopants into the first metal gate layer through conformal doping; and performing annealing to change an effective work function of a gate stack including the first metal gate layer, the high K gate dielectric, and the interfacial oxide layer. | 02-12-2015 |
20150048458 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - Provided are a semiconductor device and a method for manufacturing the same. The method may include: forming source/drain regions in a semiconductor substrate; forming an interfacial oxide layer on the semiconductor substrate; forming a high K gate dielectric layer on the interfacial oxide layer; forming a first metal gate layer on the high K gate dielectric layer; implanting dopant to the first metal gate layer through conformal doping; and performing annealing to change an effective work function of a gate stack comprising the first metal gate layer, the high K gate dielectric layer, and the interfacial oxide layer. | 02-19-2015 |
Patent application number | Description | Published |
20090087035 | Cartoon Face Generation - A face cartooning system is described. In one implementation, the system generates an attractive cartoon face or graphic of a user's facial image. The system extracts facial features separately and applies pixel-based techniques customized to each facial feature. The style of cartoon face achieved resembles the likeness of the user more than cartoons generated by conventional vector-based cartooning techniques. The cartoon faces thus achieved provide an attractive facial appearance and thus have wide applicability in art, gaming, and messaging applications in which a pleasing degree of realism is desirable without exaggerated comedy or caricature. | 04-02-2009 |
20090109236 | LOCALIZED COLOR TRANSFER - Techniques for providing localized color transfer are disclosed. In some aspects, a user may select a source region of a source image and a destination region of a destination image. The source region and the destination region may be associated by a designator to create a color transfer pair. A localized color transfer based on the color style of the source region may be implemented to modify the destination region color style. Further aspects may include optimizing the destination image to reduce discontinuities resulting from the color transfer and enabling the user to select regions of the destination image which are not modified by localized color transfer. | 04-30-2009 |
20090210939 | SKETCH-BASED PASSWORD AUTHENTICATION - A graphical password authentication method is based on sketches drawn by user. The method extracts a template edge orientation pattern from an initial sketch of the user and an input edge orientation pattern from an input sketch of the user, compares the similarity between the two edge orientation patterns, and makes an authentication decision based on the similarity. The edge orientations are quantized, and each edge orientation pattern includes a set of quantized orientation patterns each corresponding to one of the quantized edge orientations. The number of quantized edge orientations, as well as other parameters such as the dimension of the final orientation patterns and acceptance threshold, can be optimized either globally or user-specifically. | 08-20-2009 |
20090219286 | NON-LINEAR BEAM TRACING FOR COMPUTER GRAPHICS - A non-linear beam tracing technique that supports full non-linear beam tracing effects including multiple reflections and refractions for computer graphics applications. The technique introduces non-linear beam tracing to render non-linear ray tracing effects such as curved mirror reflection, refraction, caustics, and shadows. Beams are allowed to be non-linear where rays within the same beam are not parallel or do not intersect at a single point. Such is the case when a primary beam bounces off of a surface and spawns one or more secondary rays or beams. Secondary beams can be rendered in a similar manner to primary rays or beams via polygon streaming. Beyond smooth ray bundles, the technique can also be applied to incoherent ray bundles which is useful for rendering bump mapped surfaces. | 09-03-2009 |
20090252435 | CARTOON PERSONALIZATION - Embodiments that provide cartoon personalization are disclosed. In accordance with one embodiment, cartoon personalization includes selecting a face image having a pose orientation that substantially matches an original pose orientation of a character in a cartoon image. The method also includes replacing a face of the character in the cartoon image with the face image. The method further includes blending the face image with a remainder of the character in the cartoon image. | 10-08-2009 |
20100077319 | Presentation Facilitation - Multiple schemes and techniques for facilitating presentations with an interactive application are described. For example, an interactive application provides a console view overlay for integrating multiple productivity applications into a graphical user interface (GUI) window. An interactive application can also share a selected display portion of the console view overlay with other interactive applications. As another example, presenters and other audience members can draw on the selected display portion being shared, and the drawn graphics are synchronously displayed by the other interactive applications. Interactive applications, as directed by their users, can join various member groups and specific presentations thereof. Moreover, a user may share content in accordance with membership grouping. | 03-25-2010 |
20100313113 | Calibration and Annotation of Video Content - Various embodiments provide techniques for calibrating and annotating video content. In one or more embodiments, an instance of video content can be calibrated with one or more geographical models and/or existing calibrated video content to correlate the instance of video content with one or more geographical locations. According to some embodiments, geographical information can be used to annotate the video content. Geographical information can include identification information for one or more structures, natural features, and/or locations included in the video content. Some embodiments enable a particular instance of video content to be correlated with other instances of video content based on common geographical information and/or common annotation information. Thus, a user can access video content from other users with similar travel experiences and/or interests. A user may also access annotations provided by other users that may be relevant to a particular instance of video content. | 12-09-2010 |
20110283205 | AUTOMATED SOCIAL NETWORKING GRAPH MINING AND VISUALIZATION - The automated social networking graph mining and visualization technique described herein mines social connections and allows creation of a social networking graph from general (not necessarily social-application specific) Web pages. The technique uses the distances between a person's/entity's name and related people's/entities names on one or more Web pages to determine connections between people/entities and the strengths of the connections. In one embodiment, the technique lays out these connections, and then clusters them, in a 2-D layout of a social networking graph that represents the Web connection strengths among the related people's or entities' names, by using a force-directed model. | 11-17-2011 |
20110289015 | MOBILE DEVICE RECOMMENDATIONS - Users may browse web pages, interact with a plethora of applications, search for new content, and perform a wide variety of other tasks using a mobile device. Unfortunately, useful content may be difficult for a user to locate because of the large amount of content available (e.g. hundreds of thousands of applications within an application store). Accordingly, one or more systems and/or techniques for determining recommendations are disclosed herein. In particular, user input (e.g., text, numbers, etc.) and/or a user profile (e.g., contextual information relating to a user) may be used to determine a user intent. Recommendations may be determined based upon the user intent. For example, a user may input “I am hungry” using a mobile phone having a GPS location of Downtown and a noon timestamp. Using this information, an application allowing the user to make lunch reservations at local restaurants may be provided as a recommendation. | 11-24-2011 |
20120109754 | SPONSORED MULTI-MEDIA BLOGGING - The sponsored multi-media blogging technique is an advertising-driven service on a computing device, such as a mobile phone, that makes the multi-media micro-blog or blog an effective carrier for advertising. The data collected while employing the sponsored multi-media blogging technique is used for user intent mining and increasing advertisement relevance for mobile advertising projects. The benefits to the sponsored multi-media blogging technique's users are a natural interface for composing multi-media micro-blogs/blogs and instant experience sharing, while the benefits to advertisers is the promoted brand impression from the contextual advertising in rich media micro-blogs/blogs. | 05-03-2012 |
20120120097 | Clipart Cartoon Techniques - Techniques for generating a personalized cartoon by using a few text queries are described herein. The present disclosure describes efficiently searching multiple images from a network, obtaining clipart image from the multiple images, and vectorization of the clipart image. The present disclosure also describes techniques to change a style of the cartoon such as recoloring one or more cartoon objects. | 05-17-2012 |
20120130717 | Real-time Animation for an Expressive Avatar - Techniques for providing real-time animation for a personalized cartoon avatar are described. In one example, a process trains one or more animated models to provide a set of probabilistic motions of one or more upper body parts based on speech and motion data. The process links one or more predetermined phrases that represent emotional states to the one or more animated models. After creation of the models, the process receives real-time speech input. Next, the process identifies an emotional state to be expressed based on the one or more predetermined phrases matching in context to the real-time speech input. The process then generates an animated sequence of motions of the one or more upper body parts by applying the one or more animated models in response to the real-time speech input. | 05-24-2012 |
20120262552 | City scene video sharing on digital maps - A video sharing system is described to annotate and navigate tourist videos. An example video sharing system enables non-linear browsing of multiple videos and enriches the browsing experience with contextual and geographic information. | 10-18-2012 |
20120294520 | GESTURE-BASED VISUAL SEARCH - A user may perform an image search on an object shown in an image. The user may use a mobile device to display an image. In response to displaying the image, the client device may send the image to a visual search system for image segmentation. Upon receiving a segmented image from the visual search system, the client device may display the segmented image to the user who may select one or more segments including an object of interest to instantiate a search. The visual search system may formulate a search query based on the one or more selected segments and perform a search using the search query. The visual search system may then return search results to the client device for display to the user. | 11-22-2012 |
20120295640 | User Behavior Model for Contextual Personalized Recommendation - A user behavior model provides personalized recommendations based in part on time and location, particularly to users of mobile devices. Entity types are ranked according to relevance to the user. Example entity types are restaurant, hotel, etc. The relevance may be based on reference to a large-scale database containing queries from other users. Additionally, entities within each entity type may be ranked based on relevance to the user and the time and location context. A user interface may display a ranked list of entity types, such as restaurant, hotel, etc., wherein each entity type is represented by a highest-ranked entity with the entity type. Thus, the user interface may display a highest-ranked restaurant, a highest-ranked hotel, etc. Upon user selection of one such entity type the user interface is replaced with a second user interface, for example showing a ranked hierarchy of restaurants, headed by the highest-ranked restaurant. | 11-22-2012 |
20140003714 | GESTURE-BASED VISUAL SEARCH | 01-02-2014 |
20140289228 | USER BEHAVIOR MODEL FOR CONTEXTUAL PERSONALIZED RECOMMENDATION - A user behavior model provides personalized recommendations based in part on time and location, particularly to users of mobile devices. Entity types are ranked according to relevance to the user. Example entity types are restaurant, hotel, etc. The relevance may be based on reference to a large-scale database containing queries from other users. Additionally, entities within each entity type may be ranked based on relevance to the user and the time and location context. A user interface may display a ranked list of entity types, such as restaurant, hotel, etc., wherein each entity type is represented by a highest-ranked entity with the entity type. Thus, the user interface may display a highest-ranked restaurant, a highest-ranked hotel, etc. Upon user selection of one such entity type the user interface is replaced with a second user interface, for example showing a ranked hierarchy of restaurants, headed by the highest-ranked restaurant. | 09-25-2014 |
Patent application number | Description | Published |
20100213102 | CATALYTIC CONVERSION PROCESS - A catalytic conversion process which comprises catalytic cracking reaction of a hydrocarbon feedstock contacting with a medium pore size zeolite enriched catalyst in a reactor, characterized in that reaction temperature, weight hourly space velocity and catalyst/feedstock ratio by weight are sufficient to achieve a yield of fluid catalytic cracking gas oil between 12% and 60% by weight of said feedstock, wherein said weight hourly space velocity is between 25 h | 08-26-2010 |
20100248942 | CATALYST REGENERATION PROCESS FOR IMPROVING CATALYST SELECTIVITY - The object of the present invention is to provide a catalyst regeneration process which can improve catalyst selectivity. A first aspect of the invention is characterized in that a spent catalyst from a reactor is introduced into a first fluidized bed regenerator and contacted with an oxygen-containing gas stream and optional steam to carry out a coke combustion reaction, wherein the resultant mixture of the partially regenerated catalyst and flue gas is introduced into a second fluidized bed regenerator and contacted with steam and an optional oxygen-containing gas stream to carry out a further regeneration reaction, and then the regenerated catalyst is introduced into the reactor. A second aspect of the invention is characterized in that a spent catalyst from a reactor is introduced into a fluidized dense bed regenerator and contacted with an oxygen-containing gas stream and steam to carry out a coke combustion reaction, and then the regenerated catalyst is introduced into the reactor. The inventive processes result in a more uniform distribution of the regenerated catalyst activity; due to the exposure of the catalyst to a low temperature for a long time, a part of the heavy metals are buried by the matrix and the remaining are passivated. Thereby dry gas and coke yields decrease sharply when hydrocarbons are subjected to a catalytic cracking reaction on the regenerated catalyst. | 09-30-2010 |
20100326888 | CATALYTIC CRACKING CATALYST HAVING A HIGHER SELECTIVITY, PROCESSING METHOD AND USE THEREOF - The present invention provides a catalytic cracking catalyst, processing method and use thereof. When the catalyst is added into a commercial catalytic cracking unit, it has an initial activity of not higher than 80, preferably not higher than 75, more preferably not higher than 70, a self-balancing time of 0.1-50 h, and an equilibrium activity of 35-60. Said method enables the activity and selectivity of the catalyst in the catalytic cracking unit to be more homogeneous and notably improves the selectivity of the catalytic cracking catalyst, so as to obviously reduce the dry gas and coke yields, to sufficiently use steam and to reduce the energy consumption of the FCC unit. | 12-30-2010 |
20110000818 | PROCESS FOR CONVERTING INFERIOR FEEDSTOCK TO HIGH QUALITY FUEL OIL - A catalytic conversion process can convert inferior feedstock to high quality fuel oil and propylene. A inferior feedstock is introduced into first and second reactor zone, wherein the feedstock carry out first step and second step reactions by contacting with catalytic conversion catalyst. Product vapors separate from spent catalyst by gas-solid separation. The spent catalyst is stripped, regenerated by burning off coke and then returns to reactor. The product vapors are introduced into separation system to obtain propylene, gasoline, diesel, fluid catalytic cracking gas oil (FGO) and other products. The FGO is introduced into hydrotreating unit and/or extraction unit to obtain hydrotreated FGO and/or extracted FGO. Said hyrotreated FGO and/or extracted FGO return to the first reactor zone and/or another catalytic cracking unit to obtain propylene and gasoline. The extracted oil of said FGO is rich in double ring aromatics which are good chemical materials. The raffinate of said FGO is rich in chain alkane and cycloalkane which are suitable for catalytic cracking. More particularly, the invention relates to a process to utilize petroleum oil resources efficiently for decreasing the yield of dry gas and coke significantly. | 01-06-2011 |
20110073523 | CATALYTIC CONVERSION PROCESS FOR PRODUCING MORE DIESEL AND PROPYLENE - The present invention relates to a catalytic conversion process for producing more diesel and propylene, comprising contacting the feedstock oil with a catalyst having a relatively homogeneous activity in a reactor, wherein the reaction temperature, weight hourly space velocity and weight ratio of the catalyst/feedstock oil are sufficient to obtain a reaction product containing from 12 to 60% by weight of a fluid catalytic cracking gas oil relative to the weight of the feedstock oil; the fluid catalytic cracking gas oil is fed into the fluid catalytic cracking gas oil treatment device for further processing. Catalytic cracking, hydrogenation, solvent extraction, hydrocracking and process for producing more diesel are organically combined together, and hydrocarbons such as alkanes, alkyl side chains in the feedstocks for catalysis are selectively cracked and isomerized. Meanwhile, aromatics in the feedstocks, which enter into the diesel fraction, are minimized, and the retention of other components in the diesel fraction by the production of aromatics via the reaction such as aromatization and the like is avoided. While the feedstocks are converted into high cetane number diesel and propylene, the yields of dry gas and coke are significantly reduced, and the breaking tendency and consumption of the catalyst are decreased. | 03-31-2011 |
20130001129 | CATALYTIC CONVERSION METHOD FOR INCREASING CETANE NUMBER BARREL OF DIESEL - A catalytic conversion process for increasing the cetane number barrel of diesel, in which contacting the feedstock oil with a catalytic cracking catalyst having a relatively homogeneous activity containing mainly the large pore zeolites in a catalytic conversion reactor, wherein the reaction temperature, residence time of oil vapors and weight ratio of the catalyst/feedstock oil are sufficient to obtain a reaction product containing from about 12 to about 60% by weight of a fluid catalytic cracking gas oil relative to the weight of the feedstock oil and containing a diesel; the reaction temperature ranges from about 420° C. to about 550° C.; the residence time of oil vapors ranges from about 0.1 to about 5 seconds; the weight ratio of the catalytic cracking catalyst/feedstock oil is about 1-about 10. The fluid catalytic cracking gas oil is fed into other unit for further treatment or is fed back to the initial catalytic conversion reactor. The process allows the maximum production of high cetane number diesel, the cracking catalyst having a coarse particle size distribution can further improve the selectivity of dry gas and coke, and can reduce the breaking tendency of the catalyst and the consumption of the catalyst. | 01-03-2013 |
20130211167 | CATALYTIC CONVERSION METHOD FOR IMPROVING PRODUCT DISTRIBUTION - The present invention relates to a catalytic conversion process for improving the product distribution, characterized in that a feedstock oil of good quality is contacted with a hot regenerated catalyst having a lower activity in a reactor to carry out a cracking reaction, the reaction product is separated from the spent catalyst to be regenerated, then the reaction product is fed into a separation system, and the spent catalyst to be regenerated is stripped, regenerated and recycled in the process. The isobutene content in the liquefied petroleum gas (LPG) produced by the process is increased by a factor of more than 30%, and the olefin content in the gasoline composition may be increased to more than 30 wt. %. The product distribution is optimized, and the yields of dry gas and coke are decreased, so as to sufficiently utilize the petroleum resources. | 08-15-2013 |
Patent application number | Description | Published |
20080296582 | TFT-LCD ARRAY SUBSTRATE - A thin film transistor liquid crystal display (TFT-LCD) array substrate with a repairable pixel structure is provided. The array substrate comprises a gate line and a data line, and the gate line and the data line intersect with each other to define a pixel unit. The pixel unit comprises a TFT and a pixel electrode, and a spare source electrode, a spare drain electrode, and a spare channel region are formed alongside a channel region of the TFT to form a spare TFT. | 12-04-2008 |
20090058781 | GATE DRIVING DEVICE FOR LIQUID CRYSTAL DISPLAY - The invention relates to a gate driving device for Thin Film Transistor liquid crystal display comprising: a plurality of shift registers directly deposited on an array substrate, said shift registers being composed of effect transistors and a capacitor, obtaining a gate driving signal voltage by controlling an input signal. Said shift register can be realized by 5-layer mask process or 4-layer mask process, by arranging the field effect transistors on the margin part outside the active region on the substrate or at the edge of the substrate, and then directly depositing them on an array substrate. The invention obtains a gate driving signal voltage by the shift registers directly deposited on the substrate, thus overcoming the shortage of the need of driving chips and film layers in the prior art, substantially reducing the production cost for LCD. | 03-05-2009 |
20100245337 | SHIFT REGISTER AND A GATE-LINE DRIVE DEVICE THEREFOR - A shift register and a gate-line drive device relate to liquid crystal display. The shift register comprises: first thin film transistor, second thin film transistor, third thin film transistor, fourth thin film transistor and fifth thin film transistor; capacitor, connected between first node and the output terminal of the present stage; first operation modular, connected between first operation signal terminal and the first node, and connected to the low level signal terminal; second operation modular, connected between second operation signal terminal and the first node, and connected to the low level signal terminal, wherein, the first operation modular and the second operation modular are alternatively operated, and the first operation modular and the second operation modular are used to maintain both of the gate and drain of the second thin film transistor at low level respectively, when the shift register is not operated. | 09-30-2010 |
20110019117 | TFT-LCD ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - A thin film transistor liquid crystal display (TFT-LCD) array substrate comprising a first gate line, a second gate line and a data line, which are formed on a substrate and define a pixel region, the first and second gate lines being parallel to each other, a pixel electrode, and a first thin film transistor (TFT) and a second TFT provided in the pixel region. The first TFT comprises a first gate electrode and a first drain electrode, the second TFT comprises a second gate electrode and a second drain electrode, and parasitic capacitance generated between the first drain electrode and the first gate electrode is equal to parasitic capacitance generated between the second drain electrode and the second gate electrode. Both the first drain electrode and the second drain electrode are connected with the pixel electrode. When an “ON” voltage is supplied to the first TFT via the first gate line, a first voltage is supplied to the second TFT via the second gate line; when an “OFF” voltage is supplied to the first TFT via the first gate line, a second voltage is supplied to the second TFT via the second gate line, wherein the “ON” voltage−the “OFF” voltage=the second voltage−the first voltage. | 01-27-2011 |
20120081415 | ARRAY SUBSTRATE AND DRIVING METHOD THEREOF - An array substrate is provided comprising a base substrate; an array of pixel electrodes formed on the base substrate; a plurality of gate lines, each of which is formed corresponding to each row of pixel electrodes; a plurality of data lines, each of which is formed corresponding to each odd number column of pixel electrodes and the next adjacent even number column of pixel electrodes; a plurality of first switching devices, each of which is connected with each odd-number-column pixel electrode, and the data lines charging the corresponding odd-number-column pixel electrodes via the corresponding first switching devices under driving control in corresponding time sequence; a plurality of second switching devices, each of which is connected with each even-number-column pixel electrode, and the data lines charging the corresponding even-number-column pixel electrodes via the corresponding second switching devices under driving control in corresponding time sequence. | 04-05-2012 |
20120092312 | DRIVING METHOD FOR COMMON ELECTRODES, CIRCUIT AND LIQUID CRYSTAL DISPLAY THEREOF - A common electrode driving method, comprises: generating a first common electrode signal to be applied to a storage electrode line of each row of pixels on an array substrate, and a second common electrode signal to be applied to a common electrode forming a liquid crystal capacitance with pixel electrodes of each row of pixels on the array substrate, the first common electrode signal being opposite to a gate signal for gate electrodes applied to the corresponding row of pixels in terms of transition timing; and inputting the first common electrode signal to each row of pixels, and inputting the second common electrode signal to the common electrode. | 04-19-2012 |
20120161140 | TFT ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - An thin film transistor array and a manufacturing method thereof are provided. A thin film transistor (TFT) array substrate comprises a base substrate, horizontal gate lines, reticulated storage capacitor electrode (Vcom) lines, longitudinal data lines defining pixel units with the horizontal gate lines. The Vcom lines corresponding to the pixel units in each row of the reticulated Vcom line are connected with each other, and the reticulated Vcom lines are connected with an integrated-circuit (IC) element through Vcom line IC terminals; if the number of the data lines is N, the number of the Vcom line IC terminals is more than 0 and less than N+1; and at least one Vcom line longitudinal electric connection section is provided between the Vcom lines in two adjacent rows. | 06-28-2012 |
20140071366 | TFT-LCD ARRAY SUBSTRATE - A thin film transistor liquid crystal display (TFT-LCD) array substrate with a repairable pixel structure is provided. The array substrate comprises a gate line and a data line, and the gate line and the data line intersect with each other to define a pixel unit. The pixel unit comprises a TFT and a pixel electrode, and a spare source electrode, a spare drain electrode, and a spare channel region are formed alongside a channel region of the TFT to form a spare TFT. | 03-13-2014 |
20140131718 | TFT ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF - A thin film transistor (TFT) array substrate is disclosed and having a pixel region and a peripheral region surrounding the pixel region, and the pixel region comprises horizontal gate lines, longitudinal data lines defining pixel units with the horizontal gate lines, and storage capacitor electrode (Vcom) lines. The peripheral region comprises at least one peripheral common electrode line which is electrically connected with an integrated-circuit (IC) element. The Vcom lines are connected with the peripheral common electrode line through one or more Vcom line IC terminals. | 05-15-2014 |
20140253607 | ARRAY SUBSTRATE AND DRIVING METHOD THEREOF - An array substrate is provided comprising a base substrate; an array of pixel electrodes formed on the base substrate; a plurality of gate lines, each of which is formed corresponding to each row of pixel electrodes; a plurality of data lines, each of which is formed corresponding to each odd number column of pixel electrodes and the next adjacent even number column of pixel electrodes; a plurality of first switching devices, each of which is connected with each odd-number-column pixel electrode, and the data lines charging the corresponding odd-number-column pixel electrodes via the corresponding first switching devices under driving control in corresponding time sequence; a plurality of second switching devices, each of which is connected with each even-number-column pixel electrode, and the data lines charging the corresponding even-number-column pixel electrodes via the corresponding second switching devices under driving control in corresponding time sequence. | 09-11-2014 |
20140320767 | CAPACITIVE IN-CELL TOUCH PANEL AND DISPLAY DEVICE - Embodiments of the invention disclose a capacitive in-cell touch panel and a display device. The touch panel includes an array substrate and a counter substrate, the array substrate includes: pixels defined by gate lines and data lines and a common electrode corresponding to each pixel. All the common electrodes are divided into a plurality of first common electrode groups arranged in a row direction and a plurality of second common electrode groups arranged in a column direction; a plurality of metal wires disposed in a same metal layer, wherein all the metal wires are divided into a plurality of first metal wire groups arranged in the row direction and a plurality of second metal wire groups arranged in the column direction; the first metal wire groups in a direction of a same row are electrically connected to each other, and are electrically connected to first common electrode groups corresponding to them in position, respectively, so as to form a driving line; the second metal wire groups in a direction of a same column are electrically connected to each other, and are electrically connected to second common electrode groups corresponding to them in position, respectively, so as to form a sensing line. | 10-30-2014 |
20150029118 | CAPACITIVE TOUCH MODULE, CAPACITIVE IN-CELL TOUCH SCREEN PANEL AND DISPLAY DEVICE - The present invention discloses a capacitive touch module, a capacitive in-cell touch screen panel and a display device, in which an integrally connected common electrode layer in an array substrate is split to form touch sensing electrodes and touch driving electrodes which are insulated from each other; and the touch driving electrodes and the touch sensing electrodes are subjected to time-sharing drive to achieve the touch function and the display function. Moreover, each touch sensing electrode includes a plurality of touch sensing sub-electrodes; each touch driving electrode includes a plurality of touch driving sub-electrodes; and opposing sides of adjacent touch sensing sub-electrodes and touch driving sub-electrodes are broken lines. Therefore, the opposing area between the adjacent touch driving electrodes and the adjacent touch sensing electrodes can be increased, and hence the mutual capacitance between the touch driving electrodes and the touch sensing electrodes within the unit area can be increased, and consequently the sensing sensitivity of the touch screen in the touch-control process can be improved. | 01-29-2015 |