Patent application number | Description | Published |
20080293339 | Retainer Ring - A retainer ring and a method of using the retainer ring are provided. The retainer ring has openings along a bottom surface. Grooves encompass the openings and extend to an interior portion of the retainer ring wherein a semiconductor wafer may be held. In operation, a semiconductor wafer is placed inside the retainer ring. As the retainer ring and the semiconductor wafer are moved relative to an underlying polishing pad, slurry is dispensed through the openings in the retainer ring. The grooves in the retainer ring allow the slurry to flow from the openings to the interior portion of the retainer ring and the semiconductor wafer. | 11-27-2008 |
20100109098 | GATE STRUCTURE INCLUDING MODIFIED HIGH-K GATE DIELECTRIC AND METAL GATE INTERFACE - A method of fabricating a gate of a semiconductor device is provided. In an embodiment, the method includes forming a gate dielectric layer on a semiconductor substrate. An interface layer is formed on the gate dielectric layer. In an embodiment, the gate dielectric layer includes HfO | 05-06-2010 |
20100112912 | Retainer Ring - A retainer ring and a method of using the retainer ring are provided. The retainer ring has openings along a bottom surface. Grooves encompass the openings and extend to an interior portion of the retainer ring wherein a semiconductor wafer may be held. In operation, a semiconductor wafer is placed inside the retainer ring. As the retainer ring and the semiconductor wafer are moved relative to an underlying polishing pad, slurry is dispensed through the openings in the retainer ring. The grooves in the retainer ring allow the slurry to flow from the openings to the interior portion of the retainer ring and the semiconductor wafer. | 05-06-2010 |
20100140716 | N/P METAL CRYSTAL ORIENTATION FOR HIGH-K METAL GATE Vt MODULATION - The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having a first region and a second region; a first gate stack of an n-type field-effect transistor (FET) in the first region; and a second gate stack of a p-type FET in the second region. The first gate stack includes a high k dielectric layer on the semiconductor substrate, a first crystalline metal layer in a first orientation on the high k dielectric layer, and a conductive material layer on the first crystalline metal layer. The second gate stack includes the high k dielectric layer on the semiconductor substrate, a second crystalline metal layer in a second orientation on the high k dielectric layer, and the conductive material layer on the second crystalline metal layer. | 06-10-2010 |
20100163078 | SPINNER AND METHOD OF CLEANING SUBSTRATE USING THE SPINNER - A method includes spinning a semiconductor wafer about an axis normal to a major surface of the wafer. The wafer is translated in a direction parallel to the major surface with an oscillatory motion, while spinning the wafer. A material is sprayed from first and second nozzles or orifices at respective first and second locations on the major surface of the wafer simultaneously while spinning the wafer and translating the wafer. | 07-01-2010 |
20100167506 | INDUCTIVE PLASMA DOPING - In some embodiments, a method of doping a semiconductor wafer disposed on a pedestal electrode in an inductive plasma chamber includes generating a plasma having a first voltage with respect to ground in the inductive plasma chamber, and applying a radio frequency (RF) voltage with respect to ground to the pedestal electrode in the inductive plasma chamber. The positive RF voltage is based on the first voltage of the plasma. | 07-01-2010 |
20100178772 | METHOD OF FABRICATING HIGH-K METAL GATE DEVICES - The present disclosure provides a method for fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a first metal layer and a first silicon layer by an in-situ deposition process, patterning the first silicon layer to remove a portion overlying the second region, patterning the first metal layer using the patterned first silicon layer as a mask, and removing the patterned first silicon layer including applying a solution. The solution includes a first component having an [F—] concentration greater than 0.01 M, a second component configured to adjust a pH of the solution from about 4.3 to about 6.7, and a third component configured to adjust a potential of the solution to be greater than −1.4 volts. | 07-15-2010 |
20100187444 | FIELD-BY-FIELD LASER ANNEALING AND FEED FORWARD PROCESS CONTROL - A method includes dividing a semiconductor wafer into a plurality of dies areas, generating a map of the semiconductor wafer, scanning each of the plurality of die areas of the semiconductor wafer with a laser, and adjusting a parameter of the laser during the scanning based on a value of the die areas identified by the map of the semiconductor wafer. The map characterizing the die areas based on a first measurement of each individual die area. | 07-29-2010 |
20100210189 | SLURRY DISPENSER FOR CHEMICAL MECHANICAL POLISHING (CMP) APPARATUS AND METHOD - A chemical mechanical polishing method and apparatus provides a deformable, telescoping slurry dispenser arm coupled to a dispenser head that may be arcuate in shape and may also be a bendable telescoping member that can be adjusted to vary the number of slurry dispenser ports and the degree of curvature of the dispenser head. The dispenser arm may additionally include slurry dispenser ports therein. The dispenser arm may advantageously be formed of a plurality of nested tubes that are slidable with respect to one another. The adjustable dispenser arm may pivot about a pivot point and can be variously positioned to accommodate different sized polishing pads used to polish substrates of different dimensions and the bendable, telescoping slurry dispenser arm and dispenser head provide uniform slurry distribution to any of various wafer polishing locations, effective slurry usage and uniform polishing profiles in each case. | 08-19-2010 |
20100221849 | METHOD AND SYSTEM FOR CONTROLLING AN IMPLANTATION PROCESS - A method for implant uniformity is provided that includes determining a variation of critical dimensions (CD) of a semiconductor wafer, moving the semiconductor wafer in a two-dimensional mode during an implantation process, and controlling a velocity of the movement of the semiconductor wafer so that an implant dose to the semiconductor wafer is varied based on the variation of CD. | 09-02-2010 |
20100267172 | Formation of Shallow Trench Isolation Using Chemical Vapor Etch - A method includes measuring a depth of a shallow trench isolation (STI) region below a surface of a substrate. The STI region is filled with an oxide material. The substrate has a nitride layer above the surface. A thickness of the nitride layer is measured. A first chemical vapor etch (CVE) of the oxide material is performed, to partially form a recess in the STI region. The first CVE removes an amount of the oxide material less than the thickness of the nitride layer. The nitride layer is removed by dry etching. A remaining height of the STI region is measured after removing the nitride. A second CVE of the oxide material in the STI region is performed, based on the measured depth and the remaining height, to form at least one fin having a desired fin height above the oxide in the STI region without an oxide fence. | 10-21-2010 |
20100288369 | Piping System And Control For Semiconductor Processing - A vacuum system for semiconductor fabrication. The system includes a vacuum chamber for performing a semiconductor fabrication process, a vacuum source, and a piping system fluidly connecting the vacuum chamber to the vacuum source. In one embodiment, the piping system is configured without a horizontal flow path section of piping. In some embodiments, the piping system includes a first piping branch and a second piping branch. The first and second piping branches preferably have a symmetrical configuration with respect to the vacuum source. In yet other embodiments, the first and second piping branches preferably each include a throttle valve. | 11-18-2010 |
20100291751 | METHOD FOR FABRICATING AN ISOLATION STRUCTURE - The invention relates to integrated circuit fabrication, and more particularly to an electronic device with an isolation structure made having almost no void. An exemplary method for fabricating an isolation structure, comprising: providing a substrate; forming a trench in the substrate; partially filling the trench with a first silicon oxide; exposing a surface of the first silicon oxide to a vapor mixture comprising NH3 and a fluorine-containing compound; heating the substrate to a temperature between 100° C. to 200° C.; and filling the trench with a second silicon oxide, whereby the isolation structure made has almost no void. | 11-18-2010 |
20100291840 | SYSTEM AND METHOD FOR CONDITIONING CHEMICAL MECHANICAL POLISHING APPARATUS USING MULTIPLE CONDITIONING DISKS - A chemical mechanical polishing (CMP) apparatus provides for polishing semiconductor wafers and for conditioning the polishing pad of the CMP apparatus using multiple conditioning disks at the same time. The conditioning disks may be moved together or independently along the surface of polishing pad to condition the entire surface of the rotating polishing pad. | 11-18-2010 |
20110086504 | METHODS FOR FORMING INTEGRATED CIRCUITS - A method for forming an integrated circuit is provided. The method includes forming a gate dielectric structure over a substrate. A titanium-containing sacrificial layer is formed, contacting the gate dielectric structure. The whole titanium-containing sacrificial layer is substantially removed. | 04-14-2011 |
20110156166 | High Temperature Anneal for Aluminum Surface Protection - The present disclosure also provides another embodiment of a method for making metal gate stacks. The method includes forming a first dummy gate and a second dummy gate on a substrate; removing a polysilicon layer from the first dummy gate, resulting in a first gate trench; forming a first metal layer and a first aluminum layer in the first gate trench; applying a chemical mechanical polishing (CMP) process to the substrate; performing an annealing process to the first aluminum layer using a nitrogen and oxygen containing gas, forming an interfacial layer of aluminum, nitrogen and oxygen on the first aluminum layer; thereafter removing the polysilicon layer from the second dummy gate, resulting in a second gate trench; and forming a second metal layer and a second aluminum layer on the second metal layer in the second gate trench. | 06-30-2011 |
20110195570 | INTEGRATION OF BOTTOM-UP METAL FILM DEPOSITION - The described embodiments of methods of bottom-up metal deposition to fill interconnect and replacement gate structures enable gap-filling of fine features with high aspect ratios without voids and provide metal films with good film quality. In-situ pretreatment of metal film(s) deposited by gas cluster ion beam (GCIB) allows removal of surface impurities and surface oxide to improve adhesion between an underlying layer with the deposited metal film(s). Metal films deposited by photo-induced chemical vapor deposition (PI-CVD) using high energy of low-frequency light source(s) at relatively low temperature exhibit liquid-like nature, which allows the metal films to fill fine feature from bottom up. The post deposition annealing of metal film(s) deposited by PI-CVD densifies the metal film(s) and removes residual gaseous species from the metal film(s). For advanced manufacturing, such bottom-up metal deposition methods address the challenges of gap-filling of fine features with high aspect ratios. | 08-11-2011 |
20120064715 | INTEGRATION OF BOTTOM-UP METAL FILM DEPOSITION - A method of depositing a metal film on a substrate with patterned features includes placing a substrate with patterned features into a photo-induced chemical vapor deposition (PI-CVD) process chamber. The method also includes depositing a metal film by PI-CVD to fill the patterned features from bottom up. | 03-15-2012 |
20120086075 | DEVICE WITH ALUMINUM SURFACE PROTECTION - A semiconductor structure with a metal gate structure includes a first type field-effect transistor having a first gate including: a high k dielectric material on a substrate, a first metal layer on the high k dielectric material layer and having a first work function, and a first aluminum layer on the first metal layer. The first aluminum layer includes an interfacial layer including aluminum, nitrogen and oxygen. The device also includes a second type field-effect transistor having a second gate including: the high k dielectric material on the substrate, a second metal layer on the high k dielectric material layer and having a second work function different from the first work function, and a second aluminum layer on the second metal layer. | 04-12-2012 |
20120104435 | REFRACTIVE INDEX TUNING OF WAFER LEVEL PACKAGE LEDS - Two or more molded ellipsoid lenses are formed on a packaged LED die by injecting a glue material into a mold over the LED die and curing the glue material. After curing, the refractive index of the lens in contact with the LED die is greater than the refractive index of the lens not directly contacting the LED die. At least one phosphor material is incorporated into the glue material for at least one of the lenses not directly contacting the LED die. The lens directly contacting the LED die may also include one or more phosphor material. A high refractive index coating may be applied between the LED die and the lens. | 05-03-2012 |
20120119228 | LED DEVICE WITH IMPROVED THERMAL PERFORMANCE - An apparatus includes a wafer with a number of openings therein. For each opening, an LED device is coupled to a conductive carrier and the wafer in a manner so that each of the coupled LED device and a portion of the conductive carrier at least partially fill the opening. A method of fabricating an LED device includes forming a number of openings in a wafer. The method also includes coupling light-emitting diode (LED) devices to conductive carriers. The LED devices with conductive carriers at least partially fill each of the openings. | 05-17-2012 |
20120205694 | METHOD OF FORMING A LIGHT EMITTING DIODE EMITTER SUBSTRATE WITH HIGHLY REFLECTIVE METAL BONDING - The present disclosure provides one embodiment of a method for fabricating a light emitting diode (LED) package. The method includes forming a plurality of through silicon vias (TSVs) on a silicon substrate; depositing a dielectric layer over a first side and a second side of the silicon substrate and over sidewall surfaces of the TSVs; forming a metal layer patterned over the dielectric layer on the first side and the second side of the silicon substrate and further filling the TSVs; and forming a plurality of highly reflective bonding pads over the metal layer on the second side of the silicon substrate for LED bonding and wire bonding. | 08-16-2012 |
20120228650 | Light Emitting Diode Emitter Substrate with Highly Reflective Metal Bonding - The present disclosure provides one embodiment of a method for fabricating a light emitting diode (LED) package. The method includes forming a plurality of through silicon vias (TSVs) on a silicon substrate; depositing a dielectric layer over a first side and a second side of the silicon substrate and over sidewall surfaces of the TSVs; forming a metal layer patterned over the dielectric layer on the first side and the second side of the silicon substrate and further filling the TSVs; and forming a plurality of highly reflective bonding pads over the metal layer on the second side of the silicon substrate for LED bonding and wire bonding. | 09-13-2012 |
20120244652 | METHODS OF FABRICATING LIGHT EMITTING DIODE DEVICES - An embodiment of the disclosure includes a method of fabricating a plurality of light emitting diode devices. A plurality of LED dies is provided. The LED dies are bonded to a carrier substrate. A patterned mask layer comprising a plurality of openings is formed on the carrier substrate. Each one of the plurality of LED dies is exposed through one of the plurality of the openings respectively. Each of the plurality of openings is filled with a phosphor. The phosphor is cured. The phosphor and the patterned mask layer are polished to thin the phosphor covering each of the plurality of LED dies. The patterned mask layer is removed after polishing the phosphor. | 09-27-2012 |
20120256187 | DOUBLE SUBSTRATE MULTI-JUNCTION LIGHT EMITTING DIODE ARRAY STRUCTURE - The present disclosure provides one embodiment of a light-emitting structure. The light-emitting structure includes a carrier substrate having first metal features; a transparent substrate having second metal features; a plurality of light-emitting diodes (LEDs) bonded with the carrier substrate and the transparent substrate, sandwiched between the carrier substrate and the transparent substrate; and metal pillars bonded to the carrier substrate and the transparent substrate, each of the metal pillars being disposed between adjacent two of the plurality of LEDs, wherein the first metal features, the second metal features and the metal pillars are configured to electrically connect the plurality of LEDs. | 10-11-2012 |
20120264296 | METHODS OF FORMING THROUGH SILICON VIA OPENINGS - A method of forming a through-silicon-via (TSV) opening includes forming a TSV opening through a substrate. A recast of a material of the substrate on sidewalls of the TSV opening is removed with a first chemical. The sidewalls of the TSV opening are cleaned with a second chemical by substantially removing a residue of the first chemical. | 10-18-2012 |
20120286240 | Methods of Fabricating Light Emitting Diode Packages - An LED array comprises a growth substrate and at least two separated LED dies grown over the growth substrate. Each of LED dies sequentially comprise a first conductive type doped layer, a multiple quantum well layer and a second conductive type doped layer. The LED array is bonded to a carrier substrate. Each of separated LED dies on the LED array is simultaneously bonded to the carrier substrate. The second conductive type doped layer of each of separated LED dies is proximate to the carrier substrate. The first conductive type doped layer of each of LED dies is exposed. A patterned isolation layer is formed over each of LED dies and the carrier substrate. Conductive interconnects are formed over the patterned isolation layer to electrically connect the at least separated LED dies and each of LED dies to the carrier substrate. | 11-15-2012 |
20120292629 | LIGHT EMITTING DIODE AND METHOD OF FABRICATION THEREOF - A method includes providing an LED element including a substrate and a gallium nitride (GaN) layer disposed on the substrate. The GaN layer is treated. The treatment includes performing an ion implantation process on the GaN layer. The ion implantation process may provide a roughened surface region of the GaN layer. In an embodiment, the ion implantation process is performed at a temperature of less than approximately 25 degrees Celsius. In a further embodiment, the substrate is at a temperature less than approximately zero degrees Celsius during the ion implantation process. | 11-22-2012 |
20120305956 | LED PHOSPHOR PATTERNING - The present disclosure provides a method of patterning a phosphor layer on a light emitting diode (LED) emitter. The method includes providing at least one LED emitter disposed on a substrate; forming a polymer layer over the at least one LED emitter; providing a mask over the polymer layer and the at least one LED emitter; etching the polymer layer through the mask to expose the at least one LED emitter within a cavity having polymer layer walls; and coating the at least one LED emitter with phosphor. | 12-06-2012 |
20130089937 | METHOD AND APPARATUS FOR ACCURATE DIE-TO-WAFER BONDING - A method of light-emitting diode (LED) packaging includes coupling a number of LED dies to corresponding bonding pads on a sub-mount. A mold apparatus having concave recesses housing LED dies is placed over the sub-mount. The sub-mount, the LED dies, and the mold apparatus are heated in a thermal reflow process to bond the LED dies to the bonding pads. Each recess substantially restricts shifting of the LED die with respect to the bonding pad during the heating. | 04-11-2013 |
20130171746 | MULTI-ZONE TEMPERATURE CONTROL FOR SEMICONDUCTOR WAFER - An apparatus and a method for controlling critical dimension (CD) of a circuit is provided. An apparatus includes a controller for receiving CD measurements at respective locations in a circuit pattern in an etched film on a first substrate and a single wafer chamber for forming a second film of the film material on a second substrate. The single wafer chamber is responsive to a signal from the controller to locally adjust a thickness of the second film based on the measured CD's. A method provides for etching a circuit pattern of a film on a first substrate, measuring CD's of the circuit pattern, adjusting a single wafer chamber to form a second film on a second semiconductor substrate based on the measured CD. The second film thickness is locally adjusted based on the measured CD's. | 07-04-2013 |
20130171803 | METHOD FOR FABRICATING AN ISOLATION STRUCTURE - A method of fabricating an isolation structure including forming a trench in a top surface of a substrate and partially filling the trench with a first oxide, wherein the first oxide is a pure oxide. Partially filling the trench includes forming a liner layer in the trench and forming the first oxide over the liner layer using silane and oxygen precursors at a pressure less than 10 milliTorr (mTorr) and a temperature ranging from about 500° C. to about 1000° C. The method further includes producing a solid reaction product in a top portion of the first oxide. The method further includes sublimating the solid reaction product by heating the substrate in a chamber at a temperature from 100° C. to 200° C. and removing the sublimated solid reaction product by flowing a carrier gas over the substrate. The method further includes filling the trench with a second oxide. | 07-04-2013 |
20130260484 | OPTIMIZING LIGHT EXTRACTION EFFICIENCY FOR AN LED WAFER - The present disclosure involves a method of fabricating a light-emitting diode (LED) wafer. The method first determines a target surface morphology for the LED wafer. The target surface morphology yields a maximum light output for LEDs on the LED wafer. The LED wafer is etched to form a roughened wafer surface. Thereafter, using a laser scanning microscope, the method investigates an actual surface morphology of the LED wafer. Afterwards, if the actual surface morphology differs from the target surface morphology beyond an acceptable limit, the method repeats the etching step one or more times. The etching is repeated by adjusting one or more etching parameters. | 10-03-2013 |
20130270617 | INTEGRATION OF BOTTOM-UP METAL FILM DEPOSITION - A gate structure including a substrate and a gate dielectric layer formed over the substrate. The gate structure further includes a workfunction layer over the gate dielectric layer and spacers enclosing the gate dielectric layer and the workfunction layer. A top surface of a portion of the workfunction layer in contact with sidewalls of the spacer is a same distance from the gate dielectric layer as a top surface of a center portion of the work function layer. | 10-17-2013 |
20140065741 | Method and Apparatus for Accurate Die-to-Wafer Bonding - A method of light-emitting diode (LED) packaging includes coupling a number of LED dies to corresponding bonding pads on a sub-mount. A mold apparatus having concave recesses housing LED dies is placed over the sub-mount. The sub-mount, the LED dies, and the mold apparatus are heated in a thermal reflow process to bond the LED dies to the bonding pads. Each recess substantially restricts shifting of the LED die with respect to the bonding pad during the heating. | 03-06-2014 |
20140154848 | N/P METAL CRYSTAL ORIENTATION FOR HIGH-K METAL GATE Vt MODULATION - The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having a first region and a second region; a first gate stack of an n-type field-effect transistor (FET) in the first region; and a second gate stack of a p-type FET in the second region. The first gate stack includes a high k dielectric layer on the semiconductor substrate, a first crystalline metal layer in a first orientation on the high k dielectric layer, and a conductive material layer on the first crystalline metal layer. The second gate stack includes the high k dielectric layer on the semiconductor substrate, a second crystalline metal layer in a second orientation on the high k dielectric layer, and the conductive material layer on the second crystalline metal layer. | 06-05-2014 |
20140235053 | Methods of Forming Through Silicon Via Openings - A method of forming a through-silicon-via (TSV) opening includes forming a TSV opening through a substrate. A recast of a material of the substrate on sidewalls of the TSV opening is removed with a first chemical. The sidewalls of the TSV opening are cleaned with a second chemical by substantially removing a residue of the first chemical. | 08-21-2014 |
20140239323 | Method and Apparatus for Accurate Die-to-Wafer Bonding - A plurality of conductive pads are disposed on a substrate. A plurality of semiconductor dies are each disposed on a respective one of the conductive pads. A mold device is positioned over the substrate. The mold device contains a plurality of recesses that are each configured to accommodate a respective one of the semiconductor dies underneath. | 08-28-2014 |
20140252380 | Shadow Mask Assembly - A shadow mask assembly includes a securing assembly configured to hold a substrate that is configured to hold a plurality of dies. The securing assembly includes a number of guide pins and a shadow mask comprising holes for the guide pins, said holes allowing the guide pins freedom of motion in one direction. The securing assembly includes a number of embedded magnets configured to secure the shadow mask to the securing assembly. | 09-11-2014 |
20150083998 | LIGHT EMITTING DIODE AND METHOD OF FABRICATION THEREOF - A light-emitting diode (LED) element includes a substrate and a GaN layer formed on the substrate. The GaN layer includes a boundary layer including a surface of the GaN opposing the substrate. The surface has a micro-roughening texture and a macro-roughening texture. The boundary layer includes at least one of As, Si, P, Ge, C, B, F, N, Sb, and Xe ions. | 03-26-2015 |